I-F-Tile Interlaken Intel FPGA IP Design Example

Quick Start Guide

I-F-Tile Interlaken Intel® FPGA IP core inikeza ibhentshi lokuhlola lokulingisa. Isibample esekela ukuhlanganiswa nokuhlolwa kwehadiwe izotholakala ku-Intel Quartus® Prime Pro Edition software version 21.4. Uma udala i-ex designample, umhleli wepharamitha udala ngokuzenzakalelayo i filekudingekile ukulingisa, ukuhlanganisa, nokuhlola umklamo.
I-testbench kanye ne-design example isekela imodi ye-NRZ ne-PAM4 yamadivayisi we-F-tile. I-F-Tile Interlaken Intel FPGA IP core ikhiqiza i-design exampizinhlanganisela ezilandelayo ezisekelwayo zenani lemizila namazinga edatha.

I-IP Esekelwe Inhlanganisela Yenombolo Yemizila Nezilinganiso Zedatha
Izinhlanganisela ezilandelayo zisekelwa ku-Intel Quartus Prime Pro Edition software version 21.3. Zonke ezinye izinhlanganisela zizosekelwa enguqulweni ezayo ye-Intel Quartus Prime Pro Edition.

Inombolo Yemizila	I-Lane Rate (Gbps)
	6.25	10.3125	12.5	25.78125	53.125
4	Yebo	–	Yebo	Yebo	–
6	–	–	–	Yebo	Yebo
8	–	–	Yebo	Yebo	–
10	–	–	Yebo	Yebo	–
12	–	Yebo	Yebo	Yebo	–

Umfanekiso 1.Izinyathelo Zokuthuthukisa Zomklamo Example

Qaphela: I-Hardware Compilation and Testing izotholakala ku-Intel Quartus Prime Pro Edition ye-software version 21.4.
I-F-Tile Interlaken Intel FPGA IP core design example isekela izici ezilandelayo:

• I-TX yangaphakathi kuya kumodi ye-serial loopback ye-RX
• Yakha ngokuzenzakalelayo amaphakethe osayizi ongashintshi
• Amakhono okuhlola iphakethe ayisisekelo
• Ikhono lokusebenzisa Ikhonsoli Yesistimu ukuze usethe kabusha idizayini ngenjongo yokuhlola kabusha

Umfanekiso 2.High-level Block Diagram

Ulwazi Oluhlobene

• Umhlahlandlela Womsebenzisi we-F-Tile Interlaken Intel FPGA IP
• I-F-Tile Interlaken Intel FPGA IP Amanothi okukhishwa

Izingxenyekazi zekhompuyutha nezidingo zeSoftware

Ukuhlola i-example design, sebenzisa ihadiwe nesoftware elandelayo:

• Isoftware ye-Intel Quartus Prime Pro Edition engu-21.3
• Ikhonsoli Yesistimu
• Isifanisi Esisekelwe:
  • Ama-synopsy* VCS*
  • I-synopsy ye-VCS MX
  • Siemens* EDA ModelSim* SE noma Questa*

Qaphela:  Usekelo lwezingxenyekazi zekhompuyutha zomklamo example izotholakala ku-Intel Quartus Prime Pro Edition software version 21.4.

Ikhiqiza Umklamo

Umfanekiso 3. Inqubo

Landela lezi zinyathelo ukuze ukhiqize i-ex yokuklamaample kanye ne-testbench:

1. Kuhlelo lwe-Intel Quartus Prime Pro Edition, chofoza File ➤ Iseluleki Sephrojekthi Esisha sokudala iphrojekthi entsha ye-Intel Quartus Prime, noma chofoza File ➤ Vula Iphrojekthi ukuze uvule iphrojekthi ekhona ye-Intel Quartus Prime. Iwizadi ikutshela ukuthi ucacise idivayisi.
2. Cacisa i-Agilex yomndeni wedivayisi bese ukhetha idivayisi ene-F-Tile yomklamo wakho.
3. Kukhathalogi ye-IP, thola bese uchofoza kabili i-F-Tile Interlaken Intel FPGA IP. Iwindi elisha le-IP elihlukile liyavela.
4. Cacisa igama lezinga eliphezulu ngokuhlukahluka kwakho kwe-IP yangokwezifiso. Umhleli wepharamitha ugcina izilungiselelo zokuhlukahluka kwe-IP ku-a file okuthiwa .ip.
5. Chofoza okuthi KULUNGILE. Umhleli wepharamitha uyavela.

Umfanekiso 4. IsbampIthebhu Yokuklama

6. Kuthebhu ye-IP, cacisa imingcele yokuhluka kwakho kwe-IP core.
7. Ku-Example Design ithebhu, khetha inketho yokulingisa ukuze ukhiqize ibhentshi lokuhlola.
Qaphela: Inketho ye-Synthesis eye-hardware example design, ezotholakala ku-Intel Quartus Prime Pro Edition software version 21.4.
8. Ngefomethi ye-HDL Ekhiqiziwe, kokubili inketho ye-Verilog ne-VHDL iyatholakala.
9. Chofoza okuthi Khiqiza Isibample Design. Khetha ExampIwindi le-Design Directory liyavela.
10. Uma ufuna ukulungisa i-design exampindlela yohla lwemibhalo noma igama elisuka kokumisiwe okubonisiwe (ilk_f_0_example_design), phequlula endleleni entsha bese uthayipha umklamo omusha exampigama lesikhombi.
11. Chofoza OK.

Qaphela: Kumklamo we-F-Tile Interlaken Intel FPGA IP example, i-SystemPLL ifakwa ngokuzenzakalelayo, futhi ixhunywe ku-F-Tile Interlaken Intel FPGA IP core. Indlela ye-SystemPLL ye-hierarchy ku-design example yi:

example_design.test_env_inst.test_dut.dut.pll

I-SystemPLL ku-design example yabelana ngewashi lereferensi le-156.26 MHz njenge-Transceiver.

Ukwakheka Kwemibhalo

I-F-Tile Interlaken Intel FPGA IP core ikhiqiza okulandelayo files ye-design example:
Umfanekiso 5. Ukwakheka Kwemibhalo

Ithebula 2. I-Hardware Design Example File Izincazelo
Lezi files zikuample_installation_dir>/ilk_f_0_example_design directory.

File Amagama	Incazelo
example_design.qpf	Iphrojekthi ye-Intel Quartus Prime file.
example_design.qsf	Izilungiselelo zephrojekthi ye-Intel Quartus Prime file
example_design.sdc jtag_timing_template.sdc	I-Synopsys Design Constraint file. Ungakopisha futhi ulungisele umklamo wakho.
sysconsole_testbench.tcl	Okuyinhloko file ukuze ufinyelele Ikhonsoli Yesistimu

Qaphela: Usekelo lwezingxenyekazi zekhompuyutha zomklamo example izotholakala ku-Intel Quartus Prime Pro Edition software version 21.4.

Ithebula 3. Testbench File Incazelo

Lokhu file ikuample_installation_dir>/ilk_f_0_example_design/ example_design/rtl directory.

File Igama	Incazelo
top_tb.sv	I-testbench yezinga eliphezulu file.

Ithebula 4. Izikripthi ze-Testbench

Lezi files zikuample_installation_dir>/ilk_f_0_example_design/ example_design/testbench directory

File Igama	Incazelo
run_vcs.sh	Iskripthi se-Synopsy VCS sokuqalisa ibhentshi lokuhlola.
run_vcsmx.sh	Iskripthi se-Synopsy VCS MX sokuqalisa ibhentshi lokuhlola.
run_mentor.tcl	Iskripthi se-Siemens EDA ModelSim SE noma i-Questa sokuqalisa ibhentshi le-test.

Ukulingisa i-Design Example Testbench

Umfanekiso 6. Inqubo

Landela lezi zinyathelo ukuze ulingise i-testbench:

1. Emyalweni womyalo, shintshela kumkhombandlela wokulingisa we-testbench. Indlela yohla lwemibhalo ithiample_installation_dir>/example_design/ testbench.
2. Qalisa iskripthi sokulingisa sesifanisi esisekelwayo ozikhethele sona. Umbhalo uhlanganisa futhi uqhube ibhentshi lokuhlola kusifanisi. Iskripthi sakho kufanele sihlole ukuthi izibalo ze-SOP ne-EOP ziyafana ngemva kokuqedwa kokulinganisa.

Ithebula 5. Izinyathelo Zokuqalisa Ukulingisa

Isifanisi	Iziyalezo
I-VCS	Emugqeni womyalo, thayipha:   sh run_vcs.sh
I-VCS MX	Emugqeni womyalo, thayipha:   sh run_vcsmx.sh
ModelSim SE noma Questa	Emugqeni womyalo, thayipha:   vsim -do run_mentor.tcl Uma ukhetha ukulingisa ngaphandle kokuletha i-ModelSim GUI, thayipha:   vsim -c -do run_mentor.tcl

3. Hlaziya imiphumela. Ukulingisa okuphumelelayo kuthumela futhi kwamukele amaphakethe, futhi kubonisa "Ukuhlola KUPHASIWE".

Ibhentshi lokuhlola le-ex designample uqeda imisebenzi elandelayo:

• Iqinisekisa i-F-Tile Interlaken Intel FPGA IP core.
• Iphrinta isimo se-PHY.
• Ihlola ukuvumelanisa kwe-metaframe (SYNC_LOCK) nemingcele yegama (vimba) (WORD_LOCK).
• Ilinda imizila ngayinye ukuthi ikhiywe futhi iqondaniswe.
• Iqala ukudlulisa amaphakethe.
• Ihlola izibalo zephakethe:
  • CRC24 amaphutha
  • Ama-SOP
  • EOPs

Okulandelayo sampokukhiphayo kubonisa ukuqaliswa kokuhlolwa kokulingisa okuyimpumelelo:

Ukuhlanganisa i-Design Example

1. Qinisekisa i-exampi-design generation iqedile.
2. Kuhlelo lwe-Intel Quartus Prime Pro Edition, vula iphrojekthi ye-Intel Quartus Primeample_installation_dir>/example_design.qpf>.
3. Kumenyu Yokucubungula, chofoza Qala Ukuhlanganisa.

I-Design Example Incazelo

Umklamo exampI-le ibonisa ukusebenza kwe-Interlaken IP core.

I-Design Example Components

I-exampi-le design ixhuma amawashi ereferensi wesistimu kanye ne-PLL kanye nezingxenye zokuklama ezidingekayo. I-exampi-le design ilungisa i-IP core kumodi ye-loopback yangaphakathi futhi ikhiqize amaphakethe ku-IP core TX yokudlulisa idatha yomsebenzisi. I-IP core ithumela lawa maphakethe kumzila we-loopback wangaphakathi nge-transceiver.
Ngemuva kokuthi umamukeli oyinhloko we-IP ethole amaphakethe endleleni ye-loopback, icubungula amaphakethe e-Interlaken futhi iwathumele kusixhumi esibonakalayo sokudlulisa idatha yomsebenzisi we-RX. I-exampi-le design ihlola ukuthi amaphakethe atholiwe futhi adluliselwe afanayo.
I-F-Tile Interlaken Intel IP design example ihlanganisa izingxenye ezilandelayo:

1. I-F-Tile Interlaken Intel FPGA IP core
2. I-Packet Generator kanye ne-Packet Checker
3. Ireferensi ye-F-Tile kanye namawashi esistimu ye-PLL Intel FPGA IP core

Izimpawu Zokuxhumana

Ithebula 6. Idizayini Example Interface Signals

Igama Lembobo	Isiqondiso	Ububanzi (Amabhithi)	Incazelo
mgmt_clk	Okokufaka	1	Okokufaka kwewashi lesistimu. Imvamisa yewashi kufanele ibe ngu-100 MHz.
pll_ref_clk	Okokufaka	1	Iwashi lereferensi ye-Transceiver. Ishayela i-RX CDR PLL.
rx_pin	Okokufaka	Inombolo yemizila	Isamukeli sedatha yephinikhodi ye-SERDES.
tx_pin	Okukhiphayo	Inombolo yemizila	Dlulisa iphinikhodi yedatha ye-SERDES.
rx_pin_n(1)	Okokufaka	Inombolo yemizila	Isamukeli sedatha yephinikhodi ye-SERDES.
tx_pin_n(1)	Okukhiphayo	Inombolo yemizila	Dlulisa iphinikhodi yedatha ye-SERDES.
mac_clk_pll_ref	Okokufaka	1	Lesi siginali kufanele ishayelwe i-PLL futhi kufanele isebenzise umthombo wewashi ofanayo oshayela i-pll_ref_clk. Le siginali itholakala kuphela ekuhlukeni kwedivayisi yemodi ye-PAM4.
usr_pb_reset_n	Okokufaka	1	Ukuhlelwa kabusha kwesistimu.

(1) Itholakala kuphela ngezinhlobonhlobo ze-PAM4.

Inkampani ye-Intel Wonke Amalungelo Agodliwe. I-Intel, ilogo ye-Intel, nezinye izimpawu ze-Intel yizimpawu zokuthengisa ze-Intel Corporation noma izinkampani ezingaphansi kwayo. I-Intel iqinisekisa ukusebenza kwe-FPGA yayo kanye nemikhiqizo ye-semiconductor ekucacisweni kwamanje ngokuvumelana newaranti evamile ye-Intel, kodwa igodla ilungelo lokwenza izinguquko kunoma imiphi imikhiqizo namasevisi nganoma yisiphi isikhathi ngaphandle kwesaziso. I-Intel ayithathi mthwalo noma isikweletu esivele ngenxa yesicelo noma ukusetshenziswa kwanoma yiluphi ulwazi, umkhiqizo, noma isevisi echazwe lapha ngaphandle kwalapho okuvunyelwene ngakho ngokubhaliwe yi-Intel. Amakhasimende e-Intel ayelulekwa ukuthi athole inguqulo yakamuva yokucaciswa kwedivayisi ngaphambi kokuthembela kunoma yiluphi ulwazi olushicilelwe nangaphambi kokufaka ama-oda emikhiqizo noma amasevisi.
*Amanye amagama namabhrendi angafunwa njengempahla yabanye.

Bhalisa imephu

Qaphela:

• I-Design ExampIkheli lerejista liqala ngo-0x20** kuyilapho ikheli lerejista eliyinhloko le-Interlaken IP liqala ngo-0x10**.
• Ikheli lerejista le-F-tile PHY liqala ngo-0x30** kuyilapho ikheli lerejista le-F-tile FEC liqala ngo-0x40**. Irejista ye-FEC itholakala kuphela ngemodi ye-PAM4.
• Ikhodi yokufinyelela: RO—Funda Kuphela, kanye ne-RW—Funda/Bhala.
• Ikhonsoli yesistimu ifunda umklamo example irejista futhi ibike isimo sokuhlola esikrinini.

Ithebula 7. Idizayini Example Bhalisa imephu

I-Offset	Igama	Ukufinyelela	Incazelo
8h00	Igodliwe
8h01	Igodliwe
8h02	Ukusethwa kabusha kwesistimu ye-PLL	RO	Amabhithi alandelayo abonisa isicelo sokusetha kabusha uhlelo lwe-PLL futhi unike amandla inani: • Ibhithi [0] – sys_pll_rst_req • Ibhithi [1] – sys_pll_rst_en
8h03	Umzila we-RX uqondaniswe	RO	Ibonisa ukuqondanisa komzila we-RX.
8h04	IZWI likhiyiwe	RO	[NUM_LANES–1:0] – Ukuhlonza imingcele yegama (vimba).
8h05	Ukuvumelanisa kukhiyiwe	RO	[NUM_LANES–1:0] – Ukuvumelanisa i-Metaframe.
8'h06 - 8'h09	Isibalo samaphutha se-CRC32	RO	Ibonisa inani lamaphutha e-CRC32.
8h0a	Isibalo samaphutha se-CRC24	RO	Ibonisa inani lamaphutha e-CRC24.
8h0b	Isignali yokuchichima/Ukugeleza ngaphansi	RO	Amabhithi alandelayo abonisa: • I-Bit [3] – isignali ye-TX egelezayo • I-Bit [2] – isignali yokuchichima ye-TX • Ibhithi [1] – Isignali yokuchichima ye-RX
8h0c	Isibalo se-SOP	RO	Ibonisa inombolo ye-SOP.
8h0D	Ukubala kwe-EOP	RO	Ibonisa inombolo ye-EOP
8h0e	Isibalo samaphutha	RO	Ibonisa inombolo yamaphutha alandelayo: • Ukulahleka kwendlela • Igama lokulawula elingekho emthethweni • Iphethini yokufaka uzimele engekho emthethweni • I-SOP noma inkomba ye-EOP ayikho
8h0f	send_data_mm_clk	RW	Bhala oku-1 kuye kubhithi [0] ukuze unike amandla isignali yokukhiqiza.
8h10	Iphutha lokuhlola		Ibonisa iphutha lokuhlola. (Iphutha ledatha ye-SOP, iphutha lenombolo yesiteshi, kanye nephutha ledatha ye-PLD)
8h11	Ilokhi yesistimu ye-PLL	RO	I-Bit [0] ibonisa inkomba yokukhiya i-PLL.
8h14	Inani le-TX SOP	RO	Ibonisa inombolo ye-SOP ekhiqizwe ijeneretha yephakethe.
8h15	Inani eliphakeme kakhulu lama-TX EOP	RO	Ibonisa inombolo ye-EOP ekhiqizwe ijeneretha yephakethe.
8h16	Iphakethe eliqhubekayo	RW	Bhala 1 kuya kubhithi [0] ukuze unike amandla iphakethe eliqhubekayo.
waqhubeka...

I-Offset	Igama	Ukufinyelela	Incazelo
8h39	Isibalo samaphutha e-ECC	RO	Ibonisa inombolo yamaphutha e-ECC.
8h40	I-ECC ilungise inani lamaphutha	RO	Ibonisa inombolo yamaphutha e-ECC alungisiwe.
8h50	tile_tx_rst_n	WO	Ithayela lisethwe kabusha libe yi-SRC ye-TX.
8h51	ithayela_rx_rst_n	WO	Ukusetha kabusha kwethayela ku-SRC ku-RX.
8h52	tile_tx_rst_ack_n	RO	Imvume yokusetha kabusha ithayela evela ku-SRC ye-TX.
8h53	tile_rx_rst_ack_n	RO	Imvume yokusetha kabusha ithayela evela ku-SRC ye-RX.

Setha kabusha

Kumongo we-F-Tile Interlaken Intel FPGA IP, uqala ukusetha kabusha (reset_n=0) futhi ubambe kuze kube yilapho umgogodla we-IP ubuyisela ukuvuma kokusetha kabusha (reset_ack_n=0). Ngemva kokususwa kokusetha kabusha (reset_n=1), ukuvuma kokusetha kabusha kubuyela esimweni sako sokuqala.
(setha kabusha_i-ack_n=1). Kumklamo exampLe, irejista ye-rst_ack_sticky ibamba ukugomela kokusetha kabusha bese icupha ukususwa kokusetha kabusha (setha kabusha_n=1). Ungasebenzisa ezinye izindlela ezihambisana nezidingo zakho zokuklama.

Okubalulekile: Kunoma isiphi isimo lapho kudingeka khona i-serial loopback yangaphakathi, kufanele ukhulule i-TX ne-RX ye-F-tile ngokuhlukana ngokulandelana ngendlela ethile. Bheka kumbhalo wekhonsoli yesistimu ukuze uthole ulwazi olwengeziwe.

Umfanekiso 7.Setha kabusha Ukulandelana Kumodi ye-NRZ

Umfanekiso 8.Setha kabusha Ukulandelana Kumodi ye-PAM4

I-F-Tile Interlaken Intel FPGA IP Design Example Izingobo zomlando zomhlahlandlela womsebenzisi

Uma inguqulo ye-IP eyinhloko ingekho ohlwini, umhlahlandlela womsebenzisi wenguqulo yangaphambilini ye-IP iyasebenza.

Inguqulo ye-Intel Quartus Prime	Inguqulo ye-IP Core	Umhlahlandlela Womsebenzisi
21.2	2.0.0	I-F-Tile Interlaken Intel FPGA IP Design Example Umhlahlandlela Womsebenzisi

Umlando Wokubuyekeza Idokhumenti we-F-Tile Interlaken Intel FPGA IP Design Example Umhlahlandlela Womsebenzisi

Inguqulo Yedokhumenti	Inguqulo ye-Intel Quartus Prime	Inguqulo ye-IP	Izinguquko
2021.10.04	21.3	3.0.0	• Usekelo olungeziwe lwenhlanganisela entsha yesilinganiso somzila. Ukuze uthole ukwaziswa okwengeziwe, bheka Ithebula: Inhlanganisela Esekelwe I-IP Yenombolo Yemizila Nezinga Ledatha. • Kubuyekezwe uhlu lwezifanisi olusekelwayo esigabeni: Izingxenyekazi zekhompuyutha nezidingo zeSoftware. • Kwengezwe amarejista amasha okusetha kabusha esigabeni: Bhalisa imephu.
2021.06.21	21.2	2.0.0	Ukukhishwa kokuqala.

Amadokhumenti / Izinsiza

intel F-Tile Interlaken Intel FPGA IP Design Example [pdf] Umhlahlandlela Womsebenzisi I-F-Tile Interlaken Intel FPGA IP Design Example, F-Tile, Interlaken Intel FPGA IP Design Example, Intel FPGA IP Design Example, IP Design Example, Design Example

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