I-intel Interlaken 2nd Gen FPGA IP Amanothi okukhishwa
I-Interlaken (2nd Generation) Intel® FPGA IP Release Notes
Uma inothi lokukhishwa lingatholakali kunguqulo ethile ye-IP core, i-IP core ayinazo izinguquko kuleyo nguqulo. Ukuze uthole ulwazi mayelana nokukhishwa kwesibuyekezo se-IP kuze kufike ku-v18.1, bheka Amanothi Okukhishwa Kwesibuyekezo Se-Intel Quartus Prime Design Suite. Izinguqulo ze-Intel® FPGA IP zifana nezinguqulo zesofthiwe ye-Intel Quartus® Prime Design Suite kuze kube yi-v19.1. Iqala ku-Intel Quartus Prime Design Suite software version 19.2, i-Intel FPGA IP inohlelo olusha lwenguqulo. Inombolo ye-Intel FPGA IP (XYZ) ingashintsha ngenguqulo ngayinye yesofthiwe ye-Intel Quartus Prime. Ushintsho ku:
- U-X ukhombisa ukubuyekezwa okukhulu kwe-IP. Uma ubuyekeza isofthiwe ye-Intel Quartus Prime, kufanele uvuselele i-IP.
- U-Y ukhombisa ukuthi i-IP ihlanganisa izici ezintsha. Khiqiza kabusha i-IP yakho ukuze ufake lezi zici ezintsha.
- U-Z ukhombisa ukuthi i-IP ihlanganisa izinguquko ezincane. Khiqiza kabusha i-IP yakho ukuze ufake lezi zinguquko.
- I-Intel Quartus Prime Design Suite Update Notes Release Notes
- Interlaken (2nd Generation) Intel FPGA IP User Guide
- I-Errata ye-Interlaken (2nd Generation) Intel FPGA IP ku-Knowledge Base
- I-Interlaken (2nd Generation) Intel Stratix 10 FPGA IP Design Example Umhlahlandlela Womsebenzisi
- I-Interlaken (2nd Generation) Intel Agilex FPGA IP Design Example Umhlahlandlela Womsebenzisi
- Isingeniso se-Intel FPGA IP Cores
I-Interlaken (2nd Generation) Intel FPGA IP v20.0.0
Ithebula 1. v20.0.0 2020.10.05
| Inguqulo ye-Intel Quartus Prime | Incazelo | Umthelela |
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20.3 |
Usekelo olungeziwe lwezinga ledatha elingu-25.78125 Gbps. | - |
| Kushintshwe ukusekelwa kwezilinganiso zedatha kusuka ku-25.3 Gbps kuya ku-25.28 Gbps naku-25.8 Gbps kuya ku-25.78125 Gbps. |
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Inkampani ye-Intel Wonke Amalungelo Agodliwe. I-Intel, ilogo ye-Intel, nezinye izimpawu ze-Intel yizimpawu zokuthengisa ze-Intel Corporation noma izinkampani ezingaphansi kwayo. I-Intel iqinisekisa ukusebenza kwe-FPGA yayo kanye nemikhiqizo ye-semiconductor ekucacisweni kwamanje ngokuvumelana newaranti evamile ye-Intel, kodwa igodla ilungelo lokwenza izinguquko kunoma imiphi imikhiqizo namasevisi nganoma yisiphi isikhathi ngaphandle kwesaziso. I-Intel ayithathi mthwalo noma isikweletu esivele ngenxa yesicelo noma ukusetshenziswa kwanoma yiluphi ulwazi, umkhiqizo, noma isevisi echazwe lapha ngaphandle kwalapho okuvunyelwene ngakho ngokubhaliwe yi-Intel. Amakhasimende e-Intel ayelulekwa ukuthi athole inguqulo yakamuva yokucaciswa kwedivayisi ngaphambi kokuthembela kunoma yiluphi ulwazi olushicilelwe nangaphambi kokufaka ama-oda emikhiqizo noma amasevisi.
Amanye amagama namabhrendi angafunwa njengempahla yabanye.
I-Interlaken (2nd Generation) Intel FPGA IP v19.3.0
Ithebula 2. v19.3.0 2020.06.22
| Inguqulo ye-Intel Quartus Prime | Incazelo | Umthelela |
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19.3.0 |
I-IP manje isekela isici se-Interlaken Look-aside. | - |
| Kwengezwe okusha Nika amandla imodi ye-Interlaken Look-aside ipharamitha kusihleli sepharamitha ye-IP. | Ungamisa i-IP kumodi ye-Interlaken Look-aside. | |
| Ukukhetha imodi yokudlulisa ipharamitha isusiwe enguqulweni yamanje ye-Intel Quartus Prime software. |
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| Kwengezwe ukusekelwa kwesilinganiso sedatha esingu-12.5 Gbps senani lemizila engu-10 ku-H- tile kanye ne-E-tile (imodi ye-NRZ) ukuhluka okuyinhloko kwe-IP. |
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| Kukhishwe amasiginali alandelayo ku-IP:
• idatha_ye-rx_pma • tx_pma_data • ngilambile • ngilambile |
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| Kwengezwe amasiginali amasha alandelayo:
• sop_cntr_inc1 • eop_cntr_inc1 • rx_xcoder_uncor_feccw • itx_ch0_xon • irx_ch0_xon • itx_ch1_xon • irx_ch1_xon • i-itx_valid • irx_valid • ayisebenzi • irx_idle • itx_ctrl • itx_credit • irx_credit |
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| Kususwe ama-offset amabili alandelayo kumephu yokubhalisa:
• 16'h40- TX_READY_XCVR • 16'h41- RX_READY_XCVR |
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| Ukuhlolwa kwezingxenyekazi zekhompuyutha zomklamo exampi-le isiyatholakala kumadivayisi we-Intel Agilex™. | Ungahlola i-ex designampochungechungeni lwe-Intel Agilex F-Transceiver-SoC Development Kit. | |
| Ungashintsha isilinganiso sedatha kanye nemvamisa yewashi lereferensi ye-transceiver ibe amanani ahluke kancane esibonelo sakho se-Interlaken (2nd Generation) IP eqondise i-Intel Stratix® 10 H-tile noma idivayisi ye-E-tile. Bheka le KDB ukuze uthole ulwazi lokuthi ungashintsha kanjani izinga ledatha. |
Ungenza ngokwezifiso amanani edatha kuye ngamathayili. |
I-Interlaken (2nd Generation) Intel FPGA IP v19.2.1
Ithebula 3. v19.2.1 2019.09.27
| Inguqulo ye-Intel Quartus Prime | Incazelo | Umthelela |
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19.3 |
Ukukhishwa esidlangalaleni kwamadivayisi e-Intel Agilex anama-E-tile transceivers. | - |
| Iqanjwe kabusha i-Interlaken (2nd Generation) Intel Stratix 10 FPGA IP yaba yi-Interlaken (2nd Generation) Intel FPGA IP |
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I-Interlaken (2nd Generation) Intel Stratix 10 FPGA IP v18.1 Update 1
Ithebula 4. Inguqulo 18.1 Buyekeza 1 2019.03.15
| Incazelo | Umthelela |
| Kwengezwe ukusekelwa kwemodi yamasegimenti amaningi. | - |
| Kwengeziwe Inombolo Yezingxenye ipharamitha. | - |
| • Ukwesekwa okwengeziwe komzila kanye nezinhlanganisela zesilinganiso sedatha ngendlela elandelayo:
- Ngamadivayisi we-Intel Stratix 10 L-tile: • Imizila emi-4 enezilinganiso zomzila ongu-12.5/25.3/25.8 Gbps • Imizila engu-8 enezilinganiso zomzila we-12.5 Gbps - Ngamadivayisi we-Intel Stratix 10 H-tile: • Imizila emi-4 enezilinganiso zomzila ongu-12.5/25.3/25.8 Gbps • Imizila emi-8 enezilinganiso zomzila ongu-12.5/25.3/25.8 Gbps • Imizila engu-10 enezilinganiso zomzila ongu-25.3/25.8 Gbps - Okwamadivaysi e-Intel Stratix 10 E-tile (NRZ): • Imizila emi-4 enezilinganiso zomzila ongu-6.25/12.5/25.3/25.8 Gbps • Imizila emi-8 enezilinganiso zomzila ongu-12.5/25.3/25.8 Gbps • Imizila engu-10 enezilinganiso zomzila ongu-25.3/25.8 Gbps • Imizila engu-12 enesilinganiso somzila we-10.3125 Gbps |
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| • Kwengezwe amasiginali wokuxhumana wokudlulisa amasha alandelayo:
— itx_eob1 — itx_eopbits1 — itx_chan1 |
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| • Kwengezwe amasiginali wokusebenzelana womamukeli omusha olandelayo:
- irx_eob1 - irx_eopbits1 - irx_chan1 - irx_err1 - irx_err |
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I-Interlaken (2nd Generation) Intel Stratix 10 FPGA IP v18.1
Ithebula 5. Inguqulo 18.1 2018.09.10
| Incazelo | Umthelela | Amanothi |
| Iqambe kabusha ithayela ledokhumenti ngokuthi I-Interlaken (2nd Generation) Intel Stratix 10 FPGA IP User Guide |
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| Kwengezwe imodeli yokulingisa ye-VHDL kanye nosekelo lwe-testbench lwe-Interlaken (2nd Generation) IP core. |
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| Kwengezwe amarejista amasha alandelayo kumongo we-IP: | ||
| • TX_READY_XCVR | ||
| • RX_READY_XCVR
• ILKN_FEC_XCODER_TX_ILLEGAL_ STATE |
- | Lawa marejista atholakala kuphela ezinhlobonhlobo zedivayisi ye-Intel Stratix 10 E-Tile. |
| • ILKN_FEC_XCODER_RX_ILLEGAL_ STATE |
I-Interlaken (2nd Generation) Intel FPGA IP v18.0.1
Ithebula 6. Inguqulo 18.0.1 Julayi 2018
| Incazelo | Umthelela | Amanothi |
| Ukwesekwa okwengeziwe kwamadivayisi we-Intel Stratix 10 anama-transceivers e-E-Tile. |
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| Kwengezwe ukusekelwa kwesilinganiso sedatha esingu-53.125 Gbps kumadivayisi e-Intel Stratix 10 E-Tile kumodi ye-PAM4. |
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| Kungezwe isignali yewashi mac_clkin yamadivayisi we-Intel Stratix 10 E-Tile kumodi ye-PAM4 |
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I-Interlaken (2nd Generation) Intel FPGA IP v18.0
Ithebula 7. Inguqulo 18.0 May 2018
| Incazelo | Umthelela | Amanothi |
| Iqanjwe kabusha i-Interlaken IP core (2nd Generation) yaba yi-Interlaken (2nd Generation) Intel FPGA IP njengokusho kwe-Intel kabusha. |
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| Kwengezwe ukusekelwa kwesilinganiso sedatha okungu-25.8 Gbps enani lemizila 6 no-12. |
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| Usekelo olungeziwe lwe-Cadence Xcelium* Isifanisi esihambisanayo. |
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I-Interlaken IP Core (isizukulwane sesibili) v2
Ithebula 8. Inguqulo 17.1 November 2017
| Incazelo | Umthelela | Amanothi |
| Ukukhishwa kokuqala ku-Intel FPGA IP Library. | - | - |
Ulwazi Oluhlobene
I-Interlaken IP Core (isizukulwane sesibili) Umhlahlandlela Womsebenzisi
I-Interlaken (2nd Generation) Intel FPGA IP User Guide Archives
| Inguqulo ye-Quartus | Inguqulo ye-IP Core | Umhlahlandlela Womsebenzisi |
| 20.2 | 19.3.0 | I-Interlaken (2nd Generation) FPGA IP User Guide |
| 19.3 | 19.2.1 | I-Interlaken (2nd Generation) FPGA IP User Guide |
| 19.2 | 19.2 | I-Interlaken (2nd Generation) FPGA IP User Guide |
| 18.1.1 | 18.1.1 | I-Interlaken (2nd Generation) Intel Stratix 10 FPGA IP User Guide |
| 18.1 | 18.1 | I-Interlaken (2nd Generation) Intel Stratix 10 FPGA IP User Guide |
| 18.0.1 | 18.0.1 | I-Interlaken (2nd Generation) FPGA IP User Guide |
| 18.0 | 18.0 | Interlaken (2nd Generation) Intel FPGA IP User Guide |
| 17.1 | 17.1 | I-Interlaken IP Core (isizukulwane sesibili) Umhlahlandlela Womsebenzisi |
Izinguqulo ze-IP ziyefana nezinguqulo zesofthiwe ye-Intel Quartus Prime Design Suite kufika ku-v19.1. Kusukela ku-Intel Quartus Prime Design Suite software version 19.2 noma kamuva, ama-IP cores anohlelo olusha lwenguqulo ye-IP. Uma inguqulo ye-IP eyinhloko ingekho ohlwini, umhlahlandlela womsebenzisi wenguqulo yangaphambilini ye-IP iyasebenza.
Amadokhumenti / Izinsiza
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I-intel Interlaken 2nd Gen FPGA IP Amanothi okukhishwa [pdf] Iziyalezo I-Interlaken 2nd Gen FPGA IP Amanothi, Interlaken 2nd Gen, FPGA IP Amanothi okukhishwa |
