I-Intel® FPGA P-Tile Avalon ®
Ukusakaza IP ye-PCI Express*
I-Design Example Umhlahlandlela Womsebenzisi
Ibuyekezelwe i-Intel®
I-Quartus® Prime Design Suite: 21.3
Inguqulo ye-IP: 6.0.0
Umhlahlandlela Womsebenzisi

I-Design Example Incazelo

1.1. Incazelo Esebenzayo Ye-Programmed Input/Output (PIO) Design Example

I-PIO design exampi-le yenza ukudluliselwa kwememori isuka kusicubunguli somsingathi iye kudivayisi eqondiwe. Kulesi exampLe, iphrosesa yokusingatha icela i-MemRd yedword elilodwa kanye ne-emWr
Ama-TLPs.
I-PIO design example idala ngokuzenzakalelayo i files kuyadingeka ukulingisa nokuhlanganisa ku-Intel Prime software. Umklamo example ihlanganisa anhlobonhlobo nemingcele. Kodwa-ke, ayifaki wonke amapharamitha angenzeka we-P-Tile Hard IP ye-PCIe.
Lo mklamo example ihlanganisa izingxenye ezilandelayo:

• Ukuhluka okukhiqiziwe kwe-P-Tile Avalon Streaming Hard IP Endpoint (DUT) namapharamitha owashilo. Le ngxenye ishayela idatha ye-TLP etholiwe kuhlelo lokusebenza lwe-PIO
• Ingxenye ye-PIO Application (APPS), eyenza ukuhumusha okudingekayo phakathi kwe-PCI Express TLPs kanye ne-Avalon-MM elula ibhala futhi ifundele kumemori ye-onchip.
• Ingxenye ye-on-chip memory (MEM). Okwe-1x16 design exampLe, imemori ye-on-chip iqukethe ibhulokhi yememori eyodwa engu-16 KB. Okwe-2x8 design exampLe, imemori ye-on-chip iqukethe amabhulokhi ememori amabili angu-16 KB.
• Setha kabusha i-IP yokukhishwa: Le IP ibamba isifunda sokulawula sisethwe kabusha kuze kube yilapho idivayisi isingene ngokugcwele kumodi yomsebenzisi. I-FPGA igomela ngokukhiphayo kwe-INIT_DONE ukuze ibonise ukuthi idivayisi ikumodi yomsebenzisi. I-IP Yokukhipha Kabusha ikhiqiza inguqulo ehlanekezelwe yesiginali yangaphakathi ye-INIT_DONE ukuze udale okukhiphayo okungu-nINIT_DONE ongakusebenzisa edizayini yakho.Isiginali ye-nINIT_DONE iphezulu kuze kube yilapho yonke idivayisi ingena kumodi yomsebenzisi. Ngemva kokugomela kwe-nINIT_DONE (okuphansi), yonke ingqondo ikumodi yomsebenzisi futhi isebenza ngokujwayelekile. Ungasebenzisa isignali ye-nINIT_DONE ngendlela eyodwa kwezilandelayo:
  • Ukufaka ukusetha kabusha kwangaphandle noma kwangaphakathi.
  • Ukufaka okokufaka kokusetha kabusha ku-transceiver kanye nama-I/O PLL.
  • Ukufaka amandla okubhala amabhulokhi edizayini njengamabhulokhi ememori ashumekiwe, umshini wombuso, namarejista okushintsha.
  • Ukuze ushayele ngokuvumelanisa irejista setha kabusha izimbobo zokufaka kumklamo wakho.

Ibhentshi le-testbench lokulingisa liqinisekisa i-ex yedizayini ye-PIOample kanye ne-Root Port BFM ukuze kuxhunywe ne-Endpoint eqondiwe.
Inkampani ye-Intel Wonke Amalungelo Agodliwe. I-Intel, ilogo ye-Intel, nezinye izimpawu ze-Intel yizimpawu zokuthengisa ze-Intel Corporation noma izinkampani ezingaphansi kwayo. I-Intel iqinisekisa ukusebenza kwe-FPGA yayo kanye nemikhiqizo yesemiconductor ekucacisweni kwamanje ngokuvumelana newaranti evamile ye-Intel, kodwa igodla ilungelo lokwenza izinguquko kunoma imiphi imikhiqizo namasevisi nganoma yisiphi isikhathi ngaphandle kwesaziso. I-Intel ayithathi mthwalo noma isikweletu esivele ngenxa yesicelo noma ukusetshenziswa kwanoma yiluphi ulwazi, umkhiqizo, noma isevisi echazwe lapha ngaphandle kwalapho okuvunyelwene ngakho ngokubhaliwe yi-Intel. Amakhasimende e-Intel ayelulekwa ukuthi athole inguqulo yakamuva yokucaciswa kwedivayisi ngaphambi kokuthembela kunoma yiluphi ulwazi olushicilelwe nangaphambi kokufaka ama-oda emikhiqizo noma amasevisi. *Amanye amagama namabhrendi angafunwa njengempahla yabanye.
I-ISO 9001:2015 Ibhalisiwe
Umfanekiso 1. Vimba Umdwebo Womklami Wenkundla I-PIO 1×16 Design Exampfuthi Simulation Testbench

Umfanekiso 2. Vimba Umdwebo Womklami Wenkundla I-PIO 2×8 Design Exampfuthi Simulation Testbench

Uhlelo lokuhlola lubhalela futhi lufunde idatha kusukela endaweni efanayo kumemori eku-chip. Iqhathanisa idatha efundiwe nomphumela olindelekile. Uhlolo lubika ukuthi, “Ukulingisa kumisiwe ngenxa yokuqedwa ngempumelelo” uma engekho amaphutha enzekayo. I-P-Tile Avalon
Idizayini yokusakaza-bukhoma example isekela ukucupha okulandelayo:

• Gen4 x16 Indawo yokugcina
• Gen3 x16 Indawo yokugcina
• Gen4 x8x8 Indawo yokugcina
• Gen3 x8x8 Indawo yokugcina

Qaphela: Ibhentshi lokulingisa le-PCIe x8x8 PIO design exampi-le ilungiselelwe isixhumanisi esisodwa se-PCIe x8 nakuba umklamo wangempela usebenzisa izixhumanisi ezimbili ze-PCIe x8.
Qaphela: Lo mklamo exampi-le isekela kuphela izilungiselelo ezizenzakalelayo Kumhleli Wepharamitha ye-P-tile Avalon Streaming IP ye-PCI Express.
Umfanekiso 3. Okuqukethwe Kwesistimu Yokuklama Ipulatifomu ye-P-Tile Avalon yokusakaza nge-PCI Express 1×16 PIO Design Example
I-Platform Designer ikhiqiza lo mklamo kuze kufike ezinhlobonhlobo ze-Gen4 x16.

Umfanekiso 4. Okuqukethwe Kwesistimu Yokuklama Ipulatifomu ye-P-Tile Avalon yokusakaza nge-PCI Express 2×8 PIO Design Example
I-Platform Designer ikhiqiza lo mklamo kuze kufike ezinhlobonhlobo ze-Gen4 x8x8.

1.2. Incazelo Esebenzayo Ye-Single Root I/O Virtualization (SR-IOV) Design Example
Umklamo we-SR-IOV exampi-le yenza ukudluliselwa kwememori isuka kusicubunguli somsingathi iye kudivayisi eqondiwe. Isekela ama-PF amabili nama-VF angama-32 iPF ngayinye.
Umklamo we-SR-IOV example idala ngokuzenzakalelayo i filekudingekile ukulingisa nokuhlanganisa ku-Intel Quartus Prime software. Ungalanda umklamo ohlanganisiwe ku
i-Intel Stratix® 10 DX Development Kit noma i-Intel Agilex™ Development Kit.
Lo mklamo example ihlanganisa izingxenye ezilandelayo:

• Ukuhluka okukhiqiziwe kwe-P-Tile Avalon Streaming (Avalon-ST) IP Endpoint (DUT) namapharamitha owashilo. Le ngxenye ishayela idatha ye-TLP etholiwe kuhlelo lokusebenza lwe-SR-IOV.
• Ingxenye ye-SR-IOV Application (APPS), eyenza ukuhumusha okudingekayo phakathi kwe-PCI Express TLPs kanye ne-Avalon-ST elula ibhala futhi ifunde kumemori eku-chip. Okwengxenye ye-SR-IOV APPS, i-TLP efundwa yimemori izokhiqiza Ukuqedela ngedatha.
  • Okomklamo we-SR-IOV example enama-PF amabili kanye nama-VF angama-32 i-PF ngayinye, kunezindawo zenkumbulo ezingama-66 umklamo exampngingakwazi ukufinyelela. Ama-PF amabili angafinyelela izindawo ezimbili zenkumbulo, kuyilapho ama-VF angama-64 (2 x 32) angafinyelela izindawo zenkumbulo ezingama-64.
• I-IP yokukhishwa kabusha.
  Ibhentshi lesivivinyo sokulingisa liqinisekisa i-ex yedizayini ye-SR-IOVample kanye ne-Root Port BFM ukuze kuxhunywe ne-Endpoint eqondiwe.

Umfanekiso 5. Vimba Umdwebo Womklami Wenkundla SR-IOV 1×16 Design Exampfuthi Simulation Testbench

Umfanekiso 6. Vimba Umdwebo Womklami Wenkundla SR-IOV 2×8 Design Exampfuthi Simulation Testbench

Uhlelo lokuhlola lubhalela futhi lufunde idatha emuva endaweni efanayo kumemori ye-chip kuwo wonke ama-PF angu-2 nama-VF angu-32 i-PF ngayinye. Iqhathanisa idatha efundiwe nokulindelwe
umphumela. Uhlolo lubika ukuthi, “Ukulingisa kumisiwe ngenxa yokuqedwa ngempumelelo” uma engekho amaphutha enzekayo.
Umklamo we-SR-IOV example isekela ukucupha okulandelayo:

• Gen4 x16 Indawo yokugcina
• Gen3 x16 Indawo yokugcina
• Gen4 x8x8 Indawo yokugcina
• Gen3 x8x8 Indawo yokugcina

Umfanekiso 7. Okuqukethwe Kwesistimu Yokuklama Ipulatifomu ye-P-Tile Avalon-ST ene-SR-IOV ye-PCI Express 1×16 Design Example

Umfanekiso 8. Okuqukethwe Kwesistimu Yokuklama Ipulatifomu ye-P-Tile Avalon-ST ene-SR-IOV ye-PCI Express 2×8 Design Example

Quick Start Guide

Usebenzisa isoftware ye-Intel Quartus Prime, ungakha i-design ye-I/O (PIO) ehleliweample le-Intel FPGA P-Tile Avalon-ST Hard IP ye-PCI Express* IP core. I-ex yedizayini ekhiqiziweampi-le ibonisa amapharamitha owacacisayo. I-PIO example idlulisela idatha isuka kusicubunguli somsingathi iye kudivayisi eqondiwe. Ilungele izinhlelo zokusebenza zomkhawulokudonsa ophansi. Lo mklamo example idala ngokuzenzakalelayo i filekudingekile ukulingisa nokuhlanganisa ku-Intel Quartus Prime software. Ungalanda idizayini ehlanganisiwe ku-FPGA Development Board yakho. Ukuze udawunilode ku-hardware yangokwezifiso, buyekeza Izilungiselelo Eziyinhloko ze-Intel Quartus File (.qsf) enephinikhodi efanele imisebenzi . Umfanekiso 9. Izinyathelo Zokuthuthukisa Zomklamo Example

Inkampani ye-Intel Wonke Amalungelo Agodliwe. I-Intel, ilogo ye-Intel, nezinye izimpawu ze-Intel yizimpawu zokuthengisa ze-Intel Corporation noma izinkampani ezingaphansi kwayo. I-Intel iqinisekisa ukusebenza kwe-FPGA yayo kanye nemikhiqizo yesemiconductor ekucacisweni kwamanje ngokuvumelana newaranti evamile ye-Intel, kodwa igodla ilungelo lokwenza izinguquko kunoma imiphi imikhiqizo namasevisi nganoma yisiphi isikhathi ngaphandle kwesaziso. I-Intel ayithathi mthwalo noma isikweletu esivele ngenxa yesicelo noma ukusetshenziswa kwanoma yiluphi ulwazi, umkhiqizo, noma isevisi echazwe lapha ngaphandle kwalapho okuvunyelwene ngakho ngokubhaliwe yi-Intel. Amakhasimende e-Intel ayelulekwa ukuthi athole inguqulo yakamuva yokucaciswa kwedivayisi ngaphambi kokuthembela kunoma yiluphi ulwazi olushicilelwe nangaphambi kokufaka ama-oda emikhiqizo noma amasevisi. *Amanye amagama namabhrendi angafunwa njengempahla yabanye.
I-ISO 9001:2015 Ibhalisiwe
2.1. Ukwakheka Kwemibhalo
Umfanekiso 10. Ukwakheka Kwemibhalo Yomklamo Okhiqiziwe Example

2.2. Ukukhiqiza I-Design Example
Umfanekiso 11. Inqubo

1. Kuhlelo lwe-Intel Quartus Prime Pro Edition, dala iphrojekthi entsha (File ➤ Iselekeleli Sephrojekthi Esisha).
2. Cacisa Uhla Lwemibhalo, Igama, kanye Nebhizinisi Lezinga eliphezulu.
3. Ohlotsheni Lwephrojekthi, yamukela inani elizenzakalelayo, Iphrojekthi Engenalutho. Chofoza Okulandelayo.
4. Okwengeza Files chofoza Okulandelayo.
5. Ngezilungiselelo Zomndeni, Idivayisi Nebhodi ngaphansi Komndeni, khetha i-Intel Agilex noma i-Intel Stratix 10.
6. Uma ukhethe i-Intel Stratix 10 esinyathelweni sokugcina, khetha i-Stratix 10 DX kumenyu yokudonsela phansi Yedivayisi.
7. Khetha Idivayisi Eqondiwe yomklamo wakho.
8. Chofoza okuthi Qeda.
9. Kukhathalogi ye-IP thola bese wengeza i-Intel P-Tile Avalon-ST Hard IP ye-PCI Express.
10. Ebhokisini Lengxoxo Elihlukile Le-IP Entsha, cacisa igama le-IP yakho. Chofoza okuthi Dala.
11. Kumathebhu Izilungiselelo Zezinga Eliphezulu kanye ne-PCIe* Izilungiselelo, cacisa amapharamitha wokuhluka kwakho kwe-IP. Uma usebenzisa i-SR-IOV design example, yenza lezi zinyathelo ezilandelayo ukuze unike amandla i-SR-IOV:
    a. Kuthebhu ye-PCIe* Yedivayisi ngaphansi kwethebhu ye-PCIe* PCI Express / PCI Amakhono, qoka ibhokisi elithi Vumela imisebenzi yomzimba eminingi.
    b. Kuthebhu ye-PCIe* I-Multifunction kanye ne-SR-IOV System Settings, qoka ibhokisi elithi Vumela ukusekelwa kwe-SR-IOV futhi ucacise inani lama-PF nama-VF. Ngokulungiselelwa kwe-x8, qoka amabhokisi okuthi Nika amandla imisebenzi eminingi ebonakalayo bese Unika amandla ukusekela kwe-SR-IOV kukho kokubili amathebhu e-PCIe0 kanye ne-PCIe1.
    c. Kuthebhu ye-PCIe* MSI-X ngaphansi kwethebhu ye-PCIe* PCI Express / PCI Amakhono, nika amandla isici se-MSI-X njengoba kudingeka.
    d. Kuthebhu Yokubhalisa Ikheli Lesisekelo se-PCIe*, nika amandla i-BAR0 kukho kokubili i-PF ne-VF.
    e. Ezinye izilungiselelo zepharamitha azisekelwa kulesi sici somklamoample.
12. Ku-Example Designs ithebhu, khetha okulandelayo:
    a. Ngesibample Design Files, vula izinketho zokulingisa ne-Synthesis.
    Uma ungazidingi lezi simulation noma synthesis files, ukushiya i(izi)nketho ezihambisanayo icishiwe kunciphisa kakhulu i-example design sizukulwane isikhathi.
    b. Ngefomethi ye-HDL Ekhiqiziwe, i-Verilog kuphela etholakala ekukhishweni kwamanje.
    c. Ngekhithi Yokuthuthukisa Okuqondisiwe, khetha i-Intel Stratix 10 DX P-Tile ES1 FPGA Development Kit, i-Intel Stratix 10 DX P-Tile Production FPGA Development Kit noma i-Intel Agilex F-Series P-Tile ES0 FPGA Development Kit.
    13. Khetha Khiqiza Isibample Design ukwakha i-ex yokuklamaample ukuthi ungakwazi ukulingisa futhi ulande hardware. Uma ukhetha elinye lamabhodi okuthuthukisa i-P-Tile, idivayisi ekulelo bhodi isula idivayisi ekhethwe ngaphambilini kuphrojekthi ye-Intel Quartus Prime uma izisetshenziswa zihlukile. Lapho ukwaziswa kukucela ukuthi ucacise uhla lwemibhalo lwe-ex yakhoample design, ungamukela uhla lwemibhalo oluzenzakalelayo, ./intel_pcie_ptile_ast_0_example_design, noma khetha olunye uhla lwemibhalo.
    Umfanekiso 12. ExampIthebhu Yemiklamo
    
13. Chofoza okuthi Qeda. Ungagcina i-.ip yakho file uma utshelwa, kodwa akudingekile ukuthi ukwazi ukusebenzisa i-exampumklamo.
14. Vula i-example phrojekthi yokuklama.
15. Hlanganisa i-example phrojekthi yokuklama ukukhiqiza i-.sof file nge-ex epheleleample design. Lokhu file yilokho okulanda ebhodini ukuze wenze ukuqinisekiswa kwehadiwe.
16. Vala i-ex yakhoample phrojekthi yokuklama.
    Qaphela ukuthi awukwazi ukushintsha ukwabiwa kwephinikhodi ye-PCIe kuphrojekthi ye-Intel Quartus Prime. Kodwa-ke, ukwenza lula umzila we-PCB, ungathatha i-advantagI-e yokuhlehliswa komzila kanye nezici zokuguqulwa kwe-polarity ezisekelwa yile IP.

2.3. Ukulingisa i-Design Example
Ukusethwa kokulingisa kubandakanya ukusetshenziswa kwe-Root Port Bus Functional Model (BFM) ukuze usebenzise i-P-tile Avalon Streaming IP ye-PCIe (DUT) njengoba kuboniswe kokulandelayo.
umfanekiso.
Umfanekiso 13. I-PIO Design Exampfuthi Simulation Testbench

Ukuze uthole imininingwane eyengeziwe ngebhentshi le-test kanye namamojula akulo, bheka i-Testbench ekhasini le-15.
Umdwebo olandelayo wokugeleza ubonisa izinyathelo zokulingisa i-ex yomklamoample:
Umfanekiso 14. Inqubo

1.  Shintshela kumkhombandlela wokulingisa we-testbench, / pcie_ed_tb/pcie_ed_tb/sim/ /isifanisi.
2. Qalisa iskripthi sokulingisa sesifanisi osithandayo. Bheka ithebula elingezansi.
3. Hlaziya imiphumela.

Qaphela: I-P-Tile ayisekeli ukulingiswa okuhambisanayo kwe-PIPE.
Ithebula 1. Izinyathelo Zokuqalisa Ukulingisa

Isifanisi	Uhlu Lokusebenza	Iziyalezo
I-ModelSim* SE, Siemens* EDA QuestaSim*- Intel FPGA Edition	<example_design>/pcie_ed_tb/ pcie_ed_tb/sim/mentor/	1. Cela i-vsim (ngokuthayipha i-vsim, eveza iwindi lekhonsoli lapho ungasebenzisa khona imiyalo elandelayo). 2. yenza msim_setup.tcl Qaphela: Okunye, esikhundleni sokwenza Izinyathelo 1 no-2, ungathayipha: vsim -c -do msim_setup.tcl. 3. ld_debug 4. gijima -bonke 5. Ukulingisa okuyimpumelelo kugcina ngomlayezo olandelayo, “Ukulingisa kumisiwe ngenxa yokuqedwa ngempumelelo!”
VCS*	<example_design>/pcie_ed_tb/ pcie_ed_tb/sim/synopsy/vcs	1. Thayipha sh vcs_setup.sh USER_DEFINED_COMPILE_OPTIONS=”” USER_DEFINED_ELAB_OPTIONS=”-xlrm\ uniq_prior_final” USER_DEFINED_SIM_OPTIONS=”
waqhubeka...

Isifanisi	Uhlu Lokusebenza	Iziyalezo
		Qaphela: Umyalo ongenhla uwumugqa owodwa. 2. Ukulingisa okuyimpumelelo kugcina ngomlayezo olandelayo, “Ukulingisa kumisiwe ngenxa yokuqedwa ngempumelelo!” Qaphela: Ukuze uqalise ukulingisa kumodi yokusebenzisana, sebenzisa lezi zinyathelo ezilandelayo: (uma usuvele ukhiqize i-siMV esebenzisekayo ngemodi engahlanganyeli, susa i-simv ne-simv.diadir) 1. Vula i-vcs_setup.sh file bese wengeza inketho yokususa iphutha kumyalo we-VCS: vcs -debug_access+r 2. Hlanganisa umklamo example: sh vcs_setup.sh USER_DEFINED_ELAB_OPTIONS=”- xlrm\ uniq_prior_final” SKIP_SIM=1 3. Qala ukulingisa kumodi yokusebenzisana: simv -gui &

Le testbench ilingisa kufika kokuhlukile kwe-Gen4 x16.
Ukulingiswa kuyabika, "Ukulingiswa kumisiwe ngenxa yokuqedwa ngempumelelo" uma engekho amaphutha enzekayo.
2.3.1. I-Testbench
Ibhentshi le-test lisebenzisa imojula yomshayeli wokuhlola, i-altpcietb_bfm_rp_gen4_x16.sv, ukuze iqalise ukucushwa nokushintshana kwememori. Ekuqaleni, imojula yomshayeli wokuhlola ibonisa ulwazi oluvela ku-Root Port kanye namarejista e-Endpoint Configuration Space, ukuze ukwazi ukuhlobanisa nemingcele oyicacisile usebenzisa Isihleli Sepharamitha.
I-exampi-le design ne-testbench kukhiqizwa ngokuguquguqukayo ngokusekelwe ekucushweni okukhethayo kwe-P-Tile IP ye-PCIe. I-testbench isebenzisa amapharamitha owacacisa Kusihleli Sepharamitha ku-Intel Quartus Prime. Le testbench ilingisa kufika ku-×16 PCI Express ilinki isebenzisa isixhumi esibonakalayo se-serial PCI Express. Idizayini ye-testbench ayivumeli isixhumanisi se-PCI Express esingaphezu kwesisodwa ukuthi silingiswe ngesikhathi. Umfanekiso olandelayo uveza izinga eliphezulu view yomklamo we-PIO example.
Umfanekiso 15. I-PIO Design Exampfuthi Simulation Testbench

Izinga eliphezulu le-testbench lifaka amamojula alandelayo amakhulu:

• altpcietb_bfm_rp_gen4x16.sv —Lena I-Root Port PCIe BFM.
  //Indlela yohlu
  /intel_pcie_ptile_ast_0_example_design/pcie_ed_tb/ip/
  pcie_ed_tb/dut_pcie_tb_ip/intel_pcie_ptile_tbed_ /sim
• pcie_ed_dut.ip: Lona umklamo we-Endpoint namapharamitha owacacisayo.
  //Indlela yohlu
  /intel_pcie_ptile_ast_0_example_design/ip/pcie_ed
• pcie_ed_pio0.ip: Le mojula iyimpokophelo futhi iyisiqalisi semisebenzi ye-PIO design example.
  //Indlela yohlu
  /intel_pcie_ptile_ast_0_example_design/ip/pcie_ed
• pcie_ed_sriov0.ip: Le mojula iyimpoqo kanye nomqalisi wokuthengiselana we-SR-IOV design example.
  //Indlela yohlu
  /intel_pcie_ptile_ast_0_example_design/ip/pcie_ed

Umfanekiso 16. I-SR-IOV Design Exampfuthi Simulation Testbench

Ngaphezu kwalokho, i-testbench inezinqubo ezenza imisebenzi elandelayo:

• Ikhiqiza iwashi lesithenjwa le-Endpoint ngefrikhwensi edingekayo.
• Ihlinzeka ngokusetha kabusha kwe-PCI Express ekuqaleni.

Ukuze uthole imininingwane eyengeziwe nge-Root Port BFM, bheka isahluko se-TestBench se-Intel FPGA P-Tile Avalon yokusakaza IP ye-PCI Express User Guide.
Ulwazi Oluhlobene
I-Intel FPGA P-Tile Avalon isakaza i-IP ye-PCI Express Umhlahlandlela Womsebenzisi
2.3.1.1. Hlola Driver Module
Imojuli yomshayeli wokuhlola, i-intel_pcie_ptile_tbed_hwtcl.v, iqinisekisa i-toplevel BFM,altpcietb_bfm_top_rp.v.
I-BFM yezinga eliphezulu iqeda le misebenzi elandelayo:

1. Kubuza umshayeli nokuqapha.
2. Iqinisekisa i-Root Port BFM.
3. Iqinisekisa isixhumi esibonakalayo se-serial.

Imojula yokumisa, i-altpcietb_g3bfm_configure.v, yenza imisebenzi elandelayo:

1. Ilungiselela futhi yabela ama-BAR.
2. Ilungiselela i-Root Port ne-Endpoint.
3. Ibonisa i-Configuration Space, i-BAR, i-MSI, i-MSI-X, nezilungiselelo ze-AER.

2.3.1.2. I-PIO Design Example Testbench

Umfanekiso ongezansi ubonisa i-PIO design example sekulingisa design hierarchy. Ukuhlolwa kwe-PIO design example zichazwa ngepharamitha ye-apps_type_hwtcl esethwe ukuze
3. Ukuhlola okwenziwa ngaphansi kwaleli xabiso lepharamitha kuchazwa kokuthi ebfm_cfg_rp_ep_rootport, find_mem_bar kanye ne-downstream_loop.
Umfanekiso 17. I-PIO Design ExampleSimulation Design Hierarchy

I-testbench iqala ngokuqeqeshwa kwesixhumanisi bese ifinyelela indawo yokumisa ye-IP ukuze ibalwe. Umsebenzi obizwa ngokuthi i-downstream_loop (echazwe ku-Root Port
I-PCIe BFM altpcietb_bfm_rp_gen4_x16.sv) bese yenza ukuhlolwa kwesixhumanisi se-PCIe. Lokhu kuhlola kuqukethe izinyathelo ezilandelayo:

1. Khipha umyalo wokubhala inkumbulo ukuze ubhale i-dword eyodwa yedatha kumemori eku-chip ngemuva kwe-Endpoint.
2. Khipha umyalo wokufunda inkumbulo ukuze ufunde futhi idatha kumemori eku-chip.
3. Qhathanisa idatha efundiwe nedatha yokubhala. Uma zifana, ukuhlolwa kubala lokhu njengePhasi.
4. Phinda Izinyathelo 1, 2 no-3 ngokuphindaphinda okungu-10.

Ukubhalwa kwenkumbulo yokuqala kwenzeka cishe ngama-219 kithi. Kulandelwa inkumbulo efundwa ku-interface ye-Avalon-ST RX ye-P-tile Hard IP ye-PCIe. I-Completion TLP ivela ngemuva nje kwesicelo sokufundwa kwememori kusixhumi esibonakalayo se-Avalon-ST TX.
2.3.1.3. I-SR-IOV Design Example Testbench
Umfanekiso ongezansi ubonisa i-SR-IOV design example sekulingisa design hierarchy. Ukuhlolwa komklamo we-SR-IOV example zenziwa umsebenzi obizwa ngokuthi i-sriov_test,
okuchazwa kokuthi altpcietb_bfm_cfbp.sv.
Umfanekiso 18. I-SR-IOV Design ExampleSimulation Design Hierarchy

Ibhentshi lokuhlola le-SR-IOV lisekela iMisebenzi Yomzimba efika kwemibili (PFs) kanye ne-32 Virtual Functions (VFs) ngayinye ye-PF.
I-testbench iqala ngokuqeqeshwa kwesixhumanisi bese ifinyelela indawo yokumisa ye-IP ukuze ibalwe. Ngemva kwalokho, yenza lezi zinyathelo ezilandelayo:

1. Thumela isicelo sokubhala inkumbulo kuPF elandelwa isicelo sokufundwa kwememori ukuze ufunde futhi idatha efanayo ukuze uqhathanise. Uma idatha efundiwe ifana nedatha yokubhala, kunjalo
   iPhasi. Lokhu kuhlola kwenziwa umsebenzi obizwa ngokuthi my_test (echazwe ku-altpcietb_bfm_cfbp.v). Lokhu kuhlola kuphindwa kabili ku-PF ngayinye.
2. Thumela isicelo sokubhala inkumbulo ku-VF elandelwa isicelo sokufundwa kwememori ukuze ufunde futhi idatha efanayo ukuze uyiqhathanise. Uma idatha efundiwe ifana nedatha yokubhala, kunjalo
   iPhasi. Lokhu kuhlola kwenziwa umsebenzi obizwa ngokuthi cfbp_target_test (ochazwe ku-altpcietb_bfm_cfbp.v). Lokhu kuhlola kuyaphindwa ku-VF ngayinye.

Ukubhalwa kwenkumbulo yokuqala kwenzeka cishe ku-263 us. Kulandelwa inkumbulo efundwa ku-interface ye-Avalon-ST RX ye-PF0 ye-P-tile Hard IP ye-PCIe. I-Completion TLP ivela ngemuva nje kwesicelo sokufundwa kwememori kusixhumi esibonakalayo se-Avalon-ST TX.
2.4. Ukuhlanganisa i-Design Example

1. Zulazulela ku /intel_pcie_ptile_ast_0_example_design/ futhi uvule pcie_ed.qpf.
2. Uma ukhetha enye yalezi zindlela ezimbili zokuthuthukisa ezilandelayo, izilungiselelo ezihlobene ne-VID zifakiwe ku-.qsf file yomklamo okhiqiziwe example, futhi akudingekile ukuthi uwangeze mathupha. Qaphela ukuthi lezi zilungiselelo ziqondene nebhodi.
   • Ikhithi yokuthuthukisa ye-Intel Stratix 10 DX P-Tile ES1 FPGA
   • Ikhithi yokuthuthukisa ye-Intel Stratix 10 DX P-Tile Production FPGA
   • Ikhithi yokuthuthukisa ye-Intel Agilex F-Series P-Tile ES0 FPGA
3. Kumenyu Yokucubungula, khetha Qala Ukuhlanganisa.

2.5. Ukufaka i-Linux Kernel Driver

Ngaphambi kokuthi uhlole i-ex designampku-hardware, kufanele ufake i-Linux kernel
umshayeli. Ungasebenzisa lo mshayeli ukwenza izivivinyo ezilandelayo:
• Ukuhlolwa kwesixhumanisi se-PCIe okwenza 100 ukubhala nokufunda
• Indawo yenkumbulo DWORD
ufunda abhale
• Isikhala sokumisa i-DWORD ifundeka futhi ibhale
(1)
Ngaphezu kwalokho, ungasebenzisa umshayeli ukushintsha inani lamapharamitha alandelayo:
• IBHA esetshenziswayo
• Idivaysi ekhethiwe (ngokucacisa izinombolo zebhasi, idivayisi kanye nomsebenzi (BDF) we
idivayisi)
Qedela lezi zinyathelo ezilandelayo ukufaka umshayeli we-kernel:

1. Zulazulela ku-./software/kernel/linux ngaphansi kwe-example design generation directory.
2. Shintsha izimvume ekufakeni, ekulayisheni, nasekulayisheni files:
   $ chmod 777 ukufaka ukulayishwa kokulayisha
3. Faka umshayeli:
   $ sudo ./install
4. Qinisekisa ukufakwa komshayeli:
   $ lsmod | I-grep intel_fpga_pcie_drv
   Umphumela olindelekile:
   intel_fpga_pcie_drv 17792 0
5. Qinisekisa ukuthi i-Linux iyayibona i-PCIe design example:
   $ lspci -d 1172:000 -v | I-grep intel_fpga_pcie_drv
   Qaphela: Uma ushintshe i-ID yomthengisi, faka esikhundleni se-ID yomthengisi entsha ye-Intel
   I-ID yomthengisi kulo myalo.
   Umphumela olindelekile:
   Umshayeli we-Kernel osebenzayo: intel_fpga_pcie_drv

2.6. Ukusebenzisa i-Design Example
Nansi imisebenzi yokuhlola ongayenza ku-P-Tile Avalon-ST PCIe design exampkancane:

1. Kuwo wonke lo mhlahlandlela womsebenzisi, amagama athi, i-DWORD kanye ne-QWORD anencazelo efanayo nanayo ku-PCI Express Base Specification. Igama linamabhithi ayi-16, i-DWORD inamabhithi angama-32, kanti i-QWORD inamabhithi angama-64.

Ithebula 2. Ukuhlola Ukusebenza Okusekelwe I-P-Tile Avalon-ST PCIe Design ExampLes

Imisebenzi	I-BAR edingekayo	Isekelwa yi-P-Tile Avalon-ST PCIe Design Example
0: Ukuhlolwa kwesixhumanisi - 100 uyabhala futhi afunde	0	Yebo
1: Bhala isikhala senkumbulo	0	Yebo
2: Funda isikhala senkumbulo	0	Yebo
3: Bhala isikhala sokumisa	N/A	Yebo
4: Funda isikhala sokumisa	N/A	Yebo
5: Shintsha IBHA	N/A	Yebo
6: Shintsha idivayisi	N/A	Yebo
7: Nika amandla i-SR-IOV	N/A	Yebo (*)
8: Yenza ukuhlola kwesixhumanisi kuwo wonke umsebenzi obonakalayo onikwe amandla wedivayisi yamanje	N/A	Yebo (*)
9: Yenza i-DMA	N/A	Cha
10: Yeka uhlelo	N/A	Yebo

Qaphela: (*) Le misebenzi yokuhlola itholakala kuphela uma umklamo we-SR-IOV exampikhethiwe.
2.6.1. Ukusebenzisa i-PIO Design Example

1. Zulazulela ku-./software/user/example ngaphansi komklamo example directory.
2. Hlanganisa i-ex designampisicelo:
   $ yenza
3. Yenza ukuhlolwa:
   $ sudo ./intel_fpga_pcie_link_test
   Ungaqalisa ukuhlolwa kwesixhumanisi se-Intel FPGA IP PCIe ngemodi yezandla noma ezenzakalelayo. Khetha kulokhu:
   • Kwimodi e-othomathikhi, uhlelo luzikhethela idivayisi. Ukuhlolwa kukhetha idivayisi ye-Intel PCIe ene-BDF ephansi kakhulu ngokufanisa i-ID yomthengisi.
   Ukuhlola futhi kukhetha IBHA etholakalayo ephansi kakhulu.
   • Kumodi yezandla, ukuhlolwa kukubuza ngebhasi, idivayisi, nenombolo yokusebenza kanye ne-BAR.
   Nge-Intel Stratix 10 DX noma i-Intel Agilex Development Kit, ungakwazi ukunquma
   BDF ngokuthayipha umyalo olandelayo:
   $ lspci -d 1172:
   4. Nazi izi-sampi-le transcripts yezindlela ezizenzakalelayo nezamanuwali:
   Imodi ezenzakalelayo:

Imodi yokwenziwa ngesandla:

Ulwazi Oluhlobene
I-PCIe Link Inspector Overview
Sebenzisa i-PCIe Link Inspector ukuze ugade isixhumanisi kokuthi Physical, Data Link kanye Nezendlalelo Zokwenziwayo.
2.6.2. Isebenzisa i-SR-IOV Design Example

Nazi izinyathelo zokuhlola i-ex design SR-IOVampku-hardware:

1. Qalisa ukuhlolwa kwesixhumanisi se-Intel FPGA IP PCIe ngokusebenzisa i-sudo ./
   intel_fpga_pcie_link_test umyalo bese ukhetha inketho 1:
   Khetha mathupha idivayisi.
2. Faka i-BDF yomsebenzi obonakalayo lapho imisebenzi ebonakalayo yabelwe khona.
3. Faka IBHAYIBHILE “0” ukuze uqhubekele kumenyu yokuhlola.
4. Faka inketho 7 ukuze unike amandla i-SR-IOV kudivayisi yamanje.
5. Faka inombolo yemisebenzi ebonakalayo ezonikwa amandla kudivayisi yamanje.
   
6. Faka inketho yesi-8 ukuze wenze ukuhlola kwesixhumanisi kwawo wonke umsebenzi obonakalayo onikwe amandla owabelwe umsebenzi ophathekayo. Uhlelo lokusebenza lokuhlola isixhumanisi luzokwenza inkumbulo eyi-100 ibhale nge-dword eyodwa yedatha ngayinye bese ifunda idatha emuva ukuze ihlolwe. Uhlelo lokusebenza luzophrinta inombolo yemisebenzi ebonakalayo ehlulekile ukuhlolwa kwesixhumanisi ekupheleni kokuhlolwa.
   7. Kutheminali entsha, sebenzisa i-lspci –d 1172: | grep -c “Altera” umyalo wokuqinisekisa ukubalwa kwama-PF nama-VF. Umphumela olindelekile uyisamba senani lemisebenzi ebonakalayo kanye nenani lemisebenzi ebonakalayo.

I-P-tile Avalon yokusakaza IP ye-PCI Express Design

Example Izingobo zomlando zomhlahlandlela womsebenzisi

Inguqulo ye-Intel Quartus Prime	Umhlahlandlela Womsebenzisi
21.2	IP-tile Avalon yokusakaza IP ye-PCI Express Design Example Umhlahlandlela Womsebenzisi
20.3	IP-tile Avalon yokusakaza IP ye-PCI Express Design Example Umhlahlandlela Womsebenzisi
20.2	IP-tile Avalon yokusakaza IP ye-PCI Express Design Example Umhlahlandlela Womsebenzisi
20.1	IP-tile Avalon yokusakaza IP ye-PCI Express Design Example Umhlahlandlela Womsebenzisi
19.4	IP-tile Avalon yokusakaza IP ye-PCI Express Design Example Umhlahlandlela Womsebenzisi
19.1.1	IP-tile Avalon yokusakaza IP ye-PCI Express Design Example Umhlahlandlela Womsebenzisi

Inkampani ye-Intel Wonke Amalungelo Agodliwe. I-Intel, ilogo ye-Intel, nezinye izimpawu ze-Intel yizimpawu zokuthengisa ze-Intel Corporation noma izinkampani ezingaphansi kwayo. I-Intel iqinisekisa ukusebenza kwe-FPGA yayo kanye nemikhiqizo yesemiconductor ekucacisweni kwamanje ngokuvumelana newaranti evamile ye-Intel, kodwa igodla ilungelo lokwenza izinguquko kunoma imiphi imikhiqizo namasevisi nganoma yisiphi isikhathi ngaphandle kwesaziso. I-Intel ayithathi mthwalo noma isikweletu esivele ngenxa yesicelo noma ukusetshenziswa kwanoma yiluphi ulwazi, umkhiqizo, noma isevisi echazwe lapha ngaphandle kwalapho okuvunyelwene ngakho ngokubhaliwe yi-Intel. Amakhasimende e-Intel ayelulekwa ukuthi athole inguqulo yakamuva yokucaciswa kwedivayisi ngaphambi kokuthembela kunoma yiluphi ulwazi olushicilelwe nangaphambi kokufaka ama-oda emikhiqizo noma amasevisi. *Amanye amagama namabhrendi angafunwa njengempahla yabanye.
ISO
9001:2015
Ibhalisiwe

Umlando Wokubuyekezwa Kwedokhumenti we-Intel P-Tile Avalon

Ukusakaza i-IP eqinile ye-PCIe Design Example Umhlahlandlela Womsebenzisi

Inguqulo Yedokhumenti	Inguqulo ye-Intel Quartus Prime	Inguqulo ye-IP	Izinguquko
2021.10.04	21.3	6.0.0	Kushintshwe ukulungiselelwa okusekelwayo kwe-SR-IOV yomklamo example kusukela ku-Gen3 x16 EP kanye ne-Gen4 x16 EP kuya ku-Gen3 x8 EP kanye ne-Gen4 x8 EP Encazelweni Esebenzayo Ye-Single Root I/O Virtualization (SR-IOV) Design Example ngxenye. Kwengezwe ukusekelwa kwe-Intel Stratix 10 DX P-tile Production FPGA Development Kit ku-Generating the Design Ex.ample ngxenye.
2021.07.01	21.2	5.0.0	Kususwe amaza okulingisa we-PIO kanye ne-SR-IOV ex designampokuncane okuvela esigabeni Ukulinganisa I-Design Example. Buyekeza umyalo ukuze ubonise i-BDF esigabeni Ukusebenzisa i-PIO Design Example.
2020.10.05	20.3	3.1.0	Kukhishwe isigaba Sokubhalisa kusukela kumklamo we-Avalon Streaming exampLes ayinayo irejista yokulawula.
2020.07.10	20.2	3.0.0	Kungezwe ama-waveforms okulingisa, izincazelo zecala lokuhlola nezincazelo zemiphumela yokuhlola ye-ex yedizayiniampLes. Kwengezwe imiyalelo yokulingisa yesifanisi se-ModelSim Ekulingiseni I-Design Example ngxenye.
2020.05.07	20.1	2.0.0	Kubuyekezwe isihloko sedokhumenti ku-Intel FPGA P-Tile Avalon yokusakaza IP ye-PCI Express Design Example Umhlahlandlela Womsebenzisi ukuhlangabezana nemihlahlandlela emisha yokuqamba amagama. Kubuyekezwe umyalo wokulingisa wemodi esebenzayo ye-VCS.
2019.12.16	19.4	1.1.0	Kwengezwe i-SR-IOV design example incazelo.
2019.11.13	19.3	1.0.0	Kwengezwe i-Gen4 x8 Endpoint kanye ne-Gen3 x8 Endpoint ohlwini lokucushwa okusekelwayo.
2019.05.03	19.1.1	1.0.0	Ukukhishwa kokuqala.

Inkampani ye-Intel Wonke Amalungelo Agodliwe. I-Intel, ilogo ye-Intel, nezinye izimpawu ze-Intel yizimpawu zokuthengisa ze-Intel Corporation noma izinkampani ezingaphansi kwayo. I-Intel iqinisekisa ukusebenza kwe-FPGA yayo kanye nemikhiqizo yesemiconductor ekucacisweni kwamanje ngokuvumelana newaranti evamile ye-Intel, kodwa igodla ilungelo lokwenza izinguquko kunoma imiphi imikhiqizo namasevisi nganoma yisiphi isikhathi ngaphandle kwesaziso. I-Intel ayithathi mthwalo noma isikweletu esivele ngenxa yesicelo noma ukusetshenziswa kwanoma yiluphi ulwazi, umkhiqizo, noma isevisi echazwe lapha ngaphandle kwalapho okuvunyelwene ngakho ngokubhaliwe yi-Intel. Amakhasimende e-Intel ayelulekwa ukuthi athole inguqulo yakamuva yokucaciswa kwedivayisi ngaphambi kokuthembela kunoma yiluphi ulwazi olushicilelwe nangaphambi kokufaka ama-oda emikhiqizo noma amasevisi. *Amanye amagama namabhrendi angafunwa njengempahla yabanye.
ISO
9001:2015
Ibhalisiwe

I-Online Version
Thumela Impendulo
Inombolo yepholisi: 683038
UG-20234
Inguqulo: 2021.10.04

Amadokhumenti / Izinsiza

Intel FPGA P-Tile Avalon yokusakaza IP ye-PCI Express Design Example [pdf] Umhlahlandlela Womsebenzisi I-FPGA P-Tile, i-IP yokusakaza ye-Avalon ye-PCI Express Design Example, i-FPGA P-Tile Avalon yokusakaza IP ye-PCI Express Design Example, FPGA P-Tile Avalon yokusakaza IP

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