F Tile Serial Lite IV Intel FPGA IP Umhlahlandlela Womsebenzisi

Okuqukethwe fihla

F Tile Serial Lite IV Intel FPGA IP

Umhlahlandlela Womsebenzisi we-F-Tile Serial Lite IV Intel® FPGA IP
Ibuyekezelwe i-Intel® Quartus® Prime Design Suite: 22.1 IP Version: 5.0.0

Inguqulo Ye-inthanethi Thumela Impendulo

UG-20324

I-ID: 683074 Inguqulo: 2022.04.28

Okuqukethwe
Okuqukethwe
1. Mayelana Nomhlahlandlela Womsebenzisi we-F-Tile Serial Lite IV Intel® FPGA IP………………………………………….. 4
2. I-F-Tile Serial Lite IV Intel FPGA IP Overview………………………………………………………………. 6 2.1. Ulwazi Lokukhishwa…………………………………………………………………………………..7 2.2. Izici ezisekelwe…………………………………………………………………………………….. 7 2.3. I-IP Version Support Level……………………………………………………………………………..8 2.4. Ukusekelwa Kwebanga Lesivinini Sedivayisi………………………………………………………………………..8 2.5. Ukusetshenziswa Kwezinsiza kanye nokubambezeleka …………………………………………………………………………… I-Bandwidth Efficiency………………………………………………………………………………………. 9
3. Ukuqalisa……………………………………………………………………………………………………………………………………………………. 11 3.1. Ukufaka kanye nokunikeza amalayisense e-Intel FPGA IP Cores………………………………………………………… 11 3.1.1. I-Intel FPGA IP Evaluation Mode ……………………………………………………………. 11 3.2. Ukucacisa amapharamitha we-IP kanye nezinketho…………………………………………………………… 14 3.3. Kwenziwe File Isakhiwo…………………………………………………………………………………… 14 3.4. Ukulingisa i-Intel FPGA IP Cores……………………………………………………………………………… 16 3.4.1. Ukulingisa kanye Nokuqinisekisa Idizayini…………………………………………………….. 17 3.5. Ukuhlanganiswa Kwezingqikithi Ze-IP Kwamanye Amathuluzi E-EDA…………………………………………………………. 17 3.6. Ukuhlanganisa Idizayini Egcwele…………………………………………………………………………..18
4. Incazelo Yokusebenza…………………………………………………………………………………….. 19 4.1. I-TX Datapath………………………………………………………………………………………..20 4.1.1. I-adaptha ye-TX MAC………………………………………………………………………….. 21 4.1.2. Ukufakwa Kwezwi Lokulawula (CW)…………………………………………………………………………… 23 4.1.3. I-TX CRC…………………………………………………………………………………………28 4.1.4. I-TX MII Encoder……………………………………………………………………………….29 4.1.5. I-TX PCS kanye ne-PMA………………………………………………………………………….. 30 4.2. I-RX Datapath…………………………………………………………………………………………. 30 4.2.1. I-RX PCS ne-PMA………………………………………………………………………….. 31 4.2.2. Idekhoda ye-RX MII………………………………………………………………………………… 31 4.2.3. I-RX CRC………………………………………………………………………………….. 31 4.2.4. I-RX Deskew………………………………………………………………………………….32 4.2.5. Ukususwa kwe-RX CW………………………………………………………………………………35 4.3. I-F-Tile Serial Lite IV Intel FPGA IP Clock Architecture……………………………………………. 36 4.4. Ukusetha Kabusha Nokuqaliswa Kokuxhumanisa…………………………………………………………………………..37 4.4.1. I-TX Ukusetha Kabusha Nokulandelana Kokuqala …………………………………………………. 38 4.4.2. Ukusetha Kabusha kwe-RX kanye Nokulandelana Kokuqala ……………………………………………………. 39 4.5. Isilinganiso Sokuxhumanisa kanye Nezibalo ZokuSebenza Komkhawulokudonsa ………………………………………………….. 40
5. Amapharamitha………………………………………………………………………………………………………. 42
6. I-F-Tile Serial Lite IV Intel FPGA IP Interface Signals…………………………………………….. 44 6.1. Izimpawu Zewashi………………………………………………………………………………………….44 6.2. Setha kabusha Amasignali……………………………………………………………………………………………… Izimpawu ze-MAC……………………………………………………………………………………….. 44 6.3. Ama-Transceiver Reconfiguration Signals……………………………………………………………………………… 45 6.4. Izimpawu ze-PMA……………………………………………………………………………………….. 48

I-F-Tile Serial Lite IV Intel® FPGA IP Umhlahlandlela Womsebenzisi 2

Thumela Impendulo

Okuqukethwe
7. Ukuklama nge-F-Tile Serial Lite IV Intel FPGA IP…………………………………………………… 51 7.1. Setha Kabusha Izinkombandlela…………………………………………………………………………………….. 51 7.2. Izinkombandlela Zokuphatha Amaphutha…………………………………………………………………………..51
8. F-Tile Serial Lite IV Intel FPGA IP Umhlahlandlela Womsebenzisi Izingobo zomlando …………………………………………. 52 9. Umlando Wokubuyekezwa Kombhalo we-F-Tile Serial Lite IV Intel FPGA IP User Guide………53

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I-F-Tile Serial Lite IV Intel® FPGA IP Umhlahlandlela Womsebenzisi 3

683074 | 2022.04.28 Thumela Impendulo

1. Mayelana ne-F-Tile Serial Lite IV Intel® FPGA IP User Guide

Lo mbhalo uchaza izici ze-IP, incazelo yezakhiwo, izinyathelo zokukhiqiza, nemihlahlandlela yokuklama i-F-Tile Serial Lite IV Intel® FPGA IP usebenzisa ama-F-tile transceiver kumadivayisi we-Intel AgilexTM.

Izilaleli Ezihlosiwe

Lo mbhalo uhloselwe abasebenzisi abalandelayo:
· Abaklami bezakhiwo ukuze benze ukukhetha kwe-IP phakathi nesigaba sokuhlela umklamo wezinga lesistimu
· Abaklami bezingxenyekazi zekhompuyutha lapho behlanganisa i-IP kumklamo wabo wezinga lesistimu
· Onjiniyela bokuqinisekisa phakathi nezigaba zokulingiswa kwezinga lesistimu nezingxenyekazi zekhompuyutha zokuqinisekisa

Imibhalo Ehlobene

Ithebula elilandelayo libala amanye amadokhumenti ayizethenjwa ahlobene ne-F-Tile Serial Lite IV Intel FPGA IP.

Ithebula 1.

Imibhalo Ehlobene

Ireferensi

I-F-Tile Serial Lite IV Intel FPGA IP Design Example Umhlahlandlela Womsebenzisi

Ishidi ledatha yedivayisi ye-Intel Agilex

Incazelo
Lo mbhalo unikeza ukukhiqizwa, imihlahlandlela yokusebenzisa, kanye nencazelo esebenzayo ye-F-Tile Serial Lite IV Intel FPGA IP design ex.ampkumadivayisi we-Intel Agilex.
Lo mbhalo uchaza izici zikagesi, izici zokushintsha, ukucaciswa kokucushwa, kanye nesikhathi samadivayisi we-Intel Agilex.

Ithebula 2.
I-CW RS-FEC PMA TX RX PAM4 NRZ

Ama-Acronyms kanye Nohlu Lwamagama-magama afingqiwe
Isifinyezo

I-Expansion Control Word Reed-Solomon Forward Iphutha Ukulungisa I-Physical Medium Medium Receiver Receiver Pulse-Amplitude Modulation 4-Level Ukungabuyeli-ku-zero

waqhubeka...

Inkampani ye-Intel Wonke Amalungelo Agodliwe. I-Intel, ilogo ye-Intel, nezinye izimpawu ze-Intel yizimpawu zokuthengisa ze-Intel Corporation noma izinkampani ezingaphansi kwayo. I-Intel iqinisekisa ukusebenza kwe-FPGA yayo kanye nemikhiqizo yesemiconductor ekucacisweni kwamanje ngokuvumelana newaranti evamile ye-Intel, kodwa igodla ilungelo lokwenza izinguquko kunoma imiphi imikhiqizo namasevisi nganoma yisiphi isikhathi ngaphandle kwesaziso. I-Intel ayithathi mthwalo noma isikweletu esivele ngenxa yesicelo noma ukusetshenziswa kwanoma yiluphi ulwazi, umkhiqizo, noma isevisi echazwe lapha ngaphandle kwalapho okuvunyelwene ngakho ngokubhaliwe yi-Intel. Amakhasimende e-Intel ayelulekwa ukuthi athole inguqulo yakamuva yokucaciswa kwedivayisi ngaphambi kokuthembela kunoma yiluphi ulwazi olushicilelwe nangaphambi kokufaka ama-oda emikhiqizo noma amasevisi. *Amanye amagama namabhrendi angafunwa njengempahla yabanye.

I-ISO 9001:2015 Ibhalisiwe

1. Mayelana ne-F-Tile Serial Lite IV Intel® FPGA IP User Guide 683074 | 2022.04.28

I-PCS MII XGMII

Isifinyezo

Ukunwetshwa Kwekhodi Engokoqobo I-Sublayer Media Independent Interface 10 Gigabit Media Independent Interface

Thumela Impendulo

I-F-Tile Serial Lite IV Intel® FPGA IP Umhlahlandlela Womsebenzisi 5

683074 | 2022.04.28 Thumela Impendulo

2. I-F-Tile Serial Lite IV Intel FPGA IP Overview

Umfanekiso 1.

I-F-Tile Serial Lite IV Intel FPGA IP ilungele ukuxhumana kwedatha yomkhawulokudonsa ophezulu we-chip-to-chip, ibhodi ukuya ebhodini, kanye nezinhlelo zokusebenza ze-backplane.

I-F-Tile Serial Lite IV Intel FPGA IP ihlanganisa ukulawulwa kokufinyelela kwemidiya (MAC), isisekelo sombhalo wekhodi esibonakalayo (PCS), namabhulokhi okunamathiselwe kwemidiya ebonakalayo (i-PMA). I-IP isekela isivinini sokudluliswa kwedatha esingafika ku-56 Gbps emzileni ngamunye enomkhawulo wemizila emine ye-PAM4 noma u-28 Gbps emzileni ngamunye onemizila emikhulu engu-16 NRZ. Le IP inikeza umkhawulokudonsa ophezulu, amafreyimu aphezulu aphansi, isibalo se-I/O esiphansi, futhi isekela ukukala okuphezulu kuzo zombili izinombolo zemizila nesivinini. Le IP iphinda ilungiseke kalula ngosekelo lwenani elibanzi ledatha ngemodi ye-Ethernet PCS ye-F-tile transceiver.

Le IP isekela izindlela ezimbili zokudlulisela:
· Imodi eyisisekelo–Lena imodi yokusakaza emsulwa lapho idatha ithunyelwa ngaphandle kwephakethe lokuqala, umjikelezo ongenalutho, nokuphela kwephakethe ukuze kwandiswe umkhawulokudonsa. I-IP ithatha idatha yokuqala evumelekile njengesiqalo sokuqhuma.
· Imodi egcwele-Lena imodi yokudlulisa iphakethe. Kule modi, i-IP ithumela ukuqhuma kanye nomjikelezo wokuvumelanisa ekuqaleni nasekupheleni kwephakethe njengama-delimiters.

F-Tile Serial Lite IV High Level Block Diagram

I-Avalon Streaming Interface TX

I-F-Tile Serial Lite IV Intel FPGA IP
I-MAC TX
TX USRIF_CTRL

Amabhithi emigqa engu-64*n (imodi ye-NRZ)/ 2*n amabhithi emizila (imodi ye-PAM4)

I-TX MAC

I-adaptha INSERT

I-MII ENCODE

Ama-PC ngokwezifiso

I-TX PCS

I-TX MII

I-EMIB ENCODE SCRAMBLER FEC

I-TX PMA

n Lanes Bits (PAM4 mode)/ n Lanes Bits (NRZ mode)
I-TX Serial Interface

I-Avalon Streaming Interface RX
Amabhithi emigqa engu-64*n (imodi ye-NRZ)/ 2*n amabhithi emizila (imodi ye-PAM4)

RX PCS

CW RMV

DESKEW

I-MII

& HLANGANISA I-DECODE

I-RX MII

I-EMIB

I-DECODE BLOCK SYNC & FEC DESCRAMBLER

I-RX PMA

I-CSR

2n Lanes Bits (imodi ye-PAM4)/ n Lanes Bits (imodi ye-NRZ) RX Serial Interface
I-Avalon Memory-Mapped Interface Registration Config

Inganekwane

I-logic ethambile

I-logic eqinile

I-ISO 9001:2015 Ibhalisiwe

2. I-F-Tile Serial Lite IV Intel FPGA IP Overview 683074 | 2022.04.28

Ungakwazi ukukhiqiza i-F-Tile Serial Lite IV Intel FPGA IP design exampukuze ufunde kabanzi mayelana nezici ze-IP. Bheka ku-F-Tile Serial Lite IV Intel FPGA IP Design Example Umhlahlandlela Womsebenzisi.
Ulwazi Oluhlobene · Incazelo Esebenzayo ekhasini 19 · F-Tile Serial Lite IV Intel FPGA IP Design Example Umhlahlandlela Womsebenzisi

2.1. Khipha Ulwazi

Izinguqulo ze-Intel FPGA IP zifana nezinguqulo zesofthiwe ye-Intel Quartus® Prime Design Suite kuze kube yi-v19.1. Iqala ku-Intel Quartus Prime Design Suite software version 19.2, i-Intel FPGA IP inohlelo olusha lwenguqulo.

Inombolo ye-Intel FPGA IP (XYZ) ingashintsha ngenguqulo ngayinye yesofthiwe ye-Intel Quartus Prime. Ushintsho ku:

· X ikhombisa ukubuyekezwa okukhulu kwe-IP. Uma ubuyekeza isofthiwe ye-Intel Quartus Prime, kufanele uvuselele i-IP.
· U-Y ukhombisa i-IP ihlanganisa izici ezintsha. Khiqiza kabusha i-IP yakho ukuze ufake lezi zici ezintsha.
· Z ikhombisa i-IP ihlanganisa izinguquko ezincane. Khiqiza kabusha i-IP yakho ukuze ufake lezi zinguquko.

Ithebula 3.

I-F-Tile Serial Lite IV Intel FPGA IP Ulwazi Lokukhishwa

Into ye-IP Inguqulo ye-Intel Quartus Prime Version Idethi Yokukhishwa Ikhodi Yoku-oda

5.0.0 22.1 2022.04.28 IP-SLITE4F

Incazelo

2.2. Izici ezisekelwe
Ithebula elilandelayo libala izici ezitholakala ku-F-Tile Serial Lite IV Intel FPGA IP:

Thumela Impendulo

I-F-Tile Serial Lite IV Intel® FPGA IP Umhlahlandlela Womsebenzisi 7

2. I-F-Tile Serial Lite IV Intel FPGA IP Overview 683074 | 2022.04.28

Ithebula 4.

I-F-Tile Serial Lite IV Intel FPGA IP Izici

Isici

Incazelo

Ukudluliswa Kwedatha

· Ngemodi ye-PAM4:
- I-FHT isekela kuphela i-56.1, 58, kanye ne-116 Gbps ngomzila ngamunye onobukhulu bemizila emi-4.
- I-FGT isekela kufika ku-58 Gbps emzileni ngamunye onemizila emikhulu engu-12.
Bheka kuThebula 18 ekhasini 42 ukuze uthole imininingwane eyengeziwe ngamanani asekelwayo wedatha ye-transceiver yemodi ye-PAM4.
· Ngemodi ye-NRZ:
— I-FHT isekela kuphela i-28.05 kanye ne-58 Gbps ngomzila ngamunye onemizila emikhulu emi-4.
- I-FGT isekela kufika ku-28.05 Gbps emzileni ngamunye onemizila emikhulu engu-16.
Bheka kuThebula 18 ekhasini 42 ukuze uthole imininingwane eyengeziwe ngamanani asekelwayo wedatha ye-transceiver yemodi ye-NRZ.
· Isekela ukusakaza okuqhubekayo (Okuyisisekelo) noma izindlela zephakethe (Egcwele).
· Isekela amaphakethe ohlaka oluphezulu oluphansi.
· Isekela ukudluliswa kwe-byte granularity kuwo wonke usayizi wokuqhuma.
· Isekela ukuqondanisa komzila oqaliswe ngumsebenzisi noma ozenzakalelayo.
· Isekela isikhathi sokuhlela esihlelekayo.

PCS

· Isebenzisa ingqondo ye-IP eqinile ehlangana nama-transceivers e-Intel Agilex F-tile ukuze kuncishiswe insiza enengqondo ethambile.
· Isekela imodi yokushintshashintsha ye-PAM4 yokucaciswa kwe-100GBASE-KP4. I-RS-FEC ihlala inikwe amandla kule modulation mode.
· Isekela i-NRZ ngemodi yokushintshashintsha ye-RS-FEC oyikhethayo.
· Isekela ukuqoshwa kwekhodi okungu-64b/66b.

Ukutholwa Kwephutha Nokuphatha

· Isekela ukuhlolwa kwephutha le-CRC emikhondweni yedatha ye-TX ne-RX. · Isekela ukuhlolwa kwephutha lesixhumanisi se-RX. · Isekela ukutholwa kwephutha le-RX PCS.

Izixhumi ezibonakalayo

· Isekela kuphela ukudluliswa kwephakethe le-duplex eligcwele ngezixhumanisi ezizimele.
· Isebenzisa ukuxhumeka kwephoyinti nephoyinti kumadivayisi amaningi e-FPGA anobungane bokudlulisa obuphansi.
· Isekela imiyalo echazwe umsebenzisi.

2.3. Ileveli Yokusekela Inguqulo ye-IP

Isoftware ye-Intel Quartus Prime kanye nokusekelwa kwedivayisi ye-Intel FPGA ye-F-Tile Serial Lite IV Intel FPGA IP imi kanje:

Ithebula 5.

Inguqulo ye-IP kanye nezinga lokusekela

I-Intel Quartus Prime 22.1

Idivayisi ye-Intel Agilex F-tile transceivers

I-IP Version Ukulingisa Compilation Hardware Design

5.0.0

2.4. Ukusekela Ibanga Lesivinini Sedivayisi
I-F-Tile Serial Lite IV Intel FPGA IP isekela amamaki esivinini alandelayo kumadivayisi we-Intel Agilex F-tile: · Ibanga lesivinini se-Transceiver: -1, -2, kanye -3 · Ibanga lesivinini: -1, -2, kanye - 3

I-F-Tile Serial Lite IV Intel® FPGA IP Umhlahlandlela Womsebenzisi 8

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2. I-F-Tile Serial Lite IV Intel FPGA IP Overview 683074 | 2022.04.28

Ulwazi Oluhlobene
Ishidi Ledatha Yedivayisi ye-Intel Agilex Ulwazi olwengeziwe mayelana nezinga ledatha elisekelwayo kuma-transceivers e-Intel Agilex F-tile.

2.5. Ukusetshenziswa Kwensiza kanye nokubambezeleka

Izinsiza nokubambezeleka kwe-F-Tile Serial Lite IV Intel FPGA IP kutholwe ku-Intel Quartus Prime Pro Edition software version 22.1.

Ithebula 6.

Intel Agilex F-Tile Serial Lite IV Intel FPGA IP Resource Utilization
Isilinganiso sokubambezeleka sisekelwe ekubenimbezeleka kohambo olubuyayo kusukela kokokufaka okuyinhloko kwe-TX kuya kokuphumayo okuyinhloko kwe-RX.

Uhlobo lwe-Transceiver

Okuhlukile

Inombolo Yemodi Yemigqa Yedatha RS-FEC ALM

Ukubambezeleka (umjikelezo wewashi eliwumgogodla we-TX)

I-FGT

28.05 Gbps NRZ 16

Okuyisisekelo Abakhubazekile 21,691 65

Abakhubazekile Ngokugcwele 22,135 65

Okuyisisekelo Kunikwe amandla 21,915 189

Inikwe amandla ngokugcwele 22,452 189

58 Gbps PAM4 12

Okuyisisekelo Kunikwe amandla 28,206 146

Inikwe amandla ngokugcwele 30,360 146

I-FHT

58 Gbps NRZ

Okuyisisekelo Kunikwe amandla 15,793 146

Inikwe amandla ngokugcwele 16,624 146

58 Gbps PAM4 4

Okuyisisekelo Kunikwe amandla 15,771 154

Inikwe amandla ngokugcwele 16,611 154

116 Gbps PAM4 4

Okuyisisekelo Kunikwe amandla 21,605 128

Inikwe amandla ngokugcwele 23,148 128

2.6. I-Bandwidth Efficiency

Ithebula 7.

I-Bandwidth Efficiency

Imodi ye-Transceiver Eguquguqukayo

I-PAM4

Imodi yokusakaza RS-FEC

Kunikwe amandla Okugcwele

Okuyisisekelo Kuvunyelwe

Izinga lebhithi le-serial interface ku-Gbps (RAW_RATE)
Usayizi wokuqhuma wokudlulisa ngenombolo yegama (BURST_SIZE) (1)
Isikhathi sokuqondanisa kumjikelezo wewashi (SRL4_ALIGN_PERIOD)

56.0 2,048 4,096

56.0 4,194,304 4,096

Izilungiselelo

I-NRZ

Okugcwele

Ikhutshaziwe

Inikwe amandla

28.0

2,048

4,096

I-Basic Disabled 28.0

Inikwe amandla i-28.0

4,194,304

4,096

4,096 baqhubekile...

(1) I-BURST_SIZE yemodi Eyisisekelo isondela kokungapheli, yingakho kusetshenziswa inombolo enkulu.

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I-F-Tile Serial Lite IV Intel® FPGA IP Umhlahlandlela Womsebenzisi 9

2. I-F-Tile Serial Lite IV Intel FPGA IP Overview 683074 | 2022.04.28

Okuguquguqukayo

Izilungiselelo

64/66b ikhodi

0.96969697 0.96969697 0.96969697 0.96969697 0.96969697 0.96969697

Ngaphezulu kosayizi wokuqhuma kwenombolo yegama (BURST_SIZE_OVHD)

2 (2)

0 (3)

2 (2)

0 (3)

Isikhathi somaka wokuqondanisa 81,915 kumjikelezo wewashi (ALIGN_MARKER_PERIOD)

81,915

81,916

Ububanzi bomaka wokuqondanisa ku-5

umjikelezo wewashi

(ALIGN_MARKER_WIDTH)

Ukusebenza kahle komkhawulokudonsa (4)

0.96821788 0.96916433 0.96827698 0.96822967 0.96922348 0.96917616

Izinga elisebenzayo (Gbps) (5)

54.2202012 54.27320236 27.11175544 27.11043076 27.13825744 27.13693248

Ubuningi bewashi lomsebenzisi (MHz) (6)

423.59532225 424.00939437 423.62117875 423.6004806 424.0352725 424.01457

Ulwazi Oluhlobene Isilinganiso Sesixhumanisi Solwazi kanye Nesibalo Sokusebenza Komkhawulokudonsa ekhasini 40

(2) Kumodi egcwele, usayizi BURST_SIZE_OVHD uhlanganisa START/END Amagama okulawula abhanqiwe ekusakazeni idatha.
(3) Ngemodi Eyisisekelo, i-BURST_SIZE_OVHD ingu-0 ngoba akukho START/END ngesikhathi sokusakaza.
(4) Bheka Isilinganiso Sokuxhumanisa kanye nokubalwa Kokusebenza Komkhawulokudonsa ukuze uthole ukubala kokusebenza kahle komkhawulokudonsa.
(5) Bheka Isilinganiso Sokuxhumanisa kanye nokubalwa Kokusebenza Komkhawulokudonsa ukuze ubale isilinganiso esisebenzayo.
(6) Bheka Isilinganiso Sesixhumanisi kanye Nesibalo Sokusebenza Kahle Komkhawulokudonsa ukuze uthole umkhawulo wokubala ubuningi bewashi lomsebenzisi.

I-F-Tile Serial Lite IV Intel® FPGA IP Umhlahlandlela Womsebenzisi 10

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3. Ukuqalisa

3.1. Ukufaka kanye Nelayisensi Intel FPGA IP Cores

Ukufakwa kwesoftware ye-Intel Quartus Prime kufaka phakathi umtapo wezincwadi we-Intel FPGA IP. Lo mtapo wolwazi uhlinzeka ngamakhodi amaningi e-IP awusizo ukuze uwasebenzise ekukhiqizeni kwakho ngaphandle kwesidingo selayisense eyengeziwe. Amanye ama-Intel FPGA IP cores adinga ukuthengwa kwelayisense ehlukile ukuze asetshenziswe ekukhiqizeni. I-Intel FPGA IP Evaluation Mode ikuvumela ukuthi uhlole lawa makhodi e-Intel FPGA IP anelayisensi ngokulingisa nezingxenyekazi zekhompuyutha, ngaphambi kokuthatha isinqumo sokuthenga ilayisense eyinhloko ye-IP yokukhiqiza. Udinga kuphela ukuthenga ilayisense egcwele yokukhiqiza yama-Intel IP cores anelayisensi ngemva kokuqeda ukuhlola izingxenyekazi zekhompuyutha futhi usulungele ukusebenzisa i-IP ekukhiqizeni.

Isoftware ye-Intel Quartus Prime ifaka ama-IP cores ezindaweni ezilandelayo ngokuzenzakalelayo:

Umfanekiso 2.

Indlela Yokufaka I-IP Core
intelFPGA(_pro) quartus - Iqukethe isoftware ye-Intel Quartus Prime ip - Iqukethe umtapo wezincwadi we-Intel FPGA IP kanye nama-IP cores avela eceleni - Iqukethe ikhodi yomthombo welabhulali ye-Intel FPGA IP - Iqukethe umthombo we-IP we-Intel FPGA files

Ithebula 8.

Izindawo Zokufaka I-IP Core

Indawo

Isofthiwe

:intelFPGA_proquartusipaltera

I-Intel Quartus Prime Pro Edition

:/intelFPGA_pro/quartus/ip/altera Intel Quartus Prime Pro Edition

I-Platform Windows* Linux*

Qaphela:

Isofthiwe ye-Intel Quartus Prime ayisekeli izikhala endleleni yokufaka.

3.1.1. I-Intel FPGA IP Evaluation Mode
I-Intel FPGA IP Evaluation Mode yamahhala ikuvumela ukuthi uhlole ama-Intel FPGA IP cores anelayisense ekulingiseni nakwihardware ngaphambi kokuthenga. I-Intel FPGA IP Evaluation Mode isekela ukuhlaziya okulandelayo ngaphandle kwelayisensi eyengeziwe:
· Lingisa ukuziphatha kwe-Intel FPGA IP core onelayisensi ohlelweni lwakho. · Qinisekisa ukusebenza, usayizi, kanye nesivinini se-IP core ngokushesha futhi kalula. · Khiqiza uhlelo lwedivayisi olunesikhathi esilinganiselwe files yemiklamo ehlanganisa ama-IP cores. · Hlela idivayisi nge-IP core yakho futhi uqinisekise idizayini yakho kuhardware.

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I-Intel FPGA IP Evaluation Mode isekela izindlela zokusebenza ezilandelayo:
· Isebenzisa isikhathi eside—Ivumela ukusebenzisa idizayini equkethe ilayisensi ye-Intel FPGA IP unomphela ngoxhumano phakathi kwebhodi lakho nekhompyutha yokusingatha. Imodi eboshiwe idinga iqembu lesenzo sokuhlola esihlanganyelwe (JTAG) ikhebula elixhunywe phakathi kwe-JTAG imbobo ebhodini lakho kanye nekhompuyutha engusokhaya, esebenzisa i-Intel Quartus Prime Programmer ngesikhathi sokuhlolwa kwezingxenyekazi zekhompyutha. I-Programmer idinga kuphela ukufakwa okuncane kwesofthiwe ye-Intel Quartus Prime, futhi ayidingi ilayisense ye-Intel Quartus Prime. Ikhompuyutha engusokhaya ilawula isikhathi sokuhlola ngokuthumela isignali yezikhathi ezithile kudivayisi nge-JTAG itheku. Uma wonke amakhodi e-IP anelayisense kumodi yokuxhumanisa idizayini njengemodemu, isikhathi sokuhlola sisebenza kuze kuphele noma yikuphi ukuhlola okubalulekile kwe-IP. Uma wonke ama-IP cores asekela isikhathi sokuhlola esingenamkhawulo, idivayisi ayiphelelwa yisikhathi.
· Ayixhunyiwe–Ivumela ukusebenzisa idizayini equkethe i-IP enelayisensi isikhathi esilinganiselwe. I-IP core ibuyela kumodi engaxhumekile uma idivayisi inqamuka kukhompuyutha engusokhaya esebenzisa isofthiwe ye-Intel Quartus Prime. I-IP core iphinde ibuyele kumodi engaxhumekile uma noma yimuphi omunye umgogodla we-IP onelayisense eklanyweni ungasekeli imodi yokusebenzisa ifoni njengemodemu.
Uma isikhathi sokuhlola siphela kunoma iyiphi ilayisensi ye-Intel FPGA IP eklanyweni, umklamo uyayeka ukusebenza. Wonke ama-IP cores asebenzisa i-Intel FPGA IP Evaluation Mode aphelelwa isikhathi ngesikhathi esisodwa lapho noma yimuphi umgogodla we-IP uphelelwa yisikhathi. Uma isikhathi sokuhlola siphela, kufanele uhlele kabusha idivayisi ye-FPGA ngaphambi kokuqhubeka nokuqinisekisa ihadiwe. Ukuze unwebe ukusetshenziswa kwe-IP core ekukhiqizeni, thenga ilayisense egcwele yokukhiqiza ye-IP core.
Kufanele uthenge ilayisensi futhi ukhiqize ukhiye welayisense wokukhiqiza ogcwele ngaphambi kokwenza uhlelo lwedivayisi olungakhawulelwe file. Ngesikhathi se-Intel FPGA IP Evaluation Mode, I-Compiler ikhiqiza kuphela uhlelo lwedivayisi olunesikhathi esilinganiselwe file ( _time_limited.sof) esiphelelwa yisikhathi ngomkhawulo wesikhathi.

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Umfanekiso 3.

Ukugeleza Kwemodi Yokuhlola IP ye-Intel FPGA
Faka i-Intel Quartus Prime Software nge-Intel FPGA IP Library

I-Parameterize bese Uqinisekisa Ilayisense ye-Intel FPGA IP Core

Qinisekisa i-IP kusifanisi esisekelwe

Hlanganisa Idizayini ku-Intel Quartus Prime Software

Khiqiza i-Time-Limited Device Programming File

Hlela Idivayisi ye-Intel FPGA futhi Qinisekisa Ukusebenza Ebhodini
Ayikho i-IP elungele ukusetshenziswa kokukhiqiza?
Yebo Thenga Ukukhiqiza Okugcwele
IP License

Qaphela:

Faka i-IP enelayisensi kumikhiqizo yezentengiso
Bheka umhlahlandlela womsebenzisi we-IP ngayinye ngezinyathelo zokubeka imingcele kanye nemininingwane yokusebenzisa.
I-Intel ilayisensi ye-IP cores esihlalweni ngasinye, isisekelo esingapheli. Imali yelayisensi ihlanganisa ukugcinwa konyaka wokuqala kanye nokwesekwa. Kufanele uvuselele inkontileka yokulungisa ukuze uthole izibuyekezo, ukulungiswa kweziphazamisi, nosekelo lobuchwepheshe ngaphezu konyaka wokuqala. Kufanele uthenge ilayisense ephelele yokukhiqiza ye-Intel FPGA IP cores edinga ilayisense yokukhiqiza, ngaphambi kokukhiqiza izinhlelo files ongazisebenzisa isikhathi esingenamkhawulo. Ngesikhathi se-Intel FPGA IP Evaluation Mode, I-Compiler ikhiqiza kuphela uhlelo lwedivayisi olunesikhathi esilinganiselwe file ( _time_limited.sof) esiphelelwa yisikhathi ngomkhawulo wesikhathi. Ukuze uthole okhiye bakho belayisense yokukhiqiza, vakashela isikhungo selayisense ye-Intel FPGA Self-Service Licensing.
Izivumelwano Zelayisensi Yesofthiwe ye-Intel FPGA zilawula ukufakwa nokusetshenziswa kwama-IP cores anelayisensi, isofthiwe yokuklama ye-Intel Quartus Prime, nawo wonke ama-IP cores angenalayisensi.

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Ulwazi Oluhlobene · Isikhungo Sokusekela Amalayisense e-Intel FPGA · Isingeniso Sokufakwa KweSoftware ye-Intel FPGA Nokunikezwa Kwelayisense
3.2. Icacisa amapharamitha we-IP kanye nezinketho
Umhleli wepharamitha ye-IP ikuvumela ukuthi ulungiselele ngokushesha ukuhluka kwakho kwe-IP yangokwezifiso. Sebenzisa lezi zinyathelo ezilandelayo ukuze ucacise izinketho ze-IP namapharamitha kusofthiwe ye-Intel Quartus Prime Pro Edition.
1. Uma ungenayo iphrojekthi ye-Intel Quartus Prime Pro Edition ongahlanganisa kuyo i-F-Tile Serial Lite IV Intel FPGA IP yakho, kufanele udale eyodwa. a. Ku-Intel Quartus Prime Pro Edition, chofoza File Isilekeleli Sephrojekthi Esisha sokudala iphrojekthi entsha ye-Quartus Prime, noma File Vula Iphrojekthi ukuze uvule iphrojekthi ekhona ye-Quartus Prime. Iwizadi ikutshela ukuthi ucacise idivayisi. b. Cacisa umndeni wedivayisi ye-Intel Agilex bese ukhetha idivayisi yokukhiqiza ye-F-tile ehlangabezana nezimfuneko zebanga lesivinini ze-IP. c. Chofoza okuthi Qeda.
2. Kukhathalogi ye-IP, thola bese ukhetha i-F-Tile Serial Lite IV Intel FPGA IP. Iwindi le-New IP Variation liyavela.
3. Cacisa igama lezinga eliphezulu lokuhluka kwakho okusha kwangokwezifiso kwe-IP. Umhleli wepharamitha ugcina izilungiselelo zokuhlukahluka kwe-IP ku-a file okuthiwa .ip.
4. Chofoza okuthi KULUNGILE. Umhleli wepharamitha uyavela. 5. Cacisa amapharamitha wokuhluka kwakho kwe-IP. Bheka isigaba esithi Ipharamitha
ulwazi mayelana namapharamitha we-F-Tile Serial Lite IV Intel FPGA IP. 6. Ngokuzithandela, ukukhiqiza ibhentshi lokulingisa le-testbench noma ukuhlanganisa kanye nomklamo wehadiwe
example, landela imiyalelo ku-Design Example Umhlahlandlela Womsebenzisi. 7. Chofoza okuthi Khiqiza i-HDL. Ibhokisi lengxoxo lesizukulwane liyavela. 8. Cacisa okukhiphayo file ongakhetha kukho kokukhiqiza, bese uchofoza okuthi Khiqiza. Ukuhluka kwe-IP
files ukukhiqiza ngokuya ngemininingwane yakho. 9. Chofoza okuthi Qeda. Umhleli wepharamitha wengeza izinga eliphezulu elithi .ip file kweyamanje
iphrojekthi ngokuzenzakalelayo. Uma ucelwa ukuthi ungeze ngokwakho i-.ip file kuphrojekthi, chofoza okuthi Faka iphrojekthi/Susa Files kuphrojekthi yokwengeza i file. 10. Ngemva kokukhiqiza nokuqinisekisa ukuhluka kwakho kwe-IP, yenza imisebenzi yephinikhodi efanelekile ukuze uxhume izimbobo futhi usethe noma yimaphi amapharamitha e-RTL esenzo ngasinye afanelekile.
Amapharamitha Olwazi Oluhlobene ekhasini 42
3.3. Kwenziwe File Isakhiwo
Isoftware ye-Intel Quartus Prime Pro Edition ikhiqiza okuphumayo okulandelayo kwe-IP file isakhiwo.
Ukuze uthole ulwazi mayelana ne- file isakhiwo somklamo example, bhekisa ku-F-Tile Serial Lite IV Intel FPGA IP Design Example Umhlahlandlela Womsebenzisi.

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Umfanekiso 4. I-F-Tile Serial Lite IV Intel FPGA IP Ekhiqizwayo Files
.ip - Ukuhlanganiswa kwe-IP file

Ukuhluka kwe-IP files

_ Ukuhluka kwe-IP files

example_design

.cmp – Isimemezelo sengxenye ye-VHDL file _bb.v – Verilog HDL ibhokisi elimnyama EDA synthesis file _inst.v kanye .vhd – Sample instantiation izifanekiso .xml- XML umbiko file

Exampindawo ye-IP core design ex yakhoample files. Indawo ezenzakalelayo isibample_design, kodwa ucelwa ukuba ucacise indlela ehlukile.

.qgsimc - Iklelisa amapharamitha wokulingisa ukuze isekele ukukhiqizwa kabusha okukhulayo .qgsynthc - Iklelisa amapharamitha wokuhlanganisa ukusekela ukukhiqizwa kabusha okukhulayo

.qip - Iklelisa i-IP synthesis files

_generation.rpt- IP yokukhiqiza umbiko

.sopcinfo- Ukuhlanganiswa kwamathuluzi esoftware file .html- Ukuxhumana kanye nedatha yemephu yememori

.csv – Phina isabelo file

.spd - Ihlanganisa izikripthi zokulingisa ngazinye

Sim Sekulingisa files

synth IP synthesis files

.v Ukulingiswa kwezinga eliphezulu file

.v Ukuhlanganiswa kwe-IP yezinga eliphezulu file

Imibhalo yesilingisi

Imitapo yolwazi engaphansi

i-synth
I-subcore synthesis files

sim
I-Subcore Simulation files

Ithebula 9.

I-F-Tile Serial Lite IV Intel FPGA IP Yakhiwe Files

File Igama

Incazelo

.ip

Uhlelo Lomklami Wenkundla noma ukuhluka kwe-IP kwezinga eliphezulu file. igama olinikeza ukuhluka kwe-IP yakho.

.cmp

I-VHDL Component Declaration (.cmp) file umbhalo file equkethe izincazelo zasendaweni ezejwayelekile nezembobo ongazisebenzisa ekwakhiweni kwe-VHDL files.

.html

Umbiko oqukethe ulwazi lokuxhumana, imephu yememori ebonisa ikheli lesigqila ngasinye ngokuphathelene nenkosi ngayinye exhunywe kuyo, kanye nezabelo zepharamitha.

_isizukulwane.rpt

Ilogi yokukhiqiza ye-IP noma ye-Platform Designer file. Isifinyezo semilayezo ngesikhathi sokukhiqizwa kwe-IP.

.qgsimc

Ifaka kuhlu amapharamitha wokulingisa ukusekela ukukhiqizwa kabusha okukhulayo.

.qgsynthc

Ibala amapharamitha we-synthesis ukusekela ukukhiqizwa kabusha okukhulayo.

.qip

Iqukethe lonke ulwazi oludingekayo mayelana nengxenye ye-IP ukuze kuhlanganiswe futhi kuhlanganiswe ingxenye ye-IP kusofthiwe ye-Intel Quartus Prime.
waqhubeka...

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File Igama .sopcinfo
.csv .spd _bb.v _inst.v noma _inst.vhd .regmap
.svd
.v noma .vhd mentor/ synopsy/vcs/ synopsy/vcsmx/ xcelium/ submodules/ /

Incazelo
Ichaza ukuxhumana namapharamitha wengxenye ye-IP ohlelweni lwakho Lomklami Wenkundla. Ungakwazi ukuhlaziya okuqukethwe kwakho ukuze uthole izidingo lapho uthuthukisa izishayeli zesofthiwe zezingxenye ze-IP. Amathuluzi awela phansi njenge-Nios® II Tool chain asebenzisa lokhu file. I-.sopcinfo file kanye nohlelo.h file okwenzelwe uchungechunge lwamathuluzi we-Nios II kufaka phakathi imininingwane yemephu yekheli yesigqila ngasinye esihlobene nenkosi ngayinye efinyelela isigqila. Abaphathi abahlukene bangase babe nemephu yamakheli ehlukile ukuze bafinyelele ingxenye ethile yesigqila.
Iqukethe ulwazi mayelana nesimo sokuthuthukisa sengxenye ye-IP.
Okokufaka okudingekayo file ukuze i-ip-make-simscript ikhiqize imibhalo yokulingisa izilingisi ezisekelwayo. I-.spd file iqukethe uhlu lwe files enzelwe ukulingiswa, kanye nolwazi mayelana nezinkumbulo ongaziqalisa.
Ungasebenzisa i-Verilog black-box (_bb.v) file njengesimemezelo semojuli engenalutho esizosetshenziswa njengebhokisi elimnyama.
I-HDL example instantiation template. Ungakopisha futhi unamathisele okuqukethwe kwalokhu file ku-HDL yakho file ukuqinisa ukuhlukahluka kwe-IP.
Uma i-IP iqukethe ulwazi lwerejista, .regmap file yakha. I-.regmap file ichaza imininingwane yemephu yerejista ye-master interfaces nesigqila. Lokhu file igcwalisa i-.sopcinfo file ngokunikeza ulwazi lwerejista enemininingwane eminingi mayelana nohlelo. Lokhu kunika amandla ukuboniswa kwerejista views kanye nezibalo ezenziwa ngokwezifiso zomsebenzisi Kukhonsoli Yesistimu.
Ivumela amathuluzi okulungisa iphutha lesistimu (HPS) ukuthi view amamephu okubhalisa ama-peripheral axhunywe ku-HPS ohlelweni Lokuklama Ingxenyekazi. Ngesikhathi sokuhlanganiswa, i-.svd files yezindawo zokusebenzelana zesigqila ezibonakala kubaphathi be-System Console zigcinwa ku-.sof file esigabeni sokulungisa iphutha. I-System Console ifunda lesi sigaba, lapho uMklami Wenkundla angabuza mayelana nolwazi lwemephu yokubhalisa. Ezigqileni zesistimu, uMklami Wenkundla angafinyelela amarejista ngamagama.
I-HDL files eziqinisa i-submodule ngayinye noma i-IP yengane ukuze ihlanganise noma ilingise.
Iqukethe iskripthi se-ModelSim*/QuestaSim* msim_setup.tcl ukuze umise futhi uqalise ukulingisa.
Iqukethe iskripthi segobolondo vcs_setup.sh sokusetha nokusebenzisa ukulingisa kwe-VCS*. Iqukethe iskripthi segobolondo vcsmx_setup.sh kanye ne-synopsy_sim.setup file ukusetha nokusebenzisa ukulingisa kwe-VCS MX.
Iqukethe iskripthi segobolondo xcelium_setup.sh nokunye ukusetha files ukusetha nokusebenzisa ukulinganisa kwe-Xcelium*.
Iqukethe i-HDL files yamamojula amancane e-IP.
Ngohla lwemibhalo lwe-IP lwengane ngayinye olukhiqiziwe, Umklami Wenkundla ukhiqiza i-synth/ kanye ne-sim/ sub-directory.

3.4. Ilinganisa i-Intel FPGA IP Cores
Isofthiwe ye-Intel Quartus Prime isekela ukulingiswa kwe-IP core RTL kuzifanisi ezithile ze-EDA. Ukukhiqizwa kwe-IP ngokuzikhethela kudala ukulingisa files, okuhlanganisa imodeli yokulingisa esebenzayo, noma iyiphi ibhentshi yokuhlola (noma isibample design), kanye nezikripthi zokusethwa kwesifanisi esiqondene nomthengisi kumongo ngamunye we-IP. Ungasebenzisa imodeli yokulingisa esebenzayo nanoma iyiphi ibhentshi noma i-example design yokulingisa. Okukhiphayo kokukhiqiza i-IP kungase kuhlanganise nemibhalo ezohlanganiswa futhi iqalise noma iyiphi i-testbench. Izikripthi ziklelisa wonke amamodeli noma imitapo yolwazi oyidingayo ukuze ulingise i-IP core yakho.

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Isofthiwe ye-Intel Quartus Prime ihlinzeka ngokuhlanganiswa nezilingisi eziningi futhi isekela ukugeleza kokulingisa okuningi, okuhlanganisa nokugeleza kwakho kokulingisa okubhaliwe nokwezifiso. Kungakhathaliseki ukuthi yikuphi ukugeleza okukhethayo, ukulingisa okuyinhloko kwe-IP kubandakanya lezi zinyathelo ezilandelayo:
1. Khiqiza i-IP HDL, i-testbench (noma isibample design), kanye neskripthi sokusetha isilingisi files.
2. Setha indawo yakho yesilingisi nanoma yimiphi imibhalo yokulingisa.
3. Hlanganisa imitapo yolwazi eyimodeli.
4. Sebenzisa isilingisi sakho.

3.4.1. Ukulingisa kanye Nokuqinisekisa Idizayini

Ngokuzenzakalelayo, umhleli wepharamitha ukhiqiza imibhalo eqondene nesifanisi equkethe imiyalo yokuhlanganisa, ukuchaza, nokulingisa amamodeli e-Intel FPGA IP kanye nelabhulali yemodeli yokulingisa. files. Ungakopisha imiyalo kusikripthi sakho sokulingisa se-testbench, noma uyihlele files ukwengeza imiyalo yokuhlanganisa, ukuchaza, kanye nokulingisa umklamo wakho nebhentshi lokuhlola.

Ithebula 10. Intel FPGA IP Core Simulation Scripts

Isifanisi

File Uhla lwemibhalo

ImodeliSim

_sim/umeluleki

Sbusiso

I-VCS

_sim/synopsy/vcs

I-VCS MX

_sim/synopsy/vcsmx

I-Xcelium

_sim/xcelium

Iskriphthi msim_setup.tcl (7)
vcs_setup.sh vcsmx_setup.sh synopsys_sim.setup xcelium_setup.sh

3.5. Ihlanganisa Ama-IP Cores Kwamanye Amathuluzi EDA
Ngokuzithandela, sebenzisa elinye ithuluzi elisekelwayo le-EDA ukuze uhlanganise umklamo ohlanganisa ama-Intel FPGA IP cores. Lapho ukhiqiza i-IP core synthesis files ukusetshenziswa namathuluzi okuhlanganiswa e-EDA yenkampani yangaphandle, ungakha indawo kanye nohlu lwenethiwekhi lokulinganisa isikhathi. Ukuze unike amandla ukukhiqiza, vula okuthi Dala isikhathi nezilinganiso zensiza zamathuluzi okuhlanganiswa enkampani yangaphandle ye-EDA lapho wenza ngendlela oyifisayo ukuhluka kwakho kwe-IP.
Uhlu lwenethiwekhi yendawo nokulinganisa isikhathi luchaza uxhumo oluyinhloko lwe-IP kanye nezakhiwo, kodwa alufaki imininingwane mayelana nokusebenza kwangempela. Lolu lwazi lunika amandla amathuluzi athile okuhlanganiswa okuvela eceleni ukuthi abike kangcono indawo nezilinganiso zesikhathi. Ngaphezu kwalokho, amathuluzi okuhlanganiswa angasebenzisa ulwazi lwesikhathi ukuze afinyelele ukulungiselelwa okuqhutshwa isikhathi futhi athuthukise ikhwalithi yemiphumela.
Isoftware ye-Intel Quartus Prime ikhiqiza i- _syn.v uhlu lwenethiwekhi file ngefomethi ye-Verilog HDL, kungakhathaliseki ukuthi ukhiphani file ifomethi oyicacisayo. Uma usebenzisa lolu hlu lwe-net ukuze luhlanganise, kufanele ufake i-IP core wrapper file .v noma .vhd kuphrojekthi yakho ye-Intel Quartus Prime.

(7) Uma ungamisanga inketho yethuluzi le-EDA– ekuvumela ukuthi uqale izifanisi ze-EDA ezivela eceleni kusukela ku-Intel Quartus Prime software–sebenzisa lesi script ku-ModelSim noma i-QuestaSim simulator Tcl console (hhayi kusofthiwe ye-Intel Quartus Prime Tcl console) ukugwema noma imaphi amaphutha.

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3.6. Ukuhlanganisa Idizayini Egcwele
Ungasebenzisa umyalo Wokuqala Wokuhlanganiswa kumenyu Yokucubungula kusofthiwe ye-Intel Quartus Prime Pro Edition ukuze uhlanganise umklamo wakho.

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Umfanekiso 5.

I-F-Tile Serial Lite IV Intel FPGA IP iqukethe i-MAC ne-Ethernet PCS. I-MAC ixhumana ne-PCS yangokwezifiso ngokusebenzisa ukuxhumana kwe-MII.

I-IP isekela izindlela ezimbili zokuguquguquka:
· I-PAM4–Ihlinzeka ngenombolo yemizila engu-1 ukuya kweyi-12 ukuze ikhethwe. I-IP ihlale iqinisekisa amashaneli e-PCS amabili kumzila ngamunye kumodi yokumodulation ye-PAM4.
· I-NRZ–Ihlinzeka ngenombolo yemizila engu-1 ukuya kweyi-16 ukuze ikhethwe.

Imodi ngayinye yokushintshashintsha isekela izindlela ezimbili zedatha:
· Imodi eyisisekelo–Lena imodi yokusakaza emsulwa lapho idatha ithunyelwa ngaphandle kwephakethe lokuqala, umjikelezo ongenalutho, nokuphela kwephakethe ukuze kwandiswe umkhawulokudonsa. I-IP ithatha idatha yokuqala evumelekile njengesiqalo sokuqhuma.

Ukudluliswa Kwedatha Yemodi Eyisisekelo tx_core_clkout tx_avs_ready

tx_avs_valid tx_avs_data rx_core_clkout rx_avs_ready

D0 D1 D2 D3 D4 D5 D6 D7 D8 D9

rx_avs_valid rx_avs_data

D0 D1 D2 D3 D4 D5 D6 D7 D8 D9

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Umfanekiso 6.

· Imodi egcwele-Lena yimodi yephakethe yokudlulisa idatha. Kule modi, i-IP ithumela ukuqhuma kanye nomjikelezo wokuvumelanisa ekuqaleni nasekupheleni kwephakethe njengama-delimiters.

Ukudluliswa Kwedatha Yemodi Egcwele tx_core_clkout

tx_avs_ready tx_avs_valid tx_avs_startofpacket tx_avs_endofpacket
tx_avs_data rx_core_clkout rx_avs_ready rx_avs_valid rx_avs_startofpacket rx_avs_endofpacket

D0 D1 D2 D3 D4 D5 D6 D7 D8 D9

rx_avs_idatha

D0 D1 D2 D3 D4 D5 D6 D7 D8 D9

Ulwazi Oluhlobene · F-Tile Serial Lite IV Intel FPGA IP Overview ekhasini 6 · F-Tile Serial Lite IV Intel FPGA IP Design Example Umhlahlandlela Womsebenzisi

4.1. Idatha ye-TX
I-datapath ye-TX iqukethe izingxenye ezilandelayo: · I-adaptha ye-MAC · Lawula ibhulokhi yokufaka amagama · CRC · Isishumeki se-MII · Ibhulokhi ye-PCS · Ibhulokhi le-PMA

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Umfanekiso 7. I-TX Datapath

Kusuka kumqondo womsebenzisi

I-TX MAC

I-Avalon Streaming Interface

I-adaptha ye-MAC

Lawula Ukufakwa Kwamagama

CRC

I-MII Encoder

I-MII Interface Custom PCS
PCS kanye PMA

I-TX Serial Interface Kwenye Idivayisi ye-FPGA

4.1.1. I-adaptha ye-TX MAC
I-adaptha ye-TX MAC ilawula ukudluliswa kwedatha kunengqondo yomsebenzisi isebenzisa isixhumi esibonakalayo sokusakaza se-Avalon®. Leli bhulokhi lisekela ukudluliswa kolwazi oluchazwe ngumsebenzisi nokulawula ukugeleza.

Idlulisela Ulwazi Oluchazwe Ngabasebenzisi

Kumodi egcwele, i-IP inikeza isignali engu-tx_is_usr_cmd ongayisebenzisa ukuqalisa umjikelezo wolwazi oluchazwe ngumsebenzisi olufana nokudluliswa kwe-XOFF/XON kumqondo womsebenzisi. Ungakwazi ukuqalisa umjikelezo wokudlulisa ulwazi oluchazwe umsebenzisi ngokugomela lesi siginali futhi udlulise ulwazi usebenzisa i-tx_avs_data kanye nokugomela kwe-tx_avs_startofpacket kanye namasiginali we-tx_avs_valid. Ibhulokhi ibe isisusa u-tx_avs_ready imijikelezo emibili.

Qaphela:

Isici solwazi esichazwe ngumsebenzisi sitholakala kuphela kumodi egcwele.

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Umfanekiso 8.

Ukulawula Ukugeleza

Kunezimo lapho i-TX MAC ingakakulungeli ukuthola idatha evela kungqondongqondo yomsebenzisi njengaphakathi nenqubo yokuqondisa kabusha isixhumanisi noma lapho ingekho idatha etholakalayo yokudluliselwa evela kungqondongqondo yomsebenzisi. Ukuze ugweme ukulahleka kwedatha ngenxa yalezi zimo, i-IP isebenzisa isignali ethi tx_avs_ready ukuze ilawule ukugeleza kwedatha kunengqondo yomsebenzisi. I-IP desserts isignali uma izimo ezilandelayo zenzeka:
· Uma i-tx_avs_startofpacket igonyelwa, i-tx_avs_ready ikhishwa umjikelezo wewashi elilodwa.
· Uma i-tx_avs_endofpacket igonyelwa, i-tx_avs_ready ikhishwa umjikelezo wewashi elilodwa.
· Uma noma yimaphi ama-CW abhanqiwe kuthiwa tx_avs_ready ikhishwa imijikelezo yewashi emibili.
· Uma ukufakwa komaka wokuqondanisa kwe-RS-FEC kwenzeka kusixhumi esibonakalayo se-PCS ngokwezifiso, i-tx_avs_ready ikhishwa imijikelezo yewashi emine.
· Yonke imijikelezo yewashi engu-17 Ethernet kumodi yokushintshashintsha ye-PAM4 kanye nayo yonke imijikelezo yewashi engu-33 ye-Ethernet kumodi yokushintshashintsha kwe-NRZ. I-tx_avs_ready ikhishwa umjikelezo wewashi elilodwa.
· Uma logic yomsebenzisi amadesethi tx_avs_valid ngesikhathi kungekho ukudluliswa kwedatha.

Imidwebo yesikhathi elandelayo iyisibampi-adaptha ye-TX MAC esebenzisa okuthi tx_avs_ready ukulawula ukugeleza kwedatha.

Ukulawula Ukugeleza nge-tx_avs_valid Deassertion kanye START/END nama-CW abhanqiwe

tx_core_clkout

tx_avs_valid tx_avs_data

I-D1 D2 D3

Amadesethi esiginali avumelekile

I-D5 D6

tx_avs_ready tx_avs_startofpacket

Amadesethi esignali alungile ukuze imijikelezo emibili ifakwe END-STRT CW

tx_avs_endofpacket

idatha_ye-usrif

I-D1 D2 D3

CW_idatha

I-DN END STT D0 D1 D2 D3 AYINALUTHO D4

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Umfanekiso 9.

Ukulawula Ukugeleza Ngokufaka Umaka Wokuqondanisa
tx_core_clkout tx_avs_valid

tx_avs_data tx_avs_ready

I-DN-5 DN-4 DN-3 DN-2 DN-1

I-DN+1

01234

tx_avs_startofpacket tx_avs_endofpacket

idatha_ye-usrif CW_idatha CRC_datha ye-MII_data

DN-1 DN DN DN DN DN DN DN DN+1 DN-1 DN DN DN DN DN DN DN +1 DN-1 DN DN DN DN DN DN DN DN+1

i_sl_tx_mii_valid

i_sl_tx_mii_d[63:0]

I-DN-1

I-DN+1

i_sl_tx_mii_c[7:0]

0x0

i_sl_tx_mii_am

01234

i_sl_tx_mii_am_pre3

01234

Umfanekiso 10.

Ukulawula Ukugeleza Nama-CW Abhanqiwe START/END Aqondana Nokufakwa Komaka Wokuqondanisa

tx_core_clkout tx_avs_valid

tx_avs_idatha

I-DN-5 DN-4 DN-3 DN-2 DN-1

tx_avs_ready

012 345 6

tx_avs_startofpacket

tx_avs_endofpacket

idatha_ye-usrif

DN-1 DN-1 DN-1 DN-1 DN-1 DN-1 END STT D0

CW_idatha

DN-1 DN-1 DN-1 DN-1 DN-1 DN-1 END STT D0

Idatha_ye-CRC

DN-1 DN-1 DN-1 DN-1 DN-1 DN-1 END STT D0

Idatha_ye-MII

DN-1 DN-1 DN-1 DN-1 DN-1 DN-1 END STT D0

i_sl_tx_mii_valid

i_sl_tx_mii_d[63:0]

I-DN-1

QEDA U-STRT D0

i_sl_tx_mii_c[7:0]

0x0

i_sl_tx_mii_am i_sl_tx_mii_am_pre3

01234

4.1.2. Control Word (CW) Ukufakwa
I-F-Tile Serial Lite IV Intel FPGA IP yakha ama-CW ngokususelwa kumasiginali okokufaka avela kumqondo womsebenzisi. Ama-CW akhombisa izinqamuli zephakethe, ulwazi lwesimo sokudlulisela noma idatha yomsebenzisi kubhulokhi ye-PCS futhi asuselwa kumakhodi okulawula e-XGMII.
Ithebula elilandelayo libonisa incazelo yama-CW asekelwe:

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Ithebula 11.
QALA QEDA UKUHLANGANISA

Incazelo yama-CW asekelwe

Inombolo Yamagama (igama elingu-1

= 64 amabhithi)

Yebo

EMPTY_CYC

Yebo

I-IDLE

Cha

IDATHA

Yebo

In-band

Incazelo
Ukuqala kwe-delimiter yedatha. Ukuphela kwe-delimiter yedatha. Igama lokulawula (CW) lokuqondanisa kwe-RX. Umjikelezo ongenalutho ekudluliselweni kwedatha. I-IDLE (ngaphandle kwebhendi). Inkokhelo.

Ithebula 12. Incazelo Yenkundla ye-CW
Inkambu ye-RSVD inombolo_valid_bytes_eob
I-EMPTY eop sop seop qondanisa i-CRC32 usr

Incazelo
Inkambu egciniwe. Ingasetshenziselwa isandiso esizayo. Iboshelwe ku-0.
Inombolo yamabhayithi avumelekile egameni lokugcina (64-bit). Leli yinani elingu-3bit. · 3'b000: 8 byte · 3'b001: 1 byte · 3'b010: 2 byte · 3'b011: 3 byte · 3'b100: 4 bytes · 3'b101: 5 byte · 3'b110: 6 bytes · 3'b111: 7 amabhayithi
Inombolo yamagama angavumelekile ekugcineni kokuqhuma.
Ibonisa isixhumi esibonakalayo sokusakaza-bukhoma se-RX Avalon ukuze igomele isignali yokuphela kwephakethe.
Ibonisa isixhumi esibonakalayo sokusakaza-bukhoma se-RX Avalon ukuze igomele isignali yokuqala kwephakethe.
Ibonisa i-interface yokusakaza ye-RX Avalon ukuze igomele ukuqala kwephakethe kanye nokuphela kwephakethe kumjikelezo ofanayo.
Hlola ukuqondanisa kwe-RX.
Amanani ekhompuyutha ye-CRC.
Ibonisa ukuthi igama lokulawula (CW) liqukethe ulwazi oluchazwe umsebenzisi.

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4.1.2.1. Ukuqala kokuqhuma kwe-CW

Umfanekiso 11. Ifomethi ye-CW yokuqala yokuqhuma

QALA

63:56

I-RSVD

55:48

I-RSVD

47:40

I-RSVD

idatha

39:32 31:24

I-RSVD RSVD

23:16

sop usr align=0 seop

15:8

isiteshi

7:0

'hFB(QALA)

ukulawula 7:0

Ithebula 13.

Kumodi egcwele, ungafaka i-START CW ngokugomela isignali ye-tx_avs_startofpacket. Uma ugomela kuphela isignali ye-tx_avs_startofpacket, i-sop bit iyasethwa. Uma ugomela kokubili amasiginali we-tx_avs_startofpacket kanye ne-tx_avs_endofpacket, ibhithi ye-seop iyasethwa.

QALA Amanani Enkundla ye-CW
I-Field sop/seop
usr (8)
qondanisa

Inani

Kuye ngesignali ye-tx_is_usr_cmd:

1: Lapho tx_is_usr_cmd = 1

0: Lapho tx_is_usr_cmd = 0

Kumodi Eyisisekelo, i-MAC ithumela i-START CW ngemuva kokuthi ukusetha kabusha kukhishwe. Uma ingekho idatha etholakalayo, i-MAC iqhubeka ithumela i-EMPTY_CYC ebhangqwe ne-END kanye nama-START CWs uze uqale ukuthumela idatha.

4.1.2.2. Ukuphela kokuqhuma kwe-CW

Umfanekiso 12. Ifomethi ye-CW yokuphela kokuqhuma

PHELA

63:56

'hFD

55:48

I-CRC32[31:24]

47:40

I-CRC32[23:16]

idatha 39:32 31:24

CRC32[15:8] CRC32[7:0]

23:16 eop=1 RSVD RSVD RSVD

I-RSVD

15:8

I-RSVD

AKUNALUTHO

7:0

I-RSVD

inombolo_evumelekile_amabhayithi_eob

ukulawula

7:0

(8) Lokhu kusekelwa kuphela kumodi egcwele.
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Ithebula 14.

I-MAC ifaka i-END CW uma i-tx_avs_endofpacket igonyelwa. I-END CW iqukethe inani lamabhayithi avumelekile egameni ledatha lokugcina kanye nolwazi lwe-CRC.

Inani le-CRC liwumphumela we-32-bit CRC wedatha ephakathi kwe-START CW negama ledatha ngaphambi kwe-END CW.

Ithebula elilandelayo libonisa amanani ezinkambu kokuthi END CW.

QEDA Amanani Enkambu ye-CW
I-Field eop CRC32 num_valid_bytes_eob

Inani 1
Inani elibaliwe le-CRC32. Inombolo yamabhayithi avumelekile egameni ledatha lokugcina.

4.1.2.3. Ukuqondanisa Kumataniswe CW

Umfanekiso 13. Ukuqondanisa Kubhanqiwe Ifomethi ye-CW

QONGAnisa i-CW Bhangqa ne-START/END

64+8bits XGMII Interface

QALA

63:56

I-RSVD

55:48

I-RSVD

47:40

I-RSVD

idatha

39:32 31:24

I-RSVD RSVD

23:16 eop=0 isop=0 usr=0 ukuqondanisa=1 okop=0

15:8

I-RSVD

7:0

'hFB

ukulawula 7:0

64+8bits XGMII Interface

PHELA

63:56

'hFD

55:48

I-RSVD

47:40

I-RSVD

idatha

39:32 31:24

I-RSVD RSVD

23:16 eop=0 RSVD RSVD RSVD

I-RSVD

15:8

I-RSVD

7:0

I-RSVD

ukulawula 7:0

I-ALIGN CW iyi-CW ebhanqiwe ne-START/END noma END/START CWs. Ungafaka i-ALIGN ebhanqiwe i-CW ngokugomela isignali ethi tx_link_reinit, usethe isibali Senkathi Yokuqondanisa, noma ngokuqalisa ukusetha kabusha. Uma i-ALIGN ebhanqiwe i-CW ifakiwe, inkambu yokuqondanisa isethelwe ku-1 ukuze kuqaliswe ibhulokhi yokuqondisa umamukeli ukuze kuhlolwe ukuqondana kwedatha kuyo yonke imizila.

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Ithebula 15.

LINGANISA Amanani Enkundla ye-CW
Qondanisa inkambu
eop sop usr seop

Inani 1 0 0 0 0

4.1.2.4. I-CW yomjikelezo ongenalutho

Umfanekiso 14. Ifomethi ye-CW yomjikelezo ongenalutho

EMPTY_CYC Bhangqa ne-END/START

64+8bits XGMII Interface

PHELA

63:56

'hFD

55:48

I-RSVD

47:40

I-RSVD

idatha

39:32 31:24

I-RSVD RSVD

23:16 eop=0 RSVD RSVD RSVD

I-RSVD

15:8

I-RSVD

7:0

I-RSVD

ukulawula 7:0

64+8bits XGMII Interface

QALA

63:56

I-RSVD

55:48

I-RSVD

47:40

I-RSVD

idatha

39:32 31:24

I-RSVD RSVD

23:16

sop=0 usr=0 qondanisa=0 seop=0

15:8

I-RSVD

7:0

'hFB

ukulawula 7:0

Ithebula 16.

Uma ususa u-tx_avs_valid emijikelezweni yewashi emibili ngesikhathi sokuqhuma, i-MAC ifaka i-EMPTY_CYC CW ebhangqwe END/START nama-CW. Ungasebenzisa le CW uma ingekho idatha etholakalayo yokudluliselwa okwesikhashana.

Uma ususa u-tx_avs_valid umjikelezo owodwa, i-IP deassserts tx_avs_valid kabili isikhathi se-tx_avs_valid deassertion ukukhiqiza ipheya END/START CWs.

EMPTY_CYC CW Amanani Enkundla
Qondanisa inkambu
eop

Inani 0 0

waqhubeka...

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I-Field sop usr seop

Inani 0 0 0

4.1.2.5. I-CW engasebenzi

Umfanekiso 15. Ifomethi ye-CW engenzi lutho

IDLE CW

63:56

'h07

55:48

'h07

47:40

'h07

idatha

39:32 31:24

'h07'h07

23:16

'h07

15:8

'h07

7:0

'h07

ukulawula 7:0

I-MAC ifaka i-IDLE CW uma kungekho ukudluliswa. Ngalesi sikhathi, isignali ye-tx_avs_valid iphansi.
Ungasebenzisa i-IDLE CW uma ukudluliswa kokuqhuma sekuqediwe noma ukudlulisela kusesimweni sokungenzi lutho.

4.1.2.6. IZwi ledatha

Igama ledatha liwumthwalo okhokhelwayo wephakethe. Amabhithi okulawula e-XGMII wonke asethelwe ku-0 ngefomethi yegama ledatha.

Umfanekiso 16. Ifomethi yeZwi leDatha

64+8 bits XGMII Interface

IDATHA IZWI

63:56

idatha yomsebenzisi 7

55:48

idatha yomsebenzisi 6

47:40

idatha yomsebenzisi 5

idatha

39:32 31:24

idatha yomsebenzisi 4 idatha yomsebenzisi 3

23:16

idatha yomsebenzisi 2

15:8

idatha yomsebenzisi 1

7:0

idatha yomsebenzisi 0

ukulawula 7:0

4.1.3. I-TX CRC
Ungakwazi ukunika amandla ibhulokhi ye-TX CRC usebenzisa ipharamitha ethi Vumela i-CRC kusihleli sepharamitha ye-IP. Lesi sici sisekelwa kuzo zombili izindlela eziyisisekelo nezigcwele.

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I-MAC yengeza inani le-CRC ku-END CW ngokugomela isiginali ethi tx_avs_endofpacket. Kumodi ye-BASIC, i-ALIGN CW kuphela ebhangqwe ne-END CW equkethe inkambu evumelekile ye-CRC.
Ibhulokhi ye-TX CRC ihlangana ne-TX Control Word Insertion kanye nebhulokhi ye-TX MII Encode. Ibhulokhi ye-TX CRC ihlanganisa inani le-CRC yenani elingu-64-bit idatha yomjikelezo ngamunye kusukela ku-START CW kuye ku-END CW.
Ungakwazi ukugomela isiginali ye-crc_error_inject yokonakalisa ngamabomu idatha emzileni othile ukuze udale amaphutha e-CRC.

4.1.4. Isifaki khodi se-TX MII

Isifaki khodi se-TX MII siphatha ukudluliswa kwephakethe kusuka ku-MAC kuya ku-TX PCS.

Isibalo esilandelayo sibonisa iphethini yedatha ebhasini le-8-bit MII kumodi yokushintshashintsha ye-PAM4. I-START kanye ne-END CW ivela kanye emigwaqweni emibili ye-MII.

Umfanekiso 17. I-PAM4 Modulation Mode Iphethini yedatha ye-MII

UMJIKELELE 1

UMJIKELELE 2

UMJIKELELE 3

UMJIKELELE 4

UMJIKELELE 5

SOP_CW

DATA_1

DATA_9 DATA_17

I-IDLE

DATA_DUMMY SOP_CW
DATA_DUMMY

DATA_2 DATA_3 DATA_4

DATA_10 DATA_11 DATA_12

DATA_18 DATA_19 DATA_20

EOP_CW IDLE
EOP_CW

SOP_CW

DATA_5 DATA_13 DATA_21

I-IDLE

DATA_DUMMY DATA_6 DATA_14 DATA_22 EOP_CW

SOP_CW DATA_DUMMY

DATA_7 DATA_8

DATA_15 DATA_16

DATA_23 DATA_24

IDLE EOP_CW

Isibalo esilandelayo sibonisa iphethini yedatha ebhasini le-MII le-8-bit kumodi yokushintshashintsha ye-NRZ. I-START kanye ne-END CW ivela kuyo yonke imizila ye-MII.

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Umfanekiso 18. Iphethini yedatha ye-NRZ ye-MII yedatha

UMJIKELELE 1

UMJIKELELE 2

UMJIKELELE 3

SOP_CW

DATA_1

DATA_9

SOP_CW

DATA_2 DATA_10

SOP_CW SOP_CW

DATA_3 DATA_4

DATA_11 DATA_12

SOP_CW

DATA_5 DATA_13

SOP_CW

DATA_6 DATA_14

SOP_CW

DATA_7 DATA_15

SOP_CW

DATA_8 DATA_16

CYCLE 4 DATA_17 DATA_18 DATA_19 DATA_20 DATA_21 DATA_22 DATA_23 DATA_24

I-CYCLE 5 EOP_CW EOP_CW EOP_CW EOP_CW EOP_CW EOP_CW EOP_CW EOP_CW

4.1.5. I-TX PCS ne-PMA
I-F-Tile Serial Lite IV Intel FPGA IP imisa i-F-tile transceiver ibe yimodi ye-Ethernet PCS.

4.2. Idatha ye-RX
I-datapath ye-RX iqukethe izingxenye ezilandelayo: · Ibhulokhi ye-PMA · Ibhulokhi ye-PCS · Idekhoda ye-MII · CRC · Ibhulokhi yeDeskew · Ibhulokhi yokuLawula i-Word

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Umfanekiso 19. I-RX Datapath

Ku-logic yomsebenzisi I-Avalon Streaming Interface
I-RX MAC
Lawula Ukususwa Kwamagama
Deskew

CRC

Idekhoda ye-MII

I-MII Interface Custom PCS
PCS kanye PMA

I-RX Serial Interface Evela Kwenye Idivayisi ye-FPGA
4.2.1. I-RX PCS ne-PMA
I-F-Tile Serial Lite IV Intel FPGA IP imisa i-F-tile transceiver ibe imodi ye-Ethernet PCS.
4.2.2. Idekhoda ye-RX MII
Leli bhulokhi likhomba ukuthi ingabe idatha engenayo iqukethe igama lokulawula kanye nezimpawu zokuqondanisa. Idekhoda ye-RX MII ikhipha idatha ngendlela ye-1-bit evumelekile, inkomba yomaka engu-1-bit, inkomba yokulawula engu-1bit, kanye nedatha engu-64-bit ngomzila ngamunye.
4.2.3. I-RX CRC
Ungakwazi ukunika amandla ibhulokhi ye-TX CRC usebenzisa ipharamitha ethi Vumela i-CRC kusihleli sepharamitha ye-IP. Lesi sici sisekelwa kuzo zombili izindlela eziyisisekelo nezigcwele. Ibhulokhi ye-RX CRC ihlangana namabhulokhi e-RX Control Word Removal kanye namabhulokhi e-RX MII Decoder. I-IP igomela isiginali yephutha ethi rx_crc_error uma kwenzeka iphutha le-CRC.

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I-IP isusa u-rx_crc_error kukho konke ukuqhuma okusha. Kungumphumela wokulandela umqondo womsebenzisi wokuphatha iphutha lokusebenzisa ingqondo.
4.2.4. I-RX Deskew
Ibhulokhi yedeskithophu ye-RX ithola omaka bokuqondanisa kumzila ngamunye futhi iqondise kabusha idatha ngaphambi kokuyithumela kubhulokhi yokususa i-RX CW.
Ungakhetha ukuvumela i-IP core ukuthi iqondanise idatha yomzila ngamunye ngokuzenzakalelayo lapho kwenzeka iphutha lokuqondanisa ngokusetha ipharamitha yokunika amandla Ukuqondanisa Okuzenzakalelayo kusihleli sepharamitha ye-IP. Uma ukhubaza isici sokuqondanisa okuzenzakalelayo, umongo we-IP ugomela isignali yephutha ethi rx_e ukukhombisa iphutha lokuqondanisa. Kumelwe ugomele u-rx_link_reinit ukuze uqalise inqubo yokuqondisa umugqa lapho kwenzeka iphutha lokuqondanisa umugqa.
Ideskithophu ye-RX ithola omaka bokuqondanisa ngokusekelwe emshinini wezwe. Umdwebo olandelayo ubonisa izifunda ku-RX deskew block.

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Umfanekiso 20.

Umshini Wesifunda Wokuqondanisa Kwe-RX Deskew Lane Oneshadi Lokugeleza Elivunyelwe Ukuqondisa Ngokuzenzakalelayo
Qala

I-IDLE

Setha kabusha = 1 yebo cha

Wonke ama-PC

cha

imizila isilungile?

yebo

LINDA

Zonke izimpawu zokuvumelanisa inombolo
itholiwe?
yebo
QHUBEKA

cha
yebo Isikhathi siphelile?

yebo
Ulahlekelwe ukuqondanisa?
akukho End

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Umfanekiso 21.

Umshini Wesifunda Wokuqondanisa Kwe-RX Deskew Lane Oneshadi Lokugeleza Lokuqondisa Ngokuzenzakalela
Qala

I-IDLE

Setha kabusha = 1 yebo cha

Wonke ama-PC

cha

imizila isilungile?

yebo

yebo
rx_link_reinit =1
alikho IPHUTHA

cha yebo Isikhathi siphelile?

LINDA
cha Zonke izimpawu zokuvumelanisa
itholiwe?
yebo LUNGISA

yebo
Ulahlekelwe ukuqondanisa?
cha
Qeda
1. Inqubo yokuqondanisa iqala ngesimo se-IDLE. Ibhulokhi ithuthela kusimo se-WAIT lapho yonke imizila ye-PCS isilungile futhi i-rx_link_reinit ikhishiwe.
2. Esimeni se-WAIT, ibhulokhi ihlola ukuthi zonke izimpawu ezitholiwe zigonyelwa ngaphakathi komjikelezo ofanayo. Uma lesi simo siyiqiniso, ibhulokhi ithuthela esimweni OKUQINISEKILE.
3. Uma ibhulokhi isesimweni OKUQONDILE, ikhombisa ukuthi imizila iqondile. Kulesi simo, ibhulokhi iyaqhubeka nokuqapha ukuqondanisa komzila futhi ihlole ukuthi ingabe bonke omaka bakhona yini phakathi komjikelezo ofanayo. Uma okungenani umaka oyedwa ungekho emjikelezweni ofanayo futhi ipharamitha ethi Vumela Ukuqondanisa Okuzenzakalelayo isethiwe, ibhulokhi iya ku-

I-F-Tile Serial Lite IV Intel® FPGA IP Umhlahlandlela Womsebenzisi 34

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Isimo se-IDLE sokuqalisa kabusha inqubo yokuqondanisa. Uma Ukuqondisa Ukuqondanisa Okuzenzakalelayo kungasethiwe futhi okungenani umaka oyedwa ungekho emjikelezweni ofanayo, ibhulokhi iya kusimo se-ERROR futhi ilinde ingqondo yomsebenzisi ukuthi igomele isignali ye-rx_link_reinit ukuze iqalise inqubo yokuqondanisa umzila.

Umfanekiso 22. Ukuqondanisa Kabusha Komzila Ngokuvumela Ukuqondanisa Okuzenzakalelayo Kunikwe amandla rx_core_clk

rx_link_up

rx_link_reinit

kanye_nomaka_bonke

Deskew State

I-ALGNED

I-IDLE

LINDA

I-ALGNED

AUTO_ALIGN = 1

Umfanekiso 23. Ukuhlelwa Kabusha Komzila Ngokuvumela Ukuqondanisa Okuzenzakalelayo Kukhutshaziwe rx_core_clk

rx_link_up

rx_link_reinit

kanye_nomaka_bonke

Deskew State

I-ALGNED

IPHUTHA

I-IDLE

LINDA

I-ALGNED

AUTO_ALIGN = 0
4.2.5. Ukususwa kwe-RX CW
Leli bhulokhi linquma ama-CW futhi lithumela idatha kungqondongqondo yomsebenzisi kusetshenziswa isixhumi esibonakalayo sokusakaza se-Avalon ngemva kokususwa kwama-CW.
Uma ingekho idatha evumelekile etholakalayo, ibhulokhi yokususa ye-RX CW ikhipha isignali ethi rx_avs_valid.
Kumodi OKUGCWELE, uma ibhithi yomsebenzisi isethiwe, leli bhulokhi ligomela isignali ethi rx_is_usr_cmd futhi idatha ekumjikelezo wewashi lokuqala isetshenziswa njengolwazi oluchazwe umsebenzisi noma umyalo.
Uma okuthi rx_avs_ready desserts kanye nokuthi rx_avs_valid igomela, ibhulokhi yokususa ye-RX CW ikhiqiza isimo sephutha kumqondo womsebenzisi.
Amasignali okusakaza e-Avalon ahlobene naleli bhulokhi ami kanje: · rx_avs_startofpacket · rx_avs_endofpacket · rx_avs_channel · rx_avs_empty · rx_avs_data

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· rx_avs_valid
· rx_num_valid_bytes_eob
· rx_is_usr_cmd (itholakala kuphela ngemodi egcwele)
4.3. I-F-Tile Serial Lite IV Intel FPGA IP Clock Architecture
I-F-Tile Serial Lite IV Intel FPGA IP inezinto ezifakwayo zewashi ezine ezikhiqiza amawashi kumabhulokhi ahlukene: · Iwashi lereferensi le-Transceiver (xcvr_ref_clk)–Iwashi lokufaka elisuka kuwashi langaphandle
ama-chips noma ama-oscillator akhiqiza amawashi amabhulokhi e-TX MAC, RX MAC, ne-TX kanye ne-RX yangokwezifiso ye-PCS. Bheka Kumapharamitha ukuthola ibanga lefrikhwensi elisekelwayo. · Iwashi le-TX core (tx_core_clk)–Leli washi lisuselwa ku-transceiver PLL lisetshenziselwa i-TX MAC. Leli washi liphinde libe iwashi eliphumayo elisuka ku-F-tile transceiver ukuze lixhumeke kungqondongqondo yomsebenzisi we-TX. · Iwashi le-RX core (rx_core_clk)–Leli washi lisuselwa ku-transceiver PLL lisetshenziselwa i-RX deskew FIFO kanye ne-RX MAC. Leli washi liphinde libe yiwashi eliphumayo elisuka ku-F-tile transceiver ukuze lixhumeke kungqondongqondo yomsebenzisi we-RX. · Iwashi le-transceiver reconfiguration interface (reconfig_clk)–iwashi lokufaka elivela kumasekhethi wewashi angaphandle noma ama-oscillator akhiqiza amawashi okusebenza kabusha kwe-F-tile transceiver kuzo zombili izindlela zedatha ze-TX ne-RX. Imvamisa yewashi ngu-100 kuya ku-162 MHz.
Umdwebo webhulokhi olandelayo ubonisa izizinda zewashi le-F-Tile Serial Lite IV Intel FPGA IP kanye nokuxhumana ngaphakathi kwe-IP.

I-F-Tile Serial Lite IV Intel® FPGA IP Umhlahlandlela Womsebenzisi 36

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Umfanekiso 24.

I-F-Tile Serial Lite IV Intel FPGA IP Clock Architecture

I-oscillator

I-FPGA1
I-F-Tile Serial Lite IV Intel FPGA IP Transceiver Reconfiguration Interface Clock
(reconfig_clk)

tx_core_clkout (xhuma kungqondongqondo yomsebenzisi)

tx_core_clk= clk_pll_div64[mid_ch]

I-FPGA2

I-F-Tile Serial Lite IV Intel FPGA IP

Iwashi le-Transceiver Reconfiguration Interface

(reconfig_clk)

I-oscillator

rx_core_clk= clk_pll_div64[mid_ch]

rx_core_clkout (xhuma kumqondo womsebenzisi)

clk_pll_div64[mid_ch] clk_pll_div64[n-1:0]

Idatha ye-Avalon Streaming Interface TX
I-TX MAC

isixhumanisi_se-serial[n-1:0]

Deskew

I-FIFO

I-Avalon Streaming Interface RX Data RX MAC

Idatha ye-Avalon Streaming RX
I-RX MAC

Bheka i-FIFO

rx_core_clkout (xhuma kumqondo womsebenzisi)

rx_core_clk= clk_pll_div64[mid_ch]

Ama-PC ngokwezifiso

isixhumanisi_se-serial[n-1:0]

I-TX MAC

Idatha ye-Avalon Streaming Interface TX

tx_core_clk= clk_pll_div64[mid_ch]

tx_core_clkout (xhuma kungqondongqondo yomsebenzisi)

Iwashi le-Transceiver Ref (xcvr_ref_clk)
Iwashi le-Transceiver Ref (xcvr_ref_clk)

I-oscillator*

Inganekwane

Idivayisi ye-FPGA
Isizinda sewashi eliyinhloko le-TX
Isizinda sewashi eliyinhloko le-RX
Isizinda sewashi lereferensi ye-Transceiver Idivayisi yangaphandle Amasignali edatha

4.4. Setha Kabusha futhi Uqalise Isixhumanisi
I-MAC, i-F-tile Hard IP, namabhulokhi okusetha kabusha anezimpawu ezihlukile zokusetha kabusha: · Amabhulokhi e-TX kanye ne-RX MAC asebenzisa amasiginali okusetha kabusha okuthi tx_core_rst_n kanye ne-rx_core_rst_n. · tx_pcs_fec_phy_reset_n kanye ne-rx_pcs_fec_phy_reset_n shayela kabusha amasignali
isilawuli sokusetha kabusha okuthambile ukuze usethe kabusha i-F-tile Hard IP. · Ibhulokhi yokumisa kabusha isebenzisa isignali yokusetha kabusha_yokusetha kabusha.

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Umfanekiso 25. Setha kabusha i-Architecture
Idatha ye-Avalon Streaming Interface TX
I-MAC
Idatha ye-Avalon Streaming SYNC Interface RX

I-FPGA F-tile Serial Lite IV Intel FPGA IP

tx_mii rx_mii
phy_ehip_ready phy_rx_pcs_ready

I-F-tile Hard IP

Idatha ye-TX ye-Serial RX Idatha ye-serial

tx_core_rstn rx_core_rstn tx_pcs_fec_phy_reset_n rx_pcs_fec_phy_reset_n reconfig_reset

Setha kabusha i-Logic
Ulwazi Oluhlobene · Setha Kabusha Iziqondiso ekhasini 51 · F-Tile Serial Lite IV Intel FPGA IP Design Example Umhlahlandlela Womsebenzisi
4.4.1. Ukusetha Kabusha kwe-TX Nokulandelana Kokuqala
Ukulandelana kokusetha kabusha kwe-TX kwe-F-Tile Serial Lite IV Intel FPGA IP imi kanje: 1. Assert tx_pcs_fec_phy_reset_n, tx_core_rst_n, futhi reconfig_reset
kanyekanye ukuze usethe kabusha i-IP eqinile ye-F-tile, i-MAC, namabhulokhi okulungisa kabusha. Khipha i-tx_pcs_fec_phy_reset_n bese umisa kabusha ukulungiswa ngemva kokulinda i-tx_reset_ack ukuze uqinisekise ukuthi amabhulokhi asethwe kabusha ngendlela efanele. 2. I-IP ibe isigomela amasiginali we-phy_tx_lanes_stable, tx_pll_locked, kanye ne-phy_ehip_ready ngemva kokukhishwa kabusha kwe-tx_pcs_fec_phy_reset_n, ukukhombisa ukuthi i-TX PHY isilungele ukudluliselwa. 3. Isiginali ye-tx_core_rst_n amadesethi ngemva kokuba isignali ye-phy_ehip_ready iphezulu. 4. I-IP iqala ukudlulisa izinhlamvu ze-IDLE kusixhumi esibonakalayo se-MII uma i-MAC isiphelelwe ukusetha kabusha. Asikho isidingo sokuqondanisa komzila we-TX nokutshekela ngoba yonke imizila isebenzisa iwashi elifanayo. 5. Ngenkathi idlulisela izinhlamvu ze-IDLE, i-MAC igomela isignali ethi tx_link_up. 6. I-MAC ibe isiqala ukudlulisa u-ALIGN okubhangqwe ne-START/END noma END/START CW ngesikhathi esinqunyiwe ukuze kuqalwe inqubo yokuqondanisa umzila yomamukeli oxhunyiwe.

I-F-Tile Serial Lite IV Intel® FPGA IP Umhlahlandlela Womsebenzisi 38

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Umfanekiso 26.

Ukusetha kabusha kwe-TX kanye Nokuqalisa Isikhathi Umdwebo
reconfig_sl_clk

reconfig_clk

tx_core_rst_n

tx_pcs_fec_phy_reset_n 1

reconfig_reset

reconfig_sl_reset

tx_reset_ack

tx_pll _ikhiyiwe

phy_tx_lanes_stable

phy_ehip_ready

tx_li nk_up

7
5 6 8

4.4.2. Ukusetha Kabusha kwe-RX Nokulandelana Kokuqala
Ukulandelana kokusetha kabusha kwe-RX kwe-F-Tile Serial Lite IV Intel FPGA IP imi kanje:
1. Funa okuthi rx_pcs_fec_phy_reset_n, rx_core_rst_n, futhi reconfig_reset kanyekanye ukuze usethe kabusha i-F-tile eqinile IP, i-MAC, namabhulokhi okulungisa kabusha. Khipha i-rx_pcs_fec_phy_reset_n bese usetha kabusha ukulungiswa ngemva kokulinda i-rx_reset_ack ukuze uqinisekise ukuthi amabhulokhi asethwe kabusha ngendlela efanele.
2. I-IP ibe isigomela isignali ethi phy_rx_pcs_ready ngemva kokukhululwa kokusetha kabusha kwe-PCS ngokwezifiso, ukukhombisa ukuthi i-RX PHY isilungele ukudluliselwa.
3. Isiginali ye-rx_core_rst_n yamadesethi ngemva kokuba isignali ye-phy_rx_pcs_ready iye phezulu.
4. I-IP iqala inqubo yokuqondanisa umzila ngemva kokukhululwa kokusetha kabusha kwe-RX MAC futhi lapho ithola UKULINGANA okubhangqwe ne-START/END noma END/START CW.
5. I-RX deskew block igomela isignali ye-rx_link_up uma ukuqondanisa kwayo yonke imizila sekuqediwe.
6. I-IP ibe isigomela isignali ethi rx_link_up kungqondongqondo yomsebenzisi ukuze ibonise ukuthi isixhumanisi se-RX sesilungele ukuqalisa ukwamukela idatha.

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Umfanekiso 27. Ukusetha kabusha kwe-RX kanye nokuQalisa Umdwebo Wesikhathi
reconfig_sl_clk

reconfig_clk

rx_core_rst_n

rx_pcs_fec_phy_reset_n 1

reconfig_reset

reconfig_sl_reset

rx_reset_ack

rx_cdr_lock

rx_block_lock

rx_pcs_ready

rx_link_up

3 3 3 2

4 5 5

6 7

4.5. Isilinganiso Sokuxhumanisa kanye nokubalwa Kokusebenza Komkhawulokudonsa

I-F-Tile Serial Lite IV Intel FPGA IP isibalo somkhawulokudonsa sinje ngezansi:

Ukusebenza kahle komkhawulokudonsa = raw_rate * 64/66 * (burst_size – burst_size_ovhd)/burst_size * [align_marker_period / (align_marker_period + align_marker_width)] * [(srl4_align_period – 2) / srl4_align_period

Ithebula 17. I-Bandwidth Efficiency Variables Incazelo

Iyaguquguquka

Incazelo

raw_rate burst_size

Leli izinga lebhithi elitholwa isixhumi esibonakalayo se-serial. raw_rate = Ububanzi be-SERDES * imvamisa yewashi le-transceiver Example: raw_rate = 64 * 402.812500 Gbps = 25.78 Gbps
Inani losayizi wokuqhuma. Ukuze ubale ukusebenza kahle komkhawulokudonsa omaphakathi, sebenzisa inani elivamile losayizi wokuqhuma. Ukuze uthole isilinganiso esiphezulu, sebenzisa inani eliphezulu losayizi wokuqhuma.

burst_size_ovhd

Inani elingaphezulu kosayizi wokuqhuma.
Kumodi egcwele, inani le-burst_size_ovhd libhekisele kuma-CW abhanqiwe angu-START kanye END.
Kumodi Eyisisekelo, ayikho i-burst_size_ovhd ngoba awekho ama-CW abhanqiwe angu-START kanye END.

qondanisa_umaka_inkathi

Inani lenkathi lapho kufakwa khona umaka wokuqondanisa. Inani liwumjikelezo wewashi elingu-81920 lokuhlanganiswa kanye no-1280 wokulingisa okusheshayo. Leli nani litholwa ku-PCS hard logic.

align_marker_width srl4_align_period

Inani lemijikelezo yewashi lapho isignali yomaka wokuqondanisa evumelekile iphakanyiswe phezulu.
Inani lemijikelezo yewashi phakathi komaka ababili bokuqondanisa. Ungasetha leli nani usebenzisa ipharamitha Yenkathi Yokuqondanisa Kusihleli Sepharamitha ye-IP.

I-F-Tile Serial Lite IV Intel® FPGA IP Umhlahlandlela Womsebenzisi 40

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Izibalo zesilinganiso sesixhumanisi zinje ngezansi: Izinga elisebenzayo = ukusebenza kahle komkhawulokudonsa * raw_rate Ungathola ubuningi bewashi lomsebenzisi ngesibalo esilandelayo. Isibalo esiphezulu sokubala iwashi lomsebenzisi sithatha ukusakazwa kwedatha okuqhubekayo futhi awukho umjikelezo we-IDLE owenzekayo kungqondongqondo yomsebenzisi. Lesi silinganiso sibalulekile uma uklama i-FIFO enengqondo yomsebenzisi ukuze ugweme ukuchichima kwe-FIFO. Ubuningi bemvamisa yewashi lomsebenzisi = isilinganiso esisebenzayo / 64

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5. Amapharamitha

Ithebula 18. F-Tile Serial Lite IV Intel FPGA IP Ipharamitha Incazelo

Ipharamitha

Inani

Okuzenzakalelayo

Incazelo

Izinketho Zokuklama Okujwayelekile

Uhlobo lokushintshwa kwe-PMA

· PAM4 · NRZ

I-PAM4

Khetha imodi yokushintshashintsha ye-PCS.

Uhlobo lwe-PMA

· FHT · FGT

I-FGT

Ikhetha uhlobo lwe-transceiver.

Idatha ye-PMA

· Ngemodi ye-PAM4:
- Uhlobo lwe-transceiver ye-FGT: 20 Gbps 58 Gbps
- Uhlobo lwe-transceiver ye-FHT: 56.1 Gbps, 58 Gbps, 116 Gbps
· Ngemodi ye-NRZ:
- Uhlobo lwe-transceiver ye-FGT: 10 Gbps 28.05 Gbps
- Uhlobo lwe-transceiver ye-FHT: 28.05 Gbps, 58 Gbps

56.1 (FGT/FHT PAM4)
28.05 Gbps (FGT/FHT NRZ)

Icacisa izinga ledatha elisebenzayo ekuphumeni kwe-transceiver ehlanganisa ukudluliswa nokunye okungaphezulu. Inani libalwa nge-IP ngokusondeza kufikela endaweni yedesimali engu-1 kuyunithi ye-Gbps.

Imodi ye-PMA

· I-Duplex · Tx · Rx

I-Duplex

Ohlotsheni lwe-transceiver ye-FHT, isiqondiso esisekelwayo siyi-duplex kuphela. Ohlotsheni lwe-FGT transceiver, isiqondiso esisekelwayo yi-Duplex, Tx, ne-Rx.

Inombolo ye-PMA

· Ngemodi ye-PAM4:

imizila

— 1 kuya ku-12

· Ngemodi ye-NRZ:

— 1 kuya ku-16

Khetha inombolo yemizila. Ngomklamo we-simplex, inombolo esekelwe yemizila ngu-1.

Imvamisa yewashi lesithenjwa se-PLL

· Ngohlobo lwe-transceiver ye-FHT: 156.25 MHz
· Ohlotsheni lwe-FGT transceiver: 27.5 MHz 379.84375 MHz, kuye ngezinga ledatha ye-transceiver ekhethiwe.

· Ngohlobo lwe-transceiver ye-FHT: 156.25 MHz
· Ngohlobo lwe-FGT transceiver: 165 MHz

Icacisa imvamisa yewashi lesithenjwa se-transceiver.

Isistimu ye-PLL

—

iwashi eliyinkomba

imvamisa

170 MHz

Itholakala kuphela kuhlobo lwe-transceiver ye-FHT. Icacisa iwashi lesithenjwa leSistimu ye-PLL futhi izosetshenziswa njengokufakwayo Kwereferensi ye-F-Tile kanye Namawashi Esistimu ye-PLL Intel FPGA IP ukuze kukhiqizwe iwashi leSistimu ye-PLL.

Imvamisa yesistimu ye-PLL
Isikhathi Sokuqondanisa

— 128 65536

Nika amandla i-RS-FEC

Nika amandla

876.5625 MHz 128 Nika amandla

Icacisa imvamisa yewashi leSistimu ye-PLL.
Icacisa isikhathi somaka wokuqondanisa. Inani kufanele libe ngu-x2. Vula ukuze unike amandla isici se-RS-FEC.
waqhubeka...

I-ISO 9001:2015 Ibhalisiwe

5. Amapharamitha 683074 | 2022.04.28

Ipharamitha

Inani

Okuzenzakalelayo

Incazelo

Khubaza

Ngemodi yokushintshashintsha ye-PAM4 PCS, i-RS-FEC ihlala ivuliwe.

Isixhumi esibonakalayo somsebenzisi

Imodi yokusakaza

· OKUGCWELE · ISISEKO

Okugcwele

Khetha ukusakaza kwedatha ye-IP.

Okugcwele: Le modi ithumela ukuqala kwephakethe nomjikelezo wokuphela kwephakethe ngaphakathi kohlaka.

Okuyisisekelo: Lena imodi yokusakaza emsulwa lapho idatha ithunyelwa khona ngaphandle kokuqala kwephakethe, okungenalutho, nokuphela kwephakethe ukuze kwandiswe umkhawulokudonsa.

Nika amandla i-CRC

Nika amandla Khubaza

Khubaza

Vula ukuze unike amandla ukutholwa kwephutha le-CRC nokulungiswa.

Nika amandla ukuqondanisa okuzenzakalelayo

Nika amandla Khubaza

Khubaza

Vula ukuze unike amandla isici sokuqondanisa umzila ozenzakalelayo.

Nika amandla isiphetho sokususa iphutha

Nika amandla Khubaza

Khubaza

UMA VULIWE, i-F-Tile Serial Lite IV Intel FPGA IP ihlanganisa nendawo yokugcina yokususa iphutha exhumeka ngaphakathi kusixhumi esibonakalayo esinemephu yememori ye-Avalon. I-IP ingenza izivivinyo ezithile futhi ilungise imisebenzi ngo-JTAG usebenzisa Ikhonsoli Yesistimu. Inani elizenzakalelayo Livaliwe.

Ukuhlanganisa i-Simplex (Lesi silungiselelo sepharamitha sitholakala kuphela uma ukhetha i-FGT dual simplex design.)

I-RSFEC inikwe amandla kwenye i-Serial Lite IV Simplex IP ebekwe eziteshini ezifanayo ze-FGT

Nika amandla Khubaza

Khubaza

Vula le nketho uma udinga inhlanganisela yokucushwa nge-RS-FEC enikwe amandla futhi ikhutshaziwe ku-F-Tile Serial Lite IV Intel FPGA IP kumklamo ombaxambili we-simplex wemodi ye-transceiver ye-NRZ, lapho kokubili i-TX ne-RX zibekwe ku-FGT efanayo. iziteshi.

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6. Izimpawu ze-F-Tile Serial Lite IV Intel FPGA IP Interface Signals

6.1. Iwashi Izimpawu

Ithebula 19. Izimpawu Zewashi

Igama

Ububanzi Direction

Incazelo

tx_core_clkout

Iwashi eliyinhloko le-Output TX yesixhumi esibonakalayo se-TX ngokwezifiso se-PCS, i-TX MAC namalogikhi omsebenzisi

Idatha ye-TX.

Leli washi likhiqizwa ebhulokhini le-PCS langokwezifiso.

rx_core_clkout

Iwashi eliyinhloko le-RX eliphumayo le-RX custom PCS interface, i-RX deskew FIFO, i-RX MAC

kanye nama-logics wabasebenzisi ku-datapath ye-RX.

Leli washi likhiqizwa ebhulokhini le-PCS langokwezifiso.

xcvr_ref_clk
reconfig_clk reconfig_sl_clk

Iwashi lereferensi ye-Transceiver.

Uma uhlobo lwe-transceiver lusethelwe ku-FGT, xhuma leli washi kusignali yokuphumayo (out_refclk_fgt_0) ye-F-Tile Reference kanye ne-System PLL Clocks Intel FPGA IP. Uma uhlobo lwe-transceiver lusethelwe ku-FHT, xhuma

leli washi kusignali yokuphumayo (out_fht_cmmpll_clk_0) ye-F-Tile Reference kanye ne-System PLL Clocks Intel FPGA IP.

Bheka Kumapharamitha ukuthola ibanga lefrikhwensi elisekelwayo.

Iwashi lokokufaka lokusetha kabusha isixhumi esibonakalayo se-transceiver.

Imvamisa yewashi ngu-100 kuya ku-162 MHz.

Xhuma le siginali yewashi okokufaka kumasekhethi wewashi angaphandle noma ama-oscillator.

Iwashi lokokufaka lokusetha kabusha isixhumi esibonakalayo se-transceiver.

Imvamisa yewashi ngu-100 kuya ku-162 MHz.

Xhuma le siginali yewashi okokufaka kumasekhethi wewashi angaphandle noma ama-oscillator.

out_systempll_clk_ 1

Okokufaka

Iwashi lesistimu ye-PLL.
Xhuma leli washi kusignali yokuphumayo (out_systempll_clk_0) ye-F-Tile Reference kanye ne-System PLL Clocks Intel FPGA IP.

Amapharamitha Olwazi Oluhlobene ekhasini 42

6.2. Setha kabusha Amasignali

Ithebula 20. Setha Kabusha Izimpawu

Igama

Ububanzi Direction

tx_core_rst_n

Okokufaka

Isizinda Sewashi Asynchronous

rx_core_rst_n

Okokufaka

Asynchronous

tx_pcs_fec_phy_reset_n 1

Okokufaka

Asynchronous

Incazelo

Isiginali yokusetha kabusha esebenzayo ephansi. Isetha kabusha i-F-Tile Serial Lite IV TX MAC.

Isiginali yokusetha kabusha esebenzayo ephansi. Isetha kabusha i-F-Tile Serial Lite IV RX MAC.

Isiginali yokusetha kabusha esebenzayo ephansi.

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Igama

Ububanzi Bewashi Lesizinda

Incazelo

Isetha kabusha i-F-Tile Serial Lite IV TX yangokwezifiso PCS.

rx_pcs_fec_phy_reset_n 1

Okokufaka

Asynchronous

Isiginali yokusetha kabusha esebenzayo ephansi. Isetha kabusha i-F-Tile Serial Lite IV RX yangokwezifiso PCS.

reconfig_reset

Okokufaka

reconfig_clk Isignali yokusetha kabusha esebenzayo ephezulu.

Isetha kabusha ibhulokhi yokumisa kabusha isixhumi esibonakalayo esinemephu yenkumbulo ye-Avalon.

reconfig_sl_reset

Okokufaka reconfig_sl_clk Isiginali yokusetha kabusha esebenzayo ephezulu.

Isetha kabusha ibhulokhi yokumisa kabusha isixhumi esibonakalayo esinemephu yenkumbulo ye-Avalon.

6.3. Izimpawu ze-MAC

Ithebula 21.

Izimpawu ze-TX MAC
Kuleli thebula, u-N umele inombolo yemizila esethwe kusihleli sepharamitha ye-IP.

Igama

Ububanzi

Isizinda Sewashi Lesiqondiso

Incazelo

tx_avs_ready

Okukhiphayo tx_core_clkout Isignali yokusakaza ye-Avalon.

Uma kugonyelwa, kukhombisa ukuthi i-TX MAC isilungele ukwamukela idatha.

tx_avs_idatha

· (64*N)*2 (PAM4 mode)
· 64*N (imodi ye-NRZ)

Okokufaka

tx_core_clkout Isignali yokusakaza ye-Avalon. Idatha ye-TX.

tx_avs_channel

Okokufaka kwe-tx_core_clkout isignali yokusakaza ye-Avalon.

Inombolo yesiteshi yedatha edluliswayo emjikelezweni wamanje.

Lesi siginali ayitholakali kumodi Eyisisekelo.

tx_avs_valid

Okokufaka kwe-tx_core_clkout isignali yokusakaza ye-Avalon.

Uma kugonyelwa, kukhombisa ukuthi isignali yedatha ye-TX ivumelekile.

tx_avs_startofpacket

Okokufaka kwe-tx_core_clkout isignali yokusakaza ye-Avalon.

Uma kugonyelwa, kukhombisa ukuqala kwephakethe ledatha le-TX.

Zigomela ngomjikelezo wewashi owodwa kuphela wephakethe ngalinye.

Lesi siginali ayitholakali kumodi Eyisisekelo.

tx_avs_endofpacket

Okokufaka kwe-tx_core_clkout isignali yokusakaza ye-Avalon.

Uma kugonyelwa, kukhombisa ukuphela kwephakethe ledatha le-TX.

Zigomela ngomjikelezo wewashi owodwa kuphela wephakethe ngalinye.

Lesi siginali ayitholakali kumodi Eyisisekelo.

tx_avs_akunalutho

Okokufaka kwe-tx_core_clkout isignali yokusakaza ye-Avalon.

Ibonisa inombolo yamagama angavumelekile ekuqhumeni kokugcina kwedatha ye-TX.

Lesi siginali ayitholakali kumodi Eyisisekelo.

tx_num_valid_bytes_eob

Okokufaka

tx_core_clkout

Ibonisa inani lamabhayithi avumelekile egameni lokugcina lokuqhuma kokugcina. Lesi siginali ayitholakali kumodi Eyisisekelo.
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Igama elithi tx_is_usr_cmd
tx_link_up tx_link_reinit
crc_error_inject tx_error

Ububanzi 1
1 1
N 5

Isizinda Sewashi Lesiqondiso

Incazelo

Okokufaka

tx_core_clkout

Uma kugonyelwa, lesi siginali siqala umjikelezo wolwazi oluchazwe umsebenzisi.
Gomela lesi siginali emjikelezweni wewashi ofanayo njengokugomela kwe-tx_startofpacket.
Lesi siginali ayitholakali kumodi Eyisisekelo.

Okukhiphayo tx_core_clkout Uma kugonyelwa, kukhombisa ukuthi isixhumanisi sedatha ye-TX sesilungele ukudluliswa kwedatha.

Okukhiphayo

tx_core_clkout

Uma kugonyelwa, lesi siginali siqala ukuqondisa kabusha kwemizila.
Gomela lesi siginali ngomjikelezo wewashi elilodwa ukuze uqalise i-MAC ukuthumela i-ALIGN CW.

Okokufaka

tx_core_clkout Uma kugonyelwa, i-MAC ifaka iphutha le-CRC32 emigwaqweni ekhethiwe.

Okukhiphayo tx_core_clkout Ayisetshenziswanga.

Umdwebo wesikhathi olandelayo ubonisa i-exampI-le ye-TX yokudluliselwa kwedatha yamagama angu-10 ukusuka kungqondongqondo yomsebenzisi emigwaqweni engu-10 ye-serial ye-TX.

Umfanekiso 28.

Umdwebo Wesikhathi Sokudluliswa Kwedatha ye-TX
tx_core_clkout

tx_avs_valid

tx_avs_ready

tx_avs_startofpackets

tx_avs_endofpackets

tx_avs_idatha

0,1..,19 10,11…19 …… N-10..

0,1,2, 9, XNUMX,…, XNUMX

… N-10..

Umzila 0

……………

STRT 0 10

N-10 END STT 0

Umzila 1

……………

STRT 1 11

N-9 END STT 1

N-10 PHELA I-IDLE IDLE N-9 PHELA I-IDLE IDLE

Umzila 9

……………

STRT 9 19

N-1 END STT 9

N-1 QEDA I-IDLE IDLE

Ithebula 22.

Izimpawu ze-RX MAC
Kuleli thebula, u-N umele inombolo yemizila esethwe kusihleli sepharamitha ye-IP.

Igama

Ububanzi

Isizinda Sewashi Lesiqondiso

Incazelo

rx_avs_ready

Okokufaka kwe-rx_core_clkout isignali yokusakaza ye-Avalon.

Uma kugonyelwa, kukhombisa ukuthi ingqondo yomsebenzisi isilungele ukwamukela idatha.

rx_avs_idatha

(64*N)*2 (PAM4 mode)
64*N (Imodi ye-NRZ)

Okukhiphayo

rx_core_clkout Isignali yokusakaza ye-Avalon. Idatha ye-RX.

rx_avs_channel

Okukhiphayo rx_core_clkout Isignali yokusakaza ye-Avalon.

Inombolo yesiteshi yedatha

etholwe ngomjikelezo wamanje.

Lesi siginali ayitholakali kumodi Eyisisekelo.

rx_avs_valid

Okukhiphayo rx_core_clkout Isignali yokusakaza ye-Avalon.

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Igama

Ububanzi

Isizinda Sewashi Lesiqondiso

Incazelo

Uma kugonyelwa, kukhombisa ukuthi isignali yedatha ye-RX ivumelekile.

rx_avs_startofpacket

Okukhiphayo rx_core_clkout Isignali yokusakaza ye-Avalon.

Uma kugonyelwa, kukhombisa ukuqala kwephakethe ledatha le-RX.

Zigomela ngomjikelezo wewashi owodwa kuphela wephakethe ngalinye.

Lesi siginali ayitholakali kumodi Eyisisekelo.

rx_avs_endofpacket

Okukhiphayo rx_core_clkout Isignali yokusakaza ye-Avalon.

Uma kugonyelwa, kukhombisa ukuphela kwephakethe ledatha le-RX.

Zigomela ngomjikelezo wewashi owodwa kuphela wephakethe ngalinye.

Lesi siginali ayitholakali kumodi Eyisisekelo.

rx_avs_akunalutho

Okukhiphayo rx_core_clkout Isignali yokusakaza ye-Avalon.

Ibonisa inombolo yamagama angavumelekile ekuqhumeni kokugcina kwedatha ye-RX.

Lesi siginali ayitholakali kumodi Eyisisekelo.

rx_num_valid_bytes_eob

Okukhiphayo

rx_core_clkout Ibonisa inani lamabhayithi avumelekile egameni lokugcina lokuqhuma kokugcina.
Lesi siginali ayitholakali kumodi Eyisisekelo.

rx_is_usr_cmd

Okukhiphayo rx_core_clkout Uma kugonyelwa, lesi siginali iqalisa umsebenzisi-

umjikelezo wolwazi ochaziwe.

Gomela lesi siginali emjikelezweni wewashi ofanayo njengokugomela kwe-tx_startofpacket.

Lesi siginali ayitholakali kumodi Eyisisekelo.

rx_link_up

Okukhiphayo rx_core_clkout Uma kugonyelwa, kukhombisa isixhumanisi sedatha ye-RX

ilungele ukwamukelwa kwedatha.

rx_link_reinit

Okokufaka rx_core_clkout Uma kugonyelwa, lesi siginali ivula imizila

ukulungisa kabusha.

Uma ukhubaza Vumela Ukuqondanisa Okuzenzakalelayo, gomela lesi siginali ngomjikelezo wewashi elilodwa ukuze uqalise i-MAC ukuze iphinde iqondanise imizila. Uma u-Vumela Ukuqondanisa Okuzenzakalelayo kusethiwe, i-MAC iphinda iqondise imizila ngokuzenzakalelayo.

Ungagodli lesi siginali uma u-Vumela Ukuqondanisa Okuzenzakalelayo kusethiwe.

rx_iphutha

(N*2*2)+3 (PAM4 mode)
(N*2)*3 (Imodi ye-NRZ)

Okukhiphayo

rx_core_clkout

Uma kugonyelwa, kukhombisa izimo zephutha ezenzeka ku-datapath ye-RX.
· [(N*2+2):N+3] = Ibonisa iphutha le-PCS kumzila othile.
· [N+2] = Ibonisa iphutha lokuqondanisa. Phinda uqalise ukuqondanisa komugqa uma le bhithi igonyelwa.
· [N+1]= Ibonisa idatha idluliselwa kumqondo womsebenzisi lapho ingqondo yomsebenzisi ingakalungi.
· [N] = Ikhombisa ukulahleka kokuqondanisa.
· [(N-1):0] = Ibonisa idatha iqukethe iphutha le-CRC.

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6.4. Ama-Transceiver Reconfiguration Signals

Ithebula 23.

Izimpawu Zokumisa Kabusha ze-PCS
Kuleli thebula, u-N umele inombolo yemizila esethwe kusihleli sepharamitha ye-IP.

Igama

Ububanzi

Isizinda Sewashi Lesiqondiso

Incazelo

reconfig_sl_read

Faka umyalo wokufunda wokulungisa kabusha_sl_ PCS

clk

izimpawu.

reconfig_sl_write

Faka ukubhala kabusha kwe-reconfig_sl_ PCS

clk

amasignali umyalo.

reconfig_sl_address

14 bits + clogb2N

Okokufaka

reconfig_sl_ clk

Icacisa ikheli lesixhumi esibonakalayo esinemephu yenkumbulo ye-PCS emzileni okhethiwe.
Umzila ngamunye unamabhithi angu-14 kanti izingcezu ezingaphezulu zibhekisela kumzila we-offset.
Example, ngomklamo we-4-lane NRZ/PAM4, ene-reconfig_sl_address[13:0] ebhekisela enanini lekheli:
· reconfig_sl_address[15:1 4] isethwe ku-00 = ikheli lomzila 0.
· reconfig_sl_address[15:1 4] isethwe ku-01 = ikheli lomzila 1.
· reconfig_sl_address[15:1 4] isethwe ku-10 = ikheli lomzila 2.
· reconfig_sl_address[15:1 4] isethwe ku-11 = ikheli lomzila 3.

reconfig_sl_readdata

I-Output reconfig_sl_ Icacisa idatha yokuhlela kabusha ye-PCS

clk

ukufundwa umjikelezo olungile ngo

umzila okhethiwe.

reconfig_sl_waitrequest

I-Output reconfig_sl_ Imele ukumiswa kabusha kwe-PCS

clk

I-interface ye-Avalon memory-mapped

isignali yokuma emzileni okhethiwe.

reconfig_sl_writedata

Okokufaka reconfig_sl_ Icacisa idatha yokumisa kabusha i-PCS

clk

ukubhalwa emjikelezweni wokubhala a

umzila okhethiwe.

reconfig_sl_readdata_vali

Okukhiphayo

reconfig_sl_ Icacisa ukumiswa kabusha kwe-PCS

clk

idatha etholiwe ivumelekile kokukhethiwe

umzila.

Ithebula 24.

Izimpawu Zokumisa Kabusha ze-F-Tile IP
Kuleli thebula, u-N umele inombolo yemizila esethwe kusihleli sepharamitha ye-IP.

Igama

Ububanzi

Isizinda Sewashi Lesiqondiso

Incazelo

reconfig_read

Okokufaka kwe-reconfig_clk PMA kabusha kufundiwe

amasignali umyalo.

reconfig_write

Faka ukubhala kabusha kwe-reconfig_clk PMA

amasignali umyalo.

reconfig_address

18 bits + clog2bN

Okokufaka

reconfig_clk

Icacisa ikheli le-PMA Avalon elenziwe ngenkumbulo emzileni okhethiwe.
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Igama
reconfig_readdata reconfig_waitrequest reconfig_writedata reconfig_readdatavalid

Ububanzi
32 1 32 1

Isizinda Sewashi Lesiqondiso

Incazelo

Kuzo zombili izindlela ze-PAM4 zesikhangiso se-NRZ, umzila ngamunye unamabhithi angu-18 kanti izingcezu eziphezulu ezisele zibhekisela kumzila we-offset.
Example, ngomklamo wemizila emi-4:
· reconfig_address[19:18] isethwe ku-00 = ikheli lomzila 0.
· reconfig_address[19:18] isethwe ku-01 = ikheli lomzila 1.
· reconfig_address[19:18] isethwe ku-10 = ikheli lomzila 2.
· reconfig_address[19:18] isethwe ku-11 = ikheli lomzila 3.

Okukhiphayo

reconfig_clk Icacisa idatha ye-PMA okufanele ifundwe ngomjikelezo olungile emzileni okhethiwe.

Okukhiphayo

i-reconfig_clk Imelela isibonisi se-PMA ye-Avalon esimeme ngenkumbulo emile endleleni ekhethiwe.

Okokufaka

reconfig_clk Icacisa idatha ye-PMA ezobhalwa emjikelezweni wokubhala emzileni okhethiwe.

Okukhiphayo

reconfig_clk Icacisa ukucushwa kabusha kwe-PMA idatha etholiwe ivumelekile emzileni okhethiwe.

6.5. Izimpawu ze-PMA

Ithebula 25.

Izimpawu ze-PMA
Kuleli thebula, u-N umele inombolo yemizila esethwe kusihleli sepharamitha ye-IP.

Igama

Ububanzi

Isizinda Sewashi Lesiqondiso

Incazelo

phy_tx_lanes_stable

N*2 (PAM4 mode)
N (Imodi ye-NRZ)

Okukhiphayo

Asynchronous Uma kugonyelwa, kukhombisa ukuthi i-TX datapath isilungele ukuthumela idatha.

tx_pll_ikhiyiwe

N*2 (PAM4 mode)
N (Imodi ye-NRZ)

Okukhiphayo

Asynchronous Uma kugonyelwa, kukhombisa ukuthi i-TX PLL izuze isimo sokukhiya.

phy_ehip_ready

N*2 (PAM4 mode)
N (Imodi ye-NRZ)

Okukhiphayo

Asynchronous

Uma kugonyelwa, kukhombisa ukuthi i-PCS yangokwezifiso isiqedile ukuqalisa kwangaphakathi futhi isilungele ukudluliswa.
Le siginali igomela ngemuva kokuthi tx_pcs_fec_phy_reset_n kanye ne-tx_pcs_fec_phy_reset_nare kukhishwe.

tx_serial_data

Okukhiphayo TX iwashi lomkhiqizo TX izikhonkwane serial.

rx_serial_data

Okokufaka kwe-RX serial clock RX izikhonkwane zochungechunge.

phy_rx_block_lock

N*2 (PAM4 mode)
N (Imodi ye-NRZ)

Okukhiphayo

Asynchronous Uma kugonyelwa, kukhombisa ukuthi ukuqondanisa kwebhulokhi engu-66b sekuqediwe imizila.

rx_cdr_lock

N*2 (PAM4 mode)

Okukhiphayo

Asynchronous

Uma kugonyelwa, kukhombisa ukuthi amawashi atholiwe akhiyiwe kudatha.
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Yisho i-phy_rx_pcs_ready phy_rx_hi_ber

Ububanzi

Isizinda Sewashi Lesiqondiso

Incazelo

N (Imodi ye-NRZ)

N*2 (PAM4 mode)
N (Imodi ye-NRZ)

Okukhiphayo

Asynchronous

Uma kugonyelwa, kukhombisa ukuthi imizila ye-RX yesiteshi esihambelanayo se-Ethernet iqondaniswe ngokugcwele futhi ilungele ukuthola idatha.

N*2 (PAM4 mode)
N (Imodi ye-NRZ)

Okukhiphayo

Asynchronous

Uma kugonyelwa, kukhombisa ukuthi i-RX PCS yesiteshi esihambelanayo se-Ethernet isesimweni se-HI BER.

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7. Ukuklama nge-F-Tile Serial Lite IV Intel FPGA IP

7.1. Setha kabusha Imihlahlandlela
Landela le mihlahlandlela yokusetha kabusha ukuze usebenzise ukusetha kabusha izinga lesistimu yakho.
Hlanganisa amasiginali we-tx_pcs_fec_phy_reset_n kanye ne-rx_pcs_fec_phy_reset_n ndawonye ezingeni lesistimu ukuze usethe kabusha i-TX ne-RX PCS kanyekanye.
· Assert tx_pcs_fec_phy_reset_n, rx_pcs_fec_phy_reset_n, tx_core_rst_n, rx_core_rst_n, futhi reconfig_reset amasignali ngesikhathi esifanayo. Bheka kokuthi Setha Kabusha kanye Nokuqaliswa Kokuxhumanisa ukuze uthole ulwazi olwengeziwe mayelana nokusetha kabusha i-IP nokulandelana kokuqalisa.
· Bamba okuthi tx_pcs_fec_phy_reset_n, kanye ne-rx_pcs_fec_phy_reset_n amasignali aphansi, futhi reconfig_reset isignali phezulu bese ulinda tx_reset_ack kanye rx_reset_ack ukusetha kabusha F-tile eqinile IP kanye nokuvinjwa kabusha.
· Ukuze ufinyelele ukuxhumana okusheshayo phakathi kwamadivayisi e-FPGA, setha kabusha ama-IP axhunyiwe e-F-Tile Serial Lite IV Intel FPGA ngesikhathi esifanayo. Bheka ku-F-Tile Serial Lite IV Intel FPGA IP Design Example Umhlahlandlela Womsebenzisi ukuze uthole ulwazi mayelana nokuqapha isixhumanisi se-IP TX ne-RX usebenzisa ikhithi yamathuluzi.
Ulwazi Oluhlobene
· Setha kabusha futhi Uqalise Ukuxhumanisa ekhasini 37
· F-Tile Serial Lite IV Intel FPGA IP Design Example Umhlahlandlela Womsebenzisi

7.2. Izinkombandlela Zokuphatha Iphutha

Ithebula elilandelayo libala imihlahlandlela yokuphatha amaphutha ezimo zephutha okungenzeka zenzeke ngomklamo we-F-Tile Serial Lite IV Intel FPGA IP.

Ithebula 26. Isimo Sephutha Nemihlahlandlela Yokusingatha

Isimo Sephutha
Umzila owodwa noma eminingi ayikwazi ukusungula ukuxhumana ngemva kwesikhathi esibekiwe.

Iziqondiso
Sebenzisa isistimu yokuvala isikhathi ukuze usethe kabusha isixhumanisi ezingeni lesicelo.

Umzila ulahlekelwa ukuxhumana ngemva kokusungulwa kokuxhumana.
Umzila ulahlekelwa ukuxhumana phakathi nenqubo yedeski.

Lokhu kungenzeka ngemva noma phakathi nezigaba zokudlulisa idatha. Sebenzisa ukutholwa kokulahleka kwesixhumanisi ezingeni lohlelo lokusebenza bese usetha kabusha isixhumanisi.
Sebenzisa inqubo yokuvuselela isixhumanisi kumzila onephutha. Kufanele uqinisekise ukuthi umzila webhodi aweqi i-320 UI.

Ukuhlelwa komzila wokulahleka ngemva kokuba yonke imizila isiqondile.

Lokhu kungenzeka ngemva noma phakathi nezigaba zokudlulisa idatha. Sebenzisa ukutholwa kokulahleka kokuqondisa komzila ezingeni lesicelo ukuze uqale kabusha inqubo yokuqondisa umugqa.

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Izinguqulo ze-IP ziyefana nezinguqulo zesofthiwe ye-Intel Quartus Prime Design Suite kufika ku-v19.1. Kusukela ku-Intel Quartus Prime Design Suite software version 19.2 noma kamuva, ama-IP cores anohlelo olusha lwenguqulo ye-IP.

Uma inguqulo ye-IP eyinhloko ingekho ohlwini, umhlahlandlela womsebenzisi wenguqulo yangaphambilini ye-IP iyasebenza.

Inguqulo ye-Intel Quartus Prime
21.3

IP Core Inguqulo 3.0.0

Umhlahlandlela Womsebenzisi F-Tile Serial Lite IV Intel® FPGA IP Umhlahlandlela Womsebenzisi

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9. Umlando Wokubuyekezwa Kombhalo we-F-Tile Serial Lite IV Intel FPGA IP User Guide

Inguqulo Yombhalo 2022.04.28
2021.11.16 2021.10.22 2021.08.18

Inguqulo ye-Intel Quartus Prime
22.1
21.3 21.3 21.2

IP Inguqulo 5.0.0
3.0.0 3.0.0 2.0.0

Izinguquko
· Ithebula Elibuyekeziwe: I-F-Tile Serial Lite IV Izici ze-Intel FPGA IP — Incazelo Yokudluliswa Kwedatha Ebuyekeziwe enokusekelwa okwengeziwe kwesilinganiso se-transceiver se-FHT: 58G NRZ, 58G PAM4, kanye ne-116G PAM4
· Ithebula Elibuyekeziwe: I-F-Tile Serial Lite IV Intel FPGA IP Ipharamitha Incazelo — Kwengezwe ipharamitha entsha · Imvamisa yewashi lereferensi yesistimu ye-PLL · Nika amandla indawo yokugcina yokulungisa iphutha — Kubuyekezwe Amanani wesilinganiso sedatha ye-PMA — Kubuyekezwe ukuqanjwa kwepharamitha ukuze kufane ne-GUI
· Kubuyekezwe incazelo yokudluliswa kwedatha kuThebula: F-Tile Serial Lite IV Intel FPGA IP Izici.
· Igama lethebula eliqanjwe kabusha i-IP laba yi-F-Tile Serial Lite IV Intel FPGA IP Ipharamitha Incazelo esigabeni esithi Amapharamitha ukuze kucace.
· Ithebula Elibuyekeziwe: Amapharamitha e-IP: — Kwengezwe ipharamitha entsha–RSFEC inikwe amandla kwenye i-Serial Lite IV Simplex IP ebekwe eziteshini ezifanayo ze-FGT. - Kubuyekezwe amanani amisiwe obuningi bewashi lereferensi ye-Transceiver.
Ukukhishwa kokuqala.

I-ISO 9001:2015 Ibhalisiwe

Amadokhumenti / Izinsiza

	Intel F Tile Serial Lite IV Intel FPGA IP [pdf] Umhlahlandlela Womsebenzisi F Tile Serial Lite IV Intel FPGA IP, F Tile Serial Lite IV, Intel FPGA IP
	Intel F-Tile Serial Lite IV Intel FPGA IP [pdf] Umhlahlandlela Womsebenzisi F-Tile Serial Lite IV Intel FPGA IP, Serial Lite IV Intel FPGA IP, Lite IV Intel FPGA IP, IV Intel FPGA IP, FPGA IP, IP