intel F-Tile Interlaken FPGA IPDesign Example Umhlahlandlela Womsebenzisi

 

Ibuyekezelwe i-Intel® Quartus® Prime Design Suite: 21.4
Inguqulo ye-IP: 3.1.0

1. Umhlahlandlela Wokuqala Ngokushesha

I-F-Tile Interlaken Intel® FPGA IP core inikeza ibhentshi lokuhlola lokulingisa kanye ne-ex yedizayini yehadiwe.ample esekela ukuhlanganiswa nokuhlolwa kwehadiwe. Uma udala i-ex designample, umhleli wepharamitha udala ngokuzenzakalelayo i filekudingekile ukulingisa, ukuhlanganisa, nokuhlola umklamo.

I-testbench kanye ne-design example isekela imodi ye-NRZ ne-PAM4 yamadivayisi we-F-tile.
I-F-Tile Interlaken Intel FPGA IP core ikhiqiza i-design exampizinhlanganisela ezilandelayo ezisekelwayo zenani lemizila namazinga edatha.

Ithebula 1. Inhlanganisela Esekelwe I-IP Yenombolo Yemizila Nezilinganiso Zedatha
Izinhlanganisela ezilandelayo zisekelwa ku-Intel Quartus® Prime Pro Edition software version 21.4. Konke
ezinye izinhlanganisela zizosekelwa enguqulweni yesikhathi esizayo ye-Intel Quartus Prime Pro Edition.

 

Umfanekiso 1. Izinyathelo Zokuthuthukisa Zomklamo Example

(1) Lokhu okuhlukile kusekela i-Interlaken Look-aside Mode.
(2) Ngomklamo wokumisa wemizila eyi-10, i-F-tile idinga imizila engu-12 ye-TX PMA ukuze inike amandla iwashi le-transceiver eliboshiwe ukuze kuncishiswe i-skew yesiteshi.

*Amanye amagama namabhrendi angafunwa njengempahla yabanye.

I-F-Tile Interlaken Intel FPGA IP core design example isekela izici ezilandelayo:

• I-TX yangaphakathi kuya kumodi ye-serial loopback ye-RX
• Yakha ngokuzenzakalelayo amaphakethe osayizi ongashintshi
• Amakhono okuhlola iphakethe ayisisekelo
• Ikhono lokusebenzisa Ikhonsoli Yesistimu ukuze usethe kabusha idizayini ngenjongo yokuhlola kabusha

Umfanekiso 2. Umdwebo weBlock wezinga eliphezulu

Ulwazi Oluhlobene

• Umhlahlandlela Womsebenzisi we-F-Tile Interlaken Intel FPGA IP
• I-F-Tile Interlaken Intel FPGA IP Amanothi okukhishwa

1.1. Izingxenyekazi zekhompuyutha nezidingo zeSoftware
Ukuhlola i-example design, sebenzisa ihadiwe nesoftware elandelayo:

• Isoftware ye-Intel Quartus Prime Pro Edition engu-21.4
• Ikhonsoli yesistimu itholakala ngesoftware ye-Intel Quartus Prime Pro Edition
• Isifanisi esisekelwayo:
  - Synopsy* VCS*
  - Ama-synopsy VCS MX
  — Siemens* EDA ModelSim* SE noma Questa*
  -Cadence* Xcelium*
• I-Intel Agilex™ I-Series Transceiver-SoC Development Kit

1.2. Ikhiqiza Umklamo
Umfanekiso 3. Inqubo

Landela lezi zinyathelo ukuze ukhiqize i-ex yokuklamaample kanye ne-testbench:

1. Kuhlelo lwe-Intel Quartus Prime Pro Edition, chofoza File ➤ Iseluleki Sephrojekthi Esisha sokudala iphrojekthi entsha ye-Intel Quartus Prime, noma chofoza File ➤ Vula Iphrojekthi ukuze uvule iphrojekthi ekhona ye-Intel Quartus Prime. Iwizadi ikutshela ukuthi ucacise idivayisi.
2. Cacisa i-Agilex yomndeni wedivayisi bese ukhetha idivayisi ene-F-Tile yomklamo wakho.
3. Kukhathalogi ye-IP, thola bese uchofoza kabili i-F-Tile Interlaken Intel FPGA IP. Iwindi elisha le-IP elihlukile liyavela.
4. Cacisa igama lezinga eliphezulu ngokuhlukahluka kwakho kwe-IP yangokwezifiso. Umhleli wepharamitha ugcina izilungiselelo zokuhlukahluka kwe-IP ku-a file okuthiwa .ip.
5. Chofoza okuthi KULUNGILE. Umhleli wepharamitha uyavela.

Umfanekiso 4. IsbampIthebhu Yokuklama

6. Kuthebhu ye-IP, cacisa imingcele yokuhluka kwakho kwe-IP core.
7. Ku-Example Design ithebhu, khetha inketho yokulingisa ukuze ukhiqize ibhentshi lokuhlola. Khetha inketho ye-Synthesis ukuze ukhiqize i-ex ye-hardware designample. Kufanele ukhethe okungenani eyodwa yezinketho Zokulingisa kanye Nokuhlanganiswa ukuze ukhiqize i-ex yedizayiniample.
8. Ngefomethi ye-HDL Ekhiqiziwe, kokubili inketho ye-Verilog ne-VHDL iyatholakala.
9. Ngekhithi Yokuthuthukisa Ithagethi, khetha Ikhithi Yokuthuthukisa ye-Agilex I-Series Transceiver-SOC.

Qaphela: Uma ukhetha inketho Yekhithi Yokuthuthukisa, imisebenzi yephinikhodi isethwa ngokuya ngenombolo yedivayisi ye-Intel Agilex I-Series Transceiver-SoC Development Kit (AGIB027R31B1E2VR0) futhi ingase ihluke kudivayisi yakho oyikhethile. Uma uhlose ukuhlola idizayini ku-hardware ku-PCB ehlukile, khetha inketho ethi Ayikho ikhithi yokuthuthukisa bese wenza iphinikhodi elifanele ku-.qsf file
10. Chofoza okuthi Khiqiza Isibample Design. Khetha ExampIwindi le-Design Directory liyavela.
11. Uma ufuna ukulungisa i-design exampindlela yohla lwemibhalo noma igama elisuka kokumisiwe okubonisiwe (ilk_f_0_example_design), phequlula endleleni entsha bese uthayipha umklamo omusha exampigama lesikhombi.
12. Chofoza OK.

Qaphela: Ku-F-Tile Interlaken Intel FPGA IP yomklamo example, i-SystemPLL ifakwa ngokuzenzakalelayo, futhi ixhunywe ku-F-Tile Interlaken Intel FPGA IP core. Indlela ye-SystemPLL ye-hierarchy ku-design example yi:

example_design.test_env_inst.test_dut.dut.pll

I-SystemPLL ku-design example yabelana ngewashi lereferensi le-156.26 MHz njenge-Transceiver.

1.3. Ukwakheka Kwemibhalo
I-F-Tile Interlaken Intel FPGA IP core ikhiqiza okulandelayo files for the design
example:
Umfanekiso 5. Ukwakheka Kwemibhalo

Ithebula 2. I-Hardware Design Example File Izincazelo
Lezi files zikuample_installation_dir>/ilk_f_0_example_design directory.

Ithebula 3. Testbench File Incazelo
Lokhu file ikuample_installation_dir>/ilk_f_0_example_design/example_design/rtl directory.

Ithebula 4. Izikripthi ze-Testbench
Lezi files zikuample_installation_dir>/ilk_f_0_example_design/example_design/testbench directory.

1.4. Ukulingisa i-Design Example Testbench
Umfanekiso 6. Inqubo

Landela lezi zinyathelo ukuze ulingise i-testbench:

1. Emyalweni womyalo, shintshela kumkhombandlela wokulingisa we-testbench. Indlela yohla lwemibhalo ithiample_installation_dir>/example_design/testbench.
2. Qalisa iskripthi sokulingisa sesifanisi esisekelwayo ozikhethele sona. Umbhalo uhlanganisa futhi uqhube ibhentshi lokuhlola kusifanisi. Iskripthi sakho kufanele sihlole ukuthi izibalo ze-SOP ne-EOP ziyafana ngemva kokuqedwa kokulinganisa.

Ithebula 5. Izinyathelo Zokuqalisa Ukulingisa

3. Hlaziya imiphumela. Ukulingisa okuphumelelayo kuthumela futhi kwamukele amaphakethe, futhi kubonisa "Ukuhlola KUPHASIWE".
Ibhentshi lokuhlola le-ex designample uqeda imisebenzi elandelayo:

• Iqinisekisa i-F-Tile Interlaken Intel FPGA IP core.
• Iphrinta isimo se-PHY.
• Ihlola ukuvumelanisa kwe-metaframe (SYNC_LOCK) nemingcele yegama (vimba).
  (WORD_LOCK).
• Ilinda imizila ngayinye ukuthi ikhiywe futhi iqondaniswe.
• Iqala ukudlulisa amaphakethe.
• Ihlola izibalo zephakethe:
  - CRC24 amaphutha
  - Ama-SOP
  - EOP

Okulandelayo sampokukhiphayo kubonisa ukuqaliswa kokuhlolwa kokulingisa okuyimpumelelo:

Qaphela: I-Interlaken design exampI-le simulation testbench ithumela amaphakethe ayi-100 futhi ithola amaphakethe ayi-100.

Okulandelayo sampokukhiphayo kubonisa ukuqaliswa kokuhlolwa kokulingisa okuyimpumelelo kwemodi ye-Interlaken Look-aside:

1.5. Ukuhlanganisa kanye nokulungiselela i-Hardware Design Example

1. Qinisekisa i-exampi-design generation iqedile.
2. Kuhlelo lwe-Intel Quartus Prime Pro Edition, vula iphrojekthi ye-Intel Quartus Primeample_installation_dir>/example_design.qpf>.
3. Use Iyacubungula imenyu, chofoza Qala Ukuhlanganisa.
4. Ngemva kokuhlanganiswa ngempumelelo, i-.sof file iyatholakala ohlwini lwakho lwemibhalo olushilo.
   Landela lezi zinyathelo ukuze uhlele i-hardware example design kudivayisi ye-Intel Agilex ene-F-tile:
   a. Xhuma Ikhithi Yokuthuthukisa kukhompuyutha yokusingatha.
   b. Yethula uhlelo lokusebenza Lokulawula Iwashi, oluyingxenye yekhithi yokuthuthukisa. Setha amafrikhwensi amasha we-ex designampnjengokulandelayo:
   • Ngemodi ye-NRZ:
   — Si5391 (U18), OUT0: Misa inani le-pll_ref_clk(3) ngokwemfuneko yakho yomklamo.
   • Ngemodi ye-PAM:
   — Si5391 (U45), OUT1: Misa inani le-pll_ref_clk(3) ngokwemfuneko yakho yomklamo.
   — Si5391 (U19), OUT1: Misa inani le-mac_pll_ref_clk(3) ngokwemfuneko yakho yomklamo. c. Chofoza Amathuluzi ➤ Umklami ➤ Ukusethwa kwezingxenyekazi zekhompyutha.
   d. Khetha idivayisi yokuhlela. Engeza i-Intel Agilex I-Series Transceiver-SoC Development Kit.
   e. Qinisekisa ukuthi Imodi isethwe ku JTAG.
   f. Khetha idivayisi ye-Intel Agilex I-Series bese uchofoza Engeza Idivayisi. Umhleli ubonisa umdwebo wokuxhumana phakathi kwamadivayisi ebhodini lakho.
   g. Thikha ibhokisi le-.i-sof.
   h. Thikha ibhokisi ku- Uhlelo/Lungisa ikholomu.
   i. Chofoza Qala.

1.6. Ihlola i-Hardware Design Example
Ngemva kokuhlanganisa i-F-tile Interlaken Intel FPGA IP design exampfuthi ulungiselele idivayisi yakho, ungasebenzisa Ikhonsoli Yesistimu ukuhlela umongo we-IP namarejista ayo.

Landela lezi zinyathelo ukuze uveze Ikhonsoli Yesistimu futhi uhlole i-ex yedizayini yehadiweample:

• Awekho amaphutha e-CRC32, CRC24, nesihloli.
• Ama-SOP nama-EOP adlulisiwe kufanele afane nama-SOP nama-EOP atholiwe.

Okulandelayo sampi-le output ibonisa ukuhlolwa okuphumelelayo okwenziwa kumodi ye-Interlaken:

Okulandelayo sampi-le okukhiphayo ibonisa ukuhlolwa okuphumelelayo kumodi ye-Interlaken Lookaside:

 

2. Umklamo Example Incazelo

Umklamo exampI-le ibonisa ukusebenza kwe-Interlaken IP core.

2.1. Umklamo Example Components
I-exampi-le design ixhuma amawashi ereferensi wesistimu kanye ne-PLL kanye nezingxenye zokuklama ezidingekayo. I-exampi-le design ilungisa i-IP core kumodi ye-loopback yangaphakathi futhi ikhiqize amaphakethe ku-IP core TX yokudlulisa idatha yomsebenzisi. I-IP core ithumela lawa maphakethe kumzila we-loopback wangaphakathi nge-transceiver.

Ngemuva kokuthi umamukeli oyinhloko we-IP ethole amaphakethe endleleni ye-loopback, icubungula amaphakethe e-Interlaken futhi iwathumele kusixhumi esibonakalayo sokudlulisa idatha yomsebenzisi we-RX. I-exampi-le design ihlola ukuthi amaphakethe atholiwe futhi adluliselwe afanayo.

Umklamo we-F-Tile Interlaken Intel FPGA IP example ihlanganisa izingxenye ezilandelayo:

1. I-F-Tile Interlaken Intel FPGA IP core
2. I-Packet Generator kanye ne-Packet Checker
3. Ireferensi ye-F-Tile kanye namawashi esistimu ye-PLL Intel FPGA IP core

2.2. Umklamo Example Flow
I-F-Tile Interlaken Intel FPGA IP hardware design example uqedela izinyathelo ezilandelayo:

1. Setha kabusha i-F-tile Interlaken Intel FPGA IP kanye ne-F-Tile.
2. Khipha ukusetha kabusha ku-Interlaken IP (ukusethwa kabusha kwesistimu) naku-F-tile TX (tile_tx_rst_n).
3. Ilungiselela i-F-tile Interlaken Intel FPGA IP kumodi ye-loopback yangaphakathi.
4. Khipha ukusetha kabusha kwe-F-tile RX (tile_rx_rst_n).
5. Ithumela uchungechunge lwamaphakethe e-Interlaken anedatha echazwe kusengaphambili ekulayishweni okukhokhelwayo kusixhumi esibonakalayo sokudlulisa idatha somsebenzisi we-TX somongo we-IP.
6. Ihlola amaphakethe atholiwe bese ibika isimo. Isihloli sephakethe esifakwe kumklamo we-hardware exampI-le inikeza amakhono alandelayo okuhlola iphakethe:
   • Hlola ukuthi ukulandelana kwephakethe elidlulisiwe kulungile.
   • Ihlola ukuthi idatha etholiwe ifana namanani alindelekile ngokuqinisekisa ukuthi izibalo zokuqala zephakethe (SOP) kanye nokuphela kwephakethe (EOP) ziqondana ngenkathi idatha idluliswa futhi yamukelwa.

*Amanye amagama namabhrendi angafunwa njengempahla yabanye.

2.3. Izimpawu Zokuxhumana
Ithebula 6. Idizayini Example Interface Signals

2.4. Bhalisa imephu

Qaphela:

• I-Design ExampIkheli lerejista liqala ngo-0x20** kuyilapho ikheli lerejista eliyinhloko le-Interlaken IP liqala ngo-0x10**.
• Ikheli lerejista le-F-tile PHY liqala ngo-0x30** kuyilapho ikheli lerejista le-F-tile FEC liqala ngo-0x40**. Irejista ye-FEC itholakala kuphela ngemodi ye-PAM4.
• Ikhodi yokufinyelela: RO—Funda Kuphela, kanye ne-RW—Funda/Bhala.
• Ikhonsoli yesistimu ifunda umklamo example irejista futhi ibike isimo sokuhlola esikrinini.

Ithebula 7. Idizayini Example Bhalisa imephu

Ithebula 8. Idizayini Example Bhalisa imephu ye-Interlaken Bheka eceleni Yomklamo Example
Sebenzisa le mephu yerejista lapho udala i-ex designample enepharamitha ethi Vumela i-Interlaken Look-aside Mode evuliwe.

2.5. Hlela kabusha
Kumongo we-F-Tile Interlaken Intel FPGA IP, uqala ukusetha kabusha (reset_n=0) futhi ubambe kuze kube yilapho umgogodla we-IP ubuyisela ukuvuma kokusetha kabusha (reset_ack_n=0). Ngemva kokususwa kokusetha kabusha (reset_n=1), ukuvuma kokusetha kabusha kubuyela esimweni sako sokuqala (reset_ack_n=1). Kumklamo exampLe, irejista ye-rst_ack_sticky ibamba ukugomela kokusetha kabusha bese icupha ukususwa kokusetha kabusha (setha kabusha_n=1). Ungasebenzisa ezinye izindlela ezihambisana nezidingo zakho zokuklama.

Okubalulekile: Kunoma isiphi isimo lapho kudingeka khona i-serial loopback yangaphakathi, kufanele ukhulule i-TX ne-RX ye-F-tile ngokuhlukana ngokulandelana ngendlela ethile. Bheka kumbhalo wekhonsoli yesistimu ukuze uthole ulwazi olwengeziwe.

Umfanekiso 7. Setha kabusha Ukulandelana Kumodi ye-NRZ

Umfanekiso 8. Setha kabusha Ukulandelana Kumodi ye-PAM4

 

3. I-F-Tile Interlaken Intel FPGA IP Design Example Izingobo zomlando zomhlahlandlela womsebenzisi

Uma inguqulo ye-IP eyinhloko ingekho ohlwini, umhlahlandlela womsebenzisi wenguqulo yangaphambilini ye-IP iyasebenza.

 

4. Umlando Wokubuyekezwa Kombhalo we-F-Tile Interlaken Intel FPGA IP Design Example Umhlahlandlela Womsebenzisi

 

Inkampani ye-Intel Wonke Amalungelo Agodliwe. I-Intel, ilogo ye-Intel, nezinye izimpawu ze-Intel yizimpawu zokuthengisa ze-Intel Corporation noma izinkampani ezingaphansi kwayo. I-Intel iqinisekisa ukusebenza kwe-FPGA yayo kanye nemikhiqizo ye-semiconductor ibe yamanje
imininingwane ngokuhambisana newaranti evamile ye-Intel, kodwa igodla ilungelo lokwenza izinguquko kunoma imiphi imikhiqizo namasevisi nganoma yisiphi isikhathi ngaphandle kwesaziso. I-Intel ayithathi mthwalo noma isikweletu esivele ngenxa yesicelo noma ukusetshenziswa kwanoma yiluphi ulwazi, umkhiqizo, noma isevisi echazwe lapha ngaphandle kwalapho okuvunyelwene ngakho ngokubhaliwe yi-Intel. Amakhasimende e-Intel ayelulekwa ukuthi athole inguqulo yakamuva yokucaciswa kwedivayisi ngaphambi kokuthembela kunoma yiluphi ulwazi olushicilelwe nangaphambi kokufaka ama-oda emikhiqizo noma amasevisi.

 

Funda okwengeziwe ngale Manuwali & Landa i-PDF:

Amadokhumenti / Izinsiza

intel F-Tile Interlaken FPGA IPDesign Example [pdf] Umhlahlandlela Womsebenzisi I-F-Tile Interlaken FPGA IPDesign Example

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