I-Low Latency E-Tile 40G Ethernet Intel FPGA IP Design Example

Quick Start Guide

I-Low Latency E-Tile 40G Ethernet Intel® FPGA IP core inikeza ibhentshi lokuhlola lokulingisa kanye ne-ex yedizayini yehadiwe.ample esekela ukuhlanganiswa nokuhlolwa kwehadiwe. Uma udala i-ex designample, umhleli wepharamitha we-Intel Quartus® Prime IP udala ngokuzenzakalelayo i filekudingekile ukulingisa, ukuhlanganisa, nokuhlola idizayini kuhadiwe. Ngaphezu kwalokho, ungalanda idizayini yehadiwe ehlanganisiwe kukhithi yokuthuthukisa yedivayisi ye-Intel ukuze kuhlolwe ngokusebenzisana. I-Intel FPGA IP ihlanganisa ne-ex yokuhlanganisa kuphelaample phrojekthi ongayisebenzisa ukuze ulinganisele ngokushesha indawo eyinhloko ye-IP nesikhathi. I-Low Latency E-Tile 40G Ethernet Intel FPGA IP isekela i-design exampi-le generation enohlu olubanzi lwamapharamitha. Nokho, i-design exampLes ayimbozi wonke amapharamitha angenzeka we-Low Latency E-Tile 40G Ethernet Intel FPGA IP Core.

Izinyathelo Zokuthuthukisa Zomklamo Example

Ulwazi Oluhlobene

• I-Low Latency E-Tile 40G Ethernet Intel FPGA IP User Guide
  Ukuze uthole ulwazi oluningiliziwe nge-Low Latency E-Tile 40G Ethernet IP.
• I-Low Latency E-Tile 40G Ethernet Intel FPGA IP Amanothi okukhishwa
  Uhlu lwamanothi okukhishwa kwe-IP lushintsha ekukhishweni okuthile.

Ukukhiqiza I-Design Example

Inqubo

Inkampani ye-Intel Wonke Amalungelo Agodliwe. I-Intel, ilogo ye-Intel, nezinye izimpawu ze-Intel yizimpawu zokuthengisa ze-Intel Corporation noma izinkampani ezingaphansi kwayo. I-Intel iqinisekisa ukusebenza kwe-FPGA yayo kanye nemikhiqizo yesemiconductor ekucacisweni kwamanje ngokuvumelana newaranti evamile ye-Intel, kodwa igodla ilungelo lokwenza izinguquko kunoma imiphi imikhiqizo namasevisi nganoma yisiphi isikhathi ngaphandle kwesaziso. I-Intel ayithathi mthwalo noma isikweletu esivele ngenxa yesicelo noma ukusetshenziswa kwanoma yiluphi ulwazi, umkhiqizo, noma isevisi echazwe lapha ngaphandle kwalapho okuvunyelwene ngakho ngokubhaliwe yi-Intel. Amakhasimende e-Intel ayelulekwa ukuthi athole inguqulo yakamuva yokucaciswa kwedivayisi ngaphambi kokuthembela kunoma yiluphi ulwazi olushicilelwe nangaphambi kokufaka ama-oda emikhiqizo noma amasevisi. Amanye amagama namabhrendi angafunwa njengempahla yabanye.

Example-Design Tab ku-Low Latency E-Tile 40G Ethernet Parameter Editor
Khetha i-Stratix 10 TX E-Tile Transceiver Signal Integrity Development Kit ukuze ukhiqize i-design ex.ample yamadivayisi we-Intel Stratix® 10. Khetha i-Agilex F-series Transceiver-SoC Development Kit ukuze ukhiqize i-design example yamadivayisi we-Intel Agilex™.

Landela lezi zinyathelo ukuze ukhiqize i-ex ye-hardware designample kanye ne-testbench:

1. Kuhlelo lwe-Intel Quartus Prime Pro Edition, chofoza File ➤ Iselekeleli Sephrojekthi Esisha
   ukwakha iphrojekthi entsha ye-Intel Quartus Prime, noma File ➤ Vula Iphrojekthi ukuze uvule iphrojekthi yesofthiwe ye-Intel Quartus Prime ekhona. Iwizadi ikwazisa ukuthi ucacise umndeni wedivayisi nedivayisi.
   Qaphela: Umklamo exampibhala phezu kwalokho okukhethiwe ngocingo ebhodini eliqondiwe. Ucacisa ibhodi eliqondiwe kusuka kumenyu ye-design example ongakhetha kukho Example Dizayini ithebhu (Isinyathelo 8).
2. Kukhathalogi ye-IP, thola bese ukhetha i-Low Latency E-Tile 40G Ethernet Intel FPGA IP. Iwindi le-New IP Variation liyavela.
3. Cacisa igama lezinga eliphezulu lokuhluka kwakho kwe-IP yangokwezifiso. Isihleli sepharamitha ye-Intel Quartus Prime IP sigcina izilungiselelo zokuhlukahluka kwe-IP ku-a file okuthiwa .ip.
4. Chofoza okuthi KULUNGILE. Umhleli wepharamitha ye-IP uyavela.
5. Kuthebhu ye-IP, cacisa imingcele yokuhluka kwakho okubalulekile kwe-IP.
   Qaphela: I-Low Latency E-Tile 40G Ethernet Intel FPGA IP design exampi-le ayilingisi ngendlela efanele futhi ayisebenzi kahle uma ucacisa noma yimiphi imigomo elandelayo:
   1. Nika amandla ukudlula okwesethulo kuvuliwe
   2. Ukubambezeleka okulungele kusethelwe kunani elingu-3
   3. Nika amandla ukufakwa kwe-TX CRC kuvaliwe
6. Ku-Example Dizayini ithebhu, ngaphansi kwe-Example Design Files, nika amandla inketho Yokulingisa ukuze ukhiqize ibhentshi lokuhlola, bese ukhetha inketho ye-Synthesis ukuze ukhiqize i-ex yokuhlanganisa kuphela ne-hardware design.ampLes.
   Qaphela: Ku-Example Design ithebhu, ngaphansi kwefomethi ye-HDL Ekhiqiziwe, i-Verilog HDL kuphela etholakalayo. Le IP core ayisekeli i-VHDL.
7. Ngaphansi Kwekhithi Yokuthuthukisa Okuqondisiwe khetha Ikhithi Yokuthuthukisa Ubuqotho ye-Stratix 10 TX E-Tile Transceiver Signal noma i-Agilex F-series Transceiver-SoC Development Kit.
   Qaphela: Ikhithi yokuthuthukisa oyikhethayo ivala ukukhethwa kwedivayisi kokuthi Isinyathelo
   1. Idivayisi eqondiwe ye-Intel Stratix 10 E-tile ithi 1SG280LU3F50E3VGS1.
   2. Ithagethi yedivayisi ye-Intel Agilex E-tile ithi AGFB014R24A2E2VR0.
8. Chofoza okuthi Khiqiza i-Exampinkinobho ethi Design. Khetha ExampIwindi le-Design Directory liyavela.
9. Uma ufuna ukushintsha i-design example mkhombandlela noma igama elivela kokumisiwe okubonisiwe (alt_e40c3_0_example_design), phequlula endleleni entsha bese uthayipha umklamo omusha exampigama lenkomba (ample_dir>).
10. Chofoza okuthi KULUNGILE.

Ulwazi Oluhlobene

• Amapharamitha we-IP Core
  Inikeza ulwazi olwengeziwe mayelana nokwenza ngendlela oyifisayo i-IP core yakho.
• I-Intel Stratix 10 E-Tile TX Signal Integrity Development Kit
• Intel Agilex F-Series FPGA Development Kit

I-Design Example Amapharamitha

Amapharamitha ku-ExampIthebhu Yokuklama

Ipharamitha	Incazelo
Khetha i-Design	Isib esitholakalayoampidizayina izilungiselelo zepharamitha ye-IP. Uma ukhetha idizayini kumtapo wolwazi osethiwe, le nkambu ibonisa umklamo okhethiwe.
Example Design Files	I files ukukhiqizela isigaba sentuthuko esihlukene. •    Ukulingisa- yenza okudingekayo files yokulingisa i-exampumklamo. •    I-synthesis- yenza i-synthesis files. Sebenzisa lezi files ukuhlanganisa umklamo kusofthiwe ye-Intel Quartus Prime Pro Edition yokuhlolwa kwezingxenyekazi zekhompuyutha nokwenza ukuhlaziya isikhathi esimile.
Khiqiza File Ifomethi	Ifomethi ye-RTL files yokulingisa—i-Verilog noma i-VHDL.
Khetha Ibhodi	Izingxenyekazi zekhompuyutha ezisekelwayo zokuqaliswa komklamo. Uma ukhetha ibhodi lokuthuthukiswa kwe-Intel, i Idivayisi eqondiwe iyona efana nedivayisi Kukhithi Yokuthuthukisa. Uma le menyu ingatholakali, alikho ibhodi elisekelwayo lezinketho ozikhethayo. I-Agilex F-series Transceiver-SoC Development Kit: Le nketho ikuvumela ukuthi uhlole i-ex designample kukhithi yokuthuthukisa ye-Intel FPGA IP ekhethiwe. Le nketho ikhetha ngokuzenzakalelayo i Idivayisi eqondiwe Idatha ye-AGFB014R24A2E2VR0. Uma ukubuyekezwa kwebhodi lakho kunebanga elihlukile ledivayisi, ungashintsha idivayisi eqondiwe.
waqhubeka...

Ipharamitha

Incazelo

I-Stratix 10 TX E-Tile Transceiver Signal Integrity Development Kit: Le nketho ikuvumela ukuthi uhlole i-ex designample kukhithi yokuthuthukisa ye-Intel FPGA IP ekhethiwe. Le nketho ikhetha ngokuzenzakalelayo i Idivayisi eqondiwe Idatha ye-1ST280EY2F55E2VG Uma ukubuyekezwa kwebhodi lakho kunebanga elihlukile ledivayisi, ungashintsha idivayisi eqondiwe. Lutho: Le nketho ayifaki izici zehadiwe ye-ex yedizayiniample.

Ukwakheka Kwemibhalo
I-Low Latency E-Tile 40G Ethernet IP core design example file uhla lwemibhalo luqukethe okulandelayo okwenziwe files ye-design example.

Isakhiwo sohlu lwemibhalo ye-Generated Design Example

• Ukulingiswa files (i-testbench yokulingisa kuphela) itholakala kuample_dir>/example_testbench.
• I-ex yokuhlanganisa kuphelaample design itholakala kuample_dir>/ compilation_test_design.
• Ukucushwa kwezingxenyekazi zekhompuyutha nokuhlola files (i-hardware design example) zitholakala kuample_dir>/hardware_test_design

Uhla lwemibhalo kanye File Izincazelo

File Amagama	Incazelo
ethi_ex_40g.qpf	Iphrojekthi ye-Intel Quartus Prime file.
eth_ex_40g.qsf	Izilungiselelo zephrojekthi ye-Intel Quartus Prime file.
waqhubeka...

File Amagama	Incazelo
eth_ex_40g.sdc	I-Synopsy* Imikhawulo yedizayini file. Ungakopisha futhi ulungise lokhu file ngomklamo wakho we-Low Latency E-Tile 40G Ethernet Intel FPGA IP.
eth_ex_40g.srf	Umthetho wokucindezela umlayezo wephrojekthi we-Intel Quartus Prime file.
eth_ex_40g.v	Idizayini yezinga eliphezulu ye-Verilog HDL example file.
eth_ex_40g_clock.sdc	I-Synopsys Design Constrants file amawashi.
okuvamile/	Idizayini yezingxenyekazi zekhompuyutha example support files.
hwtest/main.tcl	Okuyinhloko file ukuze ufinyelele Ikhonsoli Yesistimu.

Ukulingisa i-Design Example Testbench
Ungakwazi ukuhlanganisa futhi ulingise umklamo ngokusebenzisa iskripthi sokulingisa kusukela kumyalo womyalo.

1. Emyalweni womyalo, shintsha uhla lwemibhalo olusebenzayo lubeample_dir>/example_testbench.
2. Qalisa iskripthi sokulingisa sesifanisi esisekelwayo ozikhethele sona. Umbhalo uhlanganisa futhi uqhube ibhentshi lokuhlola kusifanisi

Imiyalo Yokulingisa I-Testbench

Isifanisi	Iziyalezo
ImodeliSim*	Emugqeni womyalo, thayipha i-vsim -do run_vsim.do. Uma ukhetha ukulingisa ngaphandle kokuletha i-ModelSim GUI, thayipha i-vsim -c -do run_vsim.do. Qaphela: Izilingisi ze-ModelSim-AE ne-ModelSim-ASE azikwazi ukulingisa lo mgogodla we-IP. Kufanele usebenzise esinye isifanisi se-ModelSim esisekelwayo njenge-ModelSim SE.
VCS*	Emugqeni womyalo, thayipha okuthi sh run_vcs.sh
I-VCS MX	Emugqeni womyalo, thayipha okuthi sh run_vcsmx.sh. Sebenzisa lesi sikripthi uma umklamo uqukethe i-Verilog HDL ne-System Verilog ene-VHDL.
I-NCSim	Emugqeni womyalo, thayipha okuthi sh run_ncsim.sh
I-Xcelium*	Emugqeni womyalo, thayipha okuthi sh run_xcelium.sh

Ukulingisa okuyimpumelelo kugcina ngomlayezo olandelayo: Ukulingisa Kuphasisiwe. noma i-Testbench iqedile. Ngemva kokuphothula ngempumelelo, ungakwazi ukuhlaziya imiphumela.

Ukuhlanganisa kanye nokulungiselela i-Design Exampku-Hardware
I-Intel FPGA IP core parameter editor ikuvumela ukuthi uhlanganise futhi ulungiselele i-ex designampekhithi yokuthuthukisa eqondiwe

Ukuhlanganisa nokumisa i-ex designampku-hardware, landela lezi zinyathelo:

1. Yethula isofthiwe ye-Intel Quartus Prime Pro Edition bese ukhetha Ukucubungula ➤ Qala Ukuhlanganisa ukuze uhlanganise umklamo.
2. Ngemva kokwenza into ye-SRAM file .sof, landela lezi zinyathelo ukuze uhlele i-hardware design example kudivayisi ye-Intel:
   1. Khetha Amathuluzi ➤ Umklami.
   2. Ku-Programmer, chofoza Ukusethwa Kwezingxenyekazi zekhompuyutha.
   3. Khetha idivayisi yokuhlela.
   4. Khetha bese wengeza ibhodi le-Intel TX kuseshini yakho ye-Intel Quartus Prime Pro Edition.
   5. Qinisekisa ukuthi Imodi isethwe ku-JTAG.
   6. Khetha idivayisi ye-Intel bese uchofoza Engeza idivayisi. I-Programmer ibonisa idayagramu yebhlokhi yokuxhumana phakathi kwamadivayisi ebhodini lakho.
   7. Emgqeni ne-.sof yakho, hlola ibhokisi le-.sof.
   8. Vula inketho yoHlelo/Lungisa ye-.sof.
   9. Chofoza Qala.

Ulwazi Oluhlobene

• Ukuhlanganiswa Okukhulayo Kwedizayini Esekwe Emaqenjini
• Izinhlelo ze-Intel FPGA Amadivayisi

Ukushintsha idivayisi eqondiwe ku-Hardware Design Example
Uma ukhethe i-Stratix 10 TX E-Tile Transceiver Signal Integrity Development Kit njengedivayisi yakho okuqondiswe kuyo, i-Low Latency E-Tile 40G Ethernet Intel FPGA IP core ikhiqiza i-hardware ex.ample design yedivayisi eqondiwe engu-1ST280EY2F55E2VG. Uma ukhethe i-Agilex F-series Transceiver-SoC Development Kit njengedivayisi yakho eqondiwe, i-Low Latency E-Tile 40G Ethernet Intel FPGA IP core ikhiqiza i-hardware ex.ampidizayini yedivayisi eqondiwe engu-AGFB014R24A2E2VR0. Idivayisi eqondisiwe ecacisiwe ingase yehluke kudivayisi ekukhithi yakho yokuthuthukisa. Ukushintsha idivayisi eqondiwe kumklamo wakho wezingxenyekazi zekhompuyutha example, landela lezi zinyathelo:

1. Yethula isofthiwe ye-Intel Quartus Prime Pro Edition futhi uvule iphrojekthi yokuhlola ihadiwe file /hardware_test_design/eth_ex_40g.qpf.
2. Kumenyu Yezabelo, chofoza Idivayisi. Ibhokisi lengxoxo Yedivayisi liyavela.
3. Ebhokisini lengxoxo Yedivayisi, khetha ithebula ledivayisi eqondiwe esekelwe ku-E elifana nengxenye yenombolo yedivayisi kukhithi yakho yokuthuthukisa. Bheka isixhumanisi sekhithi yokuthuthukisa ku-Intel website ukuthola eminye imininingwane.
4. Ukwaziswa kuvela lapho ukhetha idivayisi, njengoba kukhonjisiwe esithombeni esingezansi. Khetha Cha ukuze ulondoloze imisebenzi yephinikhodi ekhiqiziwe kanye nezabelo ze-I/O.
   I-Intel Quartus Prime Prompt Yokukhethwa Kwedivayisi
5. Yenza ukuhlanganisa okugcwele komklamo wakho.

Manje ungahlola idizayini ku-hardware yakho.

Ulwazi Oluhlobene

• I-Intel Stratix 10 E-Tile TX Signal Integrity Development Kit
• Intel Agilex F-Series FPGA Development Kit

Ihlola i-Low Latency E-Tile 40G Ethernet Intel FPGA IP Design ku-Hardware
Ngemva kokuhlanganisa i-Low Latency E-Tile 40G Ethernet Intel FPGA IP core design example futhi uyilungiselele kudivayisi yakho ye-Intel, ungasebenzisa Ikhonsoli Yesistimu ukuze uhlele umongo we-IP kanye namarejista awo ayinhloko we-PHY IP ashumekiwe. Ukuze uvule ikhonsoli Yesistimu futhi uhlole idizayini yezingxenyekazi zekhompuyutha example, landela lezi zinyathelo:

1. Kuhlelo lwe-Intel Quartus Prime Pro Edition, khetha Amathuluzi ➤ Amathuluzi Okulungisa Amaphutha Esistimu ➤ Ikhonsoli Yesistimu ukuze uqalise ikhonsoli yesistimu.
2. Kufasitelana le-Tcl Console, thayipha i-cd hwtest ukuze uguqule uhla lwemibhalo lube /hardware_test_design/hwtest.
3. Thayipha umthombo main.tcl ukuze uvule uxhumano ku-JTAG inkosi.

Idizayini eyengeziwe isbample miyalo iyatholakala ukuze kuhlelwe i-IP core:

• chkphy_isimo: Ibonisa amaza wewashi nesimo sokukhiya se-PHY.
• chkmac_stats: Ibonisa amanani ezibalini zezibalo ze-MAC.
• sula_zonke_izibalo: Isula izibali zezibalo ezibalulekile ze-IP.
• qala_pkt_gen: Iqala ijeneretha yephakethe.
• stop_pkt_gen: Imisa ijeneretha yephakethe.
• sys_reset_digital_analog: Ukuhlelwa kabusha kwesistimu.
• vula_kuvuliwe: Ivula i-loopback ye-serial yangaphakathi
• iluphu_off: Ivala i-loopback ye-serial yangaphakathi.
• reg_funda : Ibuyisela inani lerejista eyinhloko ye-IP kokuthi .
• bhala_bhala : Uyabhala kurejista ye-IP eyinhloko ekhelini .

Landela inqubo yokuhlola engxenyeni yokuhlola izingxenyekazi zekhompuyutha ye-ex yomklamoample bese ubheka imiphumela yokuhlola kukhonsoli Yesistimu.

Ulwazi Oluhlobene
Ukuhlaziya nokulungisa amadizayini nge-System Console

I-Design Example Incazelo

I-E-tile esekwe ku-40G Ethernet design exampI-le ibonisa imisebenzi ye-Low Latency E-Tile 40G Ethernet Intel FPGA IP core, ene-E-tile based transceiver interface ethobelana nokucaciswa kwe-IEEE 802.3ba okujwayelekile kwe-CAUI-4. Ungakwazi ukukhiqiza umklamo kusukela Example Dizayini ithebhu kusihleli sepharamitha yepharamitha ye-Low Latency E-Tile 40G Ethernet Intel FPGA IP.
Ukukhiqiza i-design exampNokho, kufanele uqale usethe amanani epharamitha okuhluka okuyinhloko kwe-IP ohlose ukukukhiqiza kumkhiqizo wakho wokugcina. Ikhiqiza i-ex designample idala ikhophi ye-IP core; i-testbench kanye ne-hardware design exampngisebenzise lokhu kuhluka njenge-DUT. Uma ungasethi amanani epharamitha e-DUT ukuze afane namanani epharamitha kumkhiqizo wakho wokugcina, i-design ex.ampokukhiqizayo akusebenzisi ukuhluka okuyinhloko kwe-IP ohlosile.

Qaphela:
I-testbench ibonisa ukuhlolwa okuyisisekelo kwe-IP core. Akuhloselwe ukuba esikhundleni sendawo yokuqinisekisa egcwele. Kufanele wenze ukuqinisekiswa okubanzi okwengeziwe kwedizayini yakho ye-Low Latency E-Tile 40G Ethernet Intel FPGA IP ekulingiseni nakwihadiwe.

Izici

• Isekela i-40G Ethernet MAC/PCS IP core ye-E-tile transceiver isebenzisa i-Intel Stratix 10 noma idivayisi ye-Intel Agilex.
• Isekela isandulelo sokudlula nokuqeqeshwa kwesixhumanisi.
• Ikhiqiza i-design example enesici sokubala sezibalo ze-MAC.
• Ihlinzeka nge-testbench nesikripthi sokulingisa.

Izingxenyekazi zekhompuyutha nezidingo zeSoftware
Ukuhlola i-example design, sebenzisa ihadiwe nesoftware elandelayo:

• Isoftware ye-Intel Quartus Prime Pro Edition
• Ikhonsoli Yesistimu
• I-ModelSim, i-VCS, i-VCS MX, i-NCSim, noma i-Xcelium Simulator
• Ikhithi Yokuthuthukiswa Kobuqotho ye-Intel Stratix 10 TX E-Tile Transceiver Signal Integrity noma i-Intel Agilex F-series Transceiver-SoC Development Kit

Incazelo Esebenzayo
Lesi sigaba sichaza umongo we-40G Ethernet MAC/PCS IP usebenzisa idivayisi ye-Intel ku-E-tile based transceiver. Esiqondisweni sokudlulisa, i-MAC yamukela ozimele beklayenti futhi ifake i-inter-packet gap (IPG), isethulo, ukuqala kwe-frame delimiter (SFD), padding, namabhithi e-CRC ngaphambi kokuwadlulisela ku-PHY. I-PHY ibhala ngekhodi uhlaka lwe-MAC njengoba kudingeka ukuze kudluliselwe okuthembekile ngemidiya kuya ekugcineni kwesilawuli kude. Esiqondisweni sokwamukela, i-PHY idlulisela ozimele ku-MAC. I-MAC yamukela ozimele abavela ku-PHY, yenza ukuhlola, ikhiphe i-CRC, isendlalelo, ne-SFD, futhi idlulisele lonke uhlaka kuklayenti.

Ukulingisa

I-testbench ithumela ithrafikhi nge-IP core, isebenzisa uhlangothi lokudlulisa futhi yamukele uhlangothi lwe-IP core.

I-Low Latency E-Tile 40G Ethernet Design Example Block Diagram

Idizayini yokulingisa isibampukuhlolwa kwezinga eliphezulu file i-basic_avl_tb_top.sv. Lokhu file inikeza inkomba yewashi clk_ref engu-156.25 Mhz ku-PHY. Kuhlanganisa umsebenzi wokuthumela nokwamukela amaphakethe ayi-10.

I-Low Latency E-Tile 40G Ethernet Core Testbench File Izincazelo

File Amagama	Incazelo
Testbench futhi Simulation Files
basic_avl_tb_top.sv	I-testbench yezinga eliphezulu file. I-testbench iqinisekisa i-DUT futhi isebenzisa imisebenzi ye-Verilog HDL ukuze ikhiqize futhi yamukele amaphakethe.
basic_avl_tb_top_nc.sv	I-testbench yezinga eliphezulu file iyahambisana ne-NCSim simulator.
basic_avl_tb_top_msim.sv	I-testbench yezinga eliphezulu file iyahambisana ne-ModelSim simulator.
Izikripthi ze-Testbench
run_vsim.do	Iskripthi se-Mentor Graphics* ModelSim sokuqalisa ibhentshi lokuhlola.
run_vcs.sh	Iskripthi se-Synopsy VCS sokuqalisa ibhentshi lokuhlola.
waqhubeka...

File Amagama	Incazelo
run_vcsmx.sh	Iskripthi se-Synopsys VCS MX (kuhlanganiswe i-Verilog HDL ne-System Verilog ne-VHDL) ukuze kuqalise ibhentshi lokuhlola.
run_ncsim.sh	Iskripthi se-Cadence NCSim sokuqalisa ibhentshi lokuhlola.
run_xcelium.sh	Iskripthi se-cadence Xcelium sokuqalisa ibhentshi lokuhlola.

Ukuhlolwa okuphumelelayo kukhombisa okukhiphayo okuqinisekisa ukuziphatha okulandelayo:

1. Ilinde iwashi le-RX ukuthi lizinze
2. Iphrinta isimo se-PHY
3. Ithumela amaphakethe ayi-10
4. Ithola amaphakethe ayi-10
5. Ibonisa okuthi “Testbench iqedile.”

Okulandelayo sampokukhiphayo kubonisa ukuqaliswa kokuhlolwa kokulingisa okuyimpumelelo:

• #Ilinde ukulungiswa kwe-RX
• #RX deskew ikhiyiwe
• #Ukuqondanisa komzila we-RX kukhiyiwe
• #TX inikwe amandla
• #**Ithumela Iphakethe 1…
• #**Ithumela Iphakethe 2…
• #**Ithumela Iphakethe 3…
• #**Ithumela Iphakethe 4…
• #**Ithumela Iphakethe 5…
• #**Ithumela Iphakethe 6…
• #**Ithumela Iphakethe 7…
• #**Iphakethe elitholiwe 1…
• #**Ithumela Iphakethe 8…
• #**Iphakethe elitholiwe 2…
• #**Ithumela Iphakethe 9…
• #**Iphakethe elitholiwe 3…
• #**Ithumela Iphakethe 10…
• #**Iphakethe elitholiwe 4…
• #**Iphakethe elitholiwe 5…
• #**Iphakethe elitholiwe 6…
• #**Iphakethe elitholiwe 7…
• #**Iphakethe elitholiwe 8…
• #**Iphakethe elitholiwe 9…
• #**Iphakethe elitholiwe 10…

Ulwazi Oluhlobene
Ukulingisa i-Design Example Testbench ekhasini lesi-7

Hardware Testing
Kumklamo wehadiwe example, ungakwazi ukuhlela i-IP core kumodi yangaphakathi ye-serial loopback futhi ukhiqize ithrafikhi kuhlangothi lokudlulisa olujikela emuva ngohlangothi lokwamukela.

I-Low Latency E-Tile 40G Ethernet IP Hardware Design Example High Level Block Diagram

I-Low Latency E-Tile 40G Ethernet hardware design example ihlanganisa izingxenye ezilandelayo:

• I-Low Latency E-Tile 40G Ethernet Intel FPGA IP core.
• I-logic yeklayenti ehlanganisa ukuhlelwa kwe-IP core, nokukhiqizwa kwephakethe nokuhlola.
• I-IOPLL ukukhiqiza iwashi elingu-100 MHz ukusuka ewashi lokokufaka elingu-50 MHz ukuya ku-ex yedizayini yehadiwe.ample.
• JTAG isilawuli esixhumana ne-Intel System Console. Uxhumana ne-logic yeklayenti nge-System Console.

Landela inqubo ekusixhumanisi solwazi esihlobene esinikeziwe ukuze uhlole i-ex designample ku-hardware ekhethiwe.

Ulwazi Oluhlobene

• Ukuhlola i-Low Latency E-Tile 40G Ethernet Intel FPGA IP Design ku-Hardware ekhasini 9
• Ukuhlaziya nokulungisa amadizayini nge-System Console

Ukuhlolwa kwangaphakathi kwe-Loopback
Qalisa lezi zinyathelo ukuze wenze uhlolo lwangaphakathi lwe-loopback:

1. Setha kabusha isistimu.
   sys_reset_digital_analog
2. Bonisa imvamisa yewashi nesimo se-PHY.
   chkphy_isimo
3. Vula ukuhlolwa kwe-loopback yangaphakathi.
   vula_kuvuliwe
4. Bonisa imvamisa yewashi nesimo se-PHY. I-rx_clk isethelwe ku-312.5 MHz futhi
   rx_pcs_ready isethelwe ku-1.
   chkphy_isimo
5. Qala ijeneretha yephakethe.
   qala_pkt_gen
6. Misa ijeneretha yephakethe.
   yeka_pkt_gen
7. Review inani lamaphakethe adlulisiwe nawamukelwe.
   chkmac_stats
8. Vala ukuhlolwa kwangaphakathi kwe-loopback.
   luphu_cisha

Ukuhlolwa Kwe-Loopback Kwangaphandle
Qalisa lezi zinyathelo ukuze wenze ukuhlolwa kwe-loopback yangaphandle:

1. Setha kabusha isistimu.
   sys_reset_digital_analog
2. Bonisa imvamisa yewashi nesimo se-PHY. I-rx_clk isethelwe ku-312.5 MHz futhi
   I-rx_pcs_ready isethelwe ku-1. chkphy_status
3. Qala ijeneretha yephakethe.
   qala_pkt_gen
4. Misa ijeneretha yephakethe.
   yeka_pkt_gen
5. Review inani lamaphakethe adlulisiwe nawamukelwe.
   chkmac_stats

I-Low Latency E-Tile 40G Ethernet Design Example Registers

I-Low Latency E-Tile 40G Ethernet Hardware Design Example Bhalisa imephu
Iklelisa ububanzi berejista ebhalwe kumephu ye-hardware example. Ufinyelela lawa marejista ngemisebenzi ethi reg_read and reg_write kukhonsoli Yesistimu.

I-Word Offset	Uhlobo lokubhalisa
0x300-0x3FF	PHY amarejista
0x400-0x4FF	Irejista ye-TX MAC
0x500-0x5FF	Irejista ye-RX MAC
0x800-0x8FF	Irejista Yezibalo Zezibalo - isiqondiso se-TX
0x900-0x9FF	Irejista Yezibalo Zezibalo - isiqondiso se-RX
0x1000-1016	Iphakethe leKlayenti liyabhalisa

Packet Client Registers
Ungenza ngokwezifiso i-Low Latency E-Tile 40G Ethernet hardware design example ngokuhlela amarejista eklayenti.

Addr	Igama	Kancane	Incazelo	HW Setha Kabusha Inani	Ukufinyelela
0x1008	Lungiselela Usayizi Wephakethe	[29:0]	Cacisa usayizi wephakethe lokudlulisa ngamabhayithi. Lezi zingcezu zinokuncika kurejista ye-PKT_GEN_TX_CTRL. • Ibhithi [29:16]: Cacisa umkhawulo ongaphezulu wosayizi wephakethe ngamabhayithi. Lokhu kusebenza kuphela kumodi yokwengeza. • I-Bit [13:0]: - Ngemodi ehleliwe, lezi zingcezu zicacisa usayizi wephakethe lokudlulisa ngamabhayithi. - Ngemodi yokukhula, lezi zingcezu zicacisa amabhayithi akhuphukayo ephakethe.	0x25800040	RW
0x1009	Ukulawula Inombolo Yephakethe	[31:0]	Cacisa inani lamaphakethe azothunyelwa kusuka kujeneretha yephakethe.	0xA	RW
0x1010	I-PKT_GEN_TX_C TRL	[7:0]	• I-Bit [0]: Igciniwe. • Ibhithi [1]: I-packet generator vala ibhithi. Setha le bit enanini loku-1 ukuze uvale ijeneretha yephakethe, futhi uyisethe kabusha enanini elingu-0 ukuze uvule ijeneretha yephakethe. • I-Bit [2]: Igciniwe. • Ibhithi [3]: Inenani elingu-1 uma i-IP core ikumodi ye-loopback ye-MAC; inenani lika-0 uma iklayenti lephakethe lisebenzisa ijeneretha yephakethe.	0x6	RW
waqhubeka...

Addr	Igama	Kancane	Incazelo	HW Setha Kabusha Inani	Ukufinyelela
			• I-Bit [5:4]: — 00: Imodi engahleliwe — 01: Imodi ehleliwe — 10: Imodi yokwenyuka • I-Bit [6]: Misa le bithi ibe ngu-1 ukuze usebenzise irejista ye-0x1009 ukuze uvale ijeneretha yephakethe ngokusekelwe enanini elimisiwe lamaphakethe okufanele lidluliselwe. Uma kungenjalo, i-bit [1] yerejista ye-PKT_GEN_TX_CTRL isetshenziselwa ukuvala ijeneretha yephakethe. • Ibhithi [7]: — 1: Okokudlulisela ngaphandle kwegebe phakathi kwamaphakethe. — 0: Ngokudlulisela ngegebe elingahleliwe phakathi kwamaphakethe.
0x1011	Ikheli lendawo lingaphansi kwamabhithi angu-32	[31:0]	Ikheli lendawo (amabhithi angama-32 aphansi)	0x56780ADD	RW
0x1012	Ikheli okuyiwa kulo elingaphezulu kwamabhithi ayi-16	[15:0]	Ikheli lendawo (amabhithi angu-16 aphezulu)	0x1234	RW
0x1013	Ikheli lomthombo lingaphansi kwamabhithi angama-32	[31:0]	Ikheli lomthombo (amabhithi angama-32 aphansi)	0x43210ADD	RW
0x1014	Ikheli lomthombo elingaphezulu kwamabhithi ayi-16	[15:0]	Ikheli lomthombo (amabhithi angu-16 aphezulu)	0x8765	RW
0x1016	PKT_CL_LOOPB ACK_RESET	[0]	Ukusetha kabusha i-loopback ye-MAC. Misa kunani elingu-1 ukuze usethe kabusha i-ex yokuklamaampkanye ne-MAC loopback.	1 b0	RW

Ulwazi Oluhlobene
I-Low Latency E-Tile 40G Ethernet Control and Status Register Izincazelo Ichaza i-Low Latency E-Tile 40G Ethernet IP core register.

I-Design Example Interface Signals
I-Low Latency E-Tile 40G Ethernet testbench iyaziqukatha ngokwayo futhi ayidingi ukuthi ushayele noma imaphi amasiginali okokufaka.

I-Low Latency E-Tile 40G Ethernet Hardware Design Example Interface Signals

Isiginali	Isiqondiso	Amazwana
cl50	Okokufaka	Leli washi lishayelwa i-oscillator yebhodi. • Shayela ngo-50 MHz ebhodini le-Intel Stratix 10. • Shayela ngo-100 MHz ebhodini le-Intel Agilex. I-hardware design exampihambisa leli washi kokokufaka kwe-IOPLL kudivayisi futhi ilungiselela i-IOPLL ukushayela iwashi elingu-100 MHz ngaphakathi.
clk_ref	Okokufaka	Shayela ku-156.25 MHz.
waqhubeka...

Isiginali	Isiqondiso	Amazwana
cpu_resetn	Okokufaka	Isetha kabusha i-IP core. Okuphansi okusebenzayo. Ishayela ukusetha kabusha kanzima komhlaba wonke i-csr_reset_n ku-IP core.
i-tx_serial[3:0]	Okukhiphayo	I-Transceiver PHY yomkhiqizo wedatha ye-serial.
rx_serial[3:0]	Okokufaka	I-Transceiver PHY idatha yesiriyeli yokufaka.
umsebenzisi_uholwa[7:0]	Okukhiphayo	Izimpawu zesimo. I-hardware design example ixhuma lezi zingcezu ukushayela ama-LED ebhodini eliqondiwe. Amabhithi angawodwana abonisa amanani esignali alandelayo nokuziphatha kwewashi: • [0]: Isiginali yokusetha kabusha eyinhloko kumongo we-IP • [1]: Inguqulo ehlukanisiwe ye-clk_ref • [2]: Inguqulo ehlukanisiwe ye-clk50 • [3]: Inguqulo ehlukanisiwe yewashi lesimo le-100 MHz • [4]: ​​tx_lanes_stable • [5]: rx_block_lock • [6]: rx_am_lock • [7]: rx_pcs_ready

Ulwazi Oluhlobene
Ukusebenzelana Nezincazelo Zesiginali Inikeza izincazelo ezinemininingwane yamasiginali ayinhloko we-IP ye-Low Latency E-Tile 40G Ethernet IP kanye nezindawo eziyingxenye yazo.

I-Low Latency E-Tile 40G Ethernet Intel FPGA IP Archives
Uma inguqulo ye-IP eyinhloko ingekho ohlwini, umhlahlandlela womsebenzisi wenguqulo yangaphambilini ye-IP iyasebenza.

Inguqulo ye-Intel Quartus Prime	Inguqulo ye-IP Core	Umhlahlandlela Womsebenzisi
20.1	19.1.0	I-Low Latency E-Tile 40G Ethernet Design Example Umhlahlandlela Womsebenzisi

Umlando Wokubuyekeza Idokhumenti Ye-Low Latency E-tile 40G Ethernet Design Example Umhlahlandlela Womsebenzisi

Inguqulo Yedokhumenti	Inguqulo ye-Intel Quartus Prime	Inguqulo ye-IP	Izinguquko
2020.06.22	20.2	20.0.0	Kwengezwe ukusekelwa kwedivayisi kwamadivayisi we-Intel Agilex.
2020.04.13	20.1	19.1.0	Ukukhishwa Kwasekuqaleni.

Inkampani ye-Intel Wonke Amalungelo Agodliwe. I-Intel, ilogo ye-Intel, nezinye izimpawu ze-Intel yizimpawu zokuthengisa ze-Intel Corporation noma izinkampani ezingaphansi kwayo. I-Intel iqinisekisa ukusebenza kwe-FPGA yayo kanye nemikhiqizo yesemiconductor ekucacisweni kwamanje ngokuvumelana newaranti evamile ye-Intel, kodwa igodla ilungelo lokwenza izinguquko kunoma imiphi imikhiqizo namasevisi nganoma yisiphi isikhathi ngaphandle kwesaziso. I-Intel ayithathi mthwalo noma isikweletu esivele ngenxa yesicelo noma ukusetshenziswa kwanoma yiluphi ulwazi, umkhiqizo, noma isevisi echazwe lapha ngaphandle kwalapho okuvunyelwene ngakho ngokubhaliwe yi-Intel. Amakhasimende e-Intel ayelulekwa ukuthi athole inguqulo yakamuva yokucaciswa kwedivayisi ngaphambi kokuthembela kunoma yiluphi ulwazi olushicilelwe nangaphambi kokufaka ama-oda emikhiqizo noma amasevisi. Amanye amagama namabhrendi angafunwa njengempahla yabanye.

Amadokhumenti / Izinsiza

i-intel Low Latency E-Tile 40G Ethernet Intel FPGA IP Design Example [pdf] Umhlahlandlela Womsebenzisi I-Low Latency E-Tile 40G Ethernet Intel FPGA IP Design Example, I-Low Latency, i-E-Tile 40G Ethernet Intel FPGA IP Design Example, Intel FPGA IP Design Example, IP Design Example

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