I-F-Tile DisplayPort FPGA IP Design Example
Umhlahlandlela Womsebenzisi
I-F-Tile DisplayPort FPGA IP Design Example
Ibuyekezelwe i-Intel® Quartus® Prime Design Suite: 22.2 IP Version: 21.0.1
I-DisplayPort Intel FPGA IP Design Exampne-Quick Start Guide
Amadivayisi e-DisplayPort Intel® F-tile afaka ibhentshi elilingisayo kanye nedizayini yezingxenyekazi zekhompuyutha esekela ukuhlanganiswa nokuhlolwa kwezingxenyekazi zekhompuyutha I-FPGA IP design ex.ampI-Intel Agilex™
I-DisplayPort Intel FPGA IP inikeza i-ex design elandelayoampkancane:
- I-DisplayPort SST parallel loopback ngaphandle kwemojuli ye-Pixel Clock Recovery (PCR).
- I-DisplayPort SST parallel loopback ene-AXIS Video Interface
Uma udala i-ex designample, umhleli wepharamitha udala ngokuzenzakalelayo i filekudingekile ukulingisa, ukuhlanganisa, nokuhlola idizayini kuhadiwe.
Umfanekiso 1. Ukuthuthukiswa Stages
Ulwazi Oluhlobene
- I-DisplayPort Intel FPGA IP User Guide
- Ithuthela ku-Intel Quartus Prime Pro Edition
Inkampani ye-Intel Wonke Amalungelo Agodliwe. I-Intel, ilogo ye-Intel, nezinye izimpawu ze-Intel yizimpawu zokuthengisa ze-Intel Corporation noma izinkampani ezingaphansi kwayo. I-Intel iqinisekisa ukusebenza kwe-FPGA yayo kanye nemikhiqizo ye-semiconductor ekucacisweni kwamanje ngokuvumelana newaranti evamile ye-Intel, kodwa igodla ilungelo lokwenza izinguquko kunoma imiphi imikhiqizo namasevisi nganoma yisiphi isikhathi ngaphandle kwesaziso. I-Intel ayithathi mthwalo noma isikweletu esivele ngenxa yesicelo noma ukusetshenziswa kwanoma yiluphi ulwazi, umkhiqizo, noma isevisi echazwe lapha ngaphandle kwalapho okuvunyelwene ngakho ngokubhaliwe yi-Intel. Amakhasimende e-Intel ayelulekwa ukuthi athole inguqulo yakamuva yokucaciswa kwedivayisi ngaphambi kokuthembela kunoma yiluphi ulwazi olushicilelwe nangaphambi kokufaka ama-oda emikhiqizo noma amasevisi.
*Amanye amagama namabhrendi angafunwa njengempahla yabanye.
I-ISO 9001:2015 Ibhalisiwe
1.1. Ukwakheka Kwemibhalo
Umfanekiso 2. Ukwakheka Kwemibhalo
Ithebula 1. Idizayini Example Components
| Amafolda | Files |
| i-rtl/core | dp_core.ip |
| dp_rx. ip | |
| dp_tx. ip | |
| rtl/rx_phy | dp_gxb_rx/ ((ibhulokhi yokwakha ye-DP PMA UX) |
| dp_rx_data_fifo . ip | |
| rx_phezulu_phy . sv | |
| rtl/tx_phy | dp_gxb_rx/ ((ibhulokhi yokwakha ye-DP PMA UX) |
| dp_tx_data_fifo.ip | |
| dp_tx_data_fifo.ip |
1.2. Izingxenyekazi zekhompuyutha nezidingo zeSoftware
I-Intel isebenzisa izingxenyekazi zekhompuyutha ezilandelayo nesofthiwe ukuhlola i-ex yedizayiniample:
Izingxenyekazi zekhompuyutha
- I-Intel Agilex I-Series Development Kit
- I-DisplayPort Source GPU
- I-DisplayPort Sink (Monitor)
- I-Bitec DisplayPort FMC ikhadi lendodakazi Ukubuyekezwa 8C
- Izintambo ze-DisplayPort
Isofthiwe
- Intel Quartus® Prime
- Synopsy* VCS Simulator
1.3. Ikhiqiza Umklamo
Sebenzisa isihleli sepharamitha ye-DisplayPort Intel FPGA IP ku-Intel Quartus Prime software ukuze ukhiqize i-ex yomklamoample.
Umfanekiso 3. Ukukhiqiza Ukugeleza Komklamo
- Khetha Amathuluzi ➤ Ikhathalogi ye-IP, bese ukhetha i-Intel Agilex F-tile njengomndeni wedivayisi okuqondiswe kuyo.
Qaphela: Umklamo exampi-le isekela kuphela amadivayisi we-Intel Agilex F-tile. - Kukhathalogi ye-IP, thola bese uchofoza kabili i-DisplayPort Intel FPGA IP. Iwindi le-New IP Variation liyavela.
- Cacisa igama lezinga eliphezulu lokuhluka kwakho kwe-IP yangokwezifiso. Umhleli wepharamitha ugcina izilungiselelo zokuhlukahluka kwe-IP ku-a file okuthiwa .ip.
- Khetha idivayisi ye-Intel Agilex F-tile kunkambu yeDivayisi, noma gcina ukukhethwa kwedivayisi yesofthiwe ye-Intel Quartus Prime.
- Chofoza okuthi KULUNGILE. Umhleli wepharamitha uyavela.
- Lungiselela imingcele oyifunayo yakho kokubili i-TX ne-RX.
- Ngaphansi Komklamo Exampkuthebhu, khetha i-DisplayPort SST Parallel Loopback Ngaphandle kwe-PCR.
- Khetha Ukulingisa ukuze ukhiqize ibhentshi lokuhlola, bese ukhetha i-Synthesis ukuze ukhiqize i-ex ye-hardware designample. Kufanele ukhethe okungenani eyodwa yalezi zinketho ukuze ukhiqize i-ex yokuklamaample files. Uma ukhetha kokubili, isikhathi sokukhiqiza siba side.
- Ngekhithi Yokuthuthukiswa Kwethagethi, khetha i-Intel Agilex I-Series SOC Development Kit. Lokhu kubangela idivayisi eqondiwe ekhethwe esinyathelweni sesi-4 ukuthi ishintshe ukuze ifane nedivayisi kukhithi yokuthuthukisa. Nge-Intel Agilex I-Series SOC Development Kit, idivayisi ezenzakalelayo yi-AGIB027R31B1E2VR0.
- Chofoza okuthi Khiqiza Isibample Design.
1.4. Ukulingisa Umklamo
I-DisplayPort Intel FPGA IP design exampI-le testbench ilingisa ukwakheka kwe-serial loopback kusuka kusibonelo se-TX kuya kusibonelo se-RX. Imojuli yangaphakathi yokukhiqiza iphethini yevidiyo ishayela isibonelo se-DisplayPort TX futhi okokukhiphayo kwevidiyo okuyisibonelo se-RX kuxhumeka kuzihloli ze-CRC kubhentshi lokuhlola.
Umfanekiso 4. Ukugeleza Kokulingisa Komklamo
- Iya kufolda yesilingisi se-Synopsys bese ukhetha i-VCS.
- Qalisa isikripthi sokulingisa.
Umthombo vcs_sim.sh - Iskripthi senza i-Quartus TLG, sihlanganise futhi sisebenzise ibhentshi lokuhlola kusifanisi.
- Hlaziya umphumela.
Ukulingisa okuyimpumelelo kugcina ngokuqhathanisa Umthombo kanye neSink SRC.
1.5. Ukuhlanganisa Nokuhlola Idizayini
Umfanekiso 5. Ukuhlanganisa kanye Nokulingisa Umklamo
Ukuhlanganisa nokusebenzisa ukuhlolwa kokubonisa ku-hardware example design, landela lezi zinyathelo:
- Qinisekisa i-hardware exampi-design generation iqedile.
- Yethula isofthiwe ye-Intel Quartus Prime Pro Edition futhi uvule / quartus/agi_dp_demo.qpf.
- Chofoza Ukucubungula ➤ Qala Ukuhlanganisa.
- Ngemva kokuhlanganiswa ngempumelelo, isofthiwe ye-Intel Quartus Prime Pro Edition ikhiqiza i-.sof file ohlwini lwakho lwemibhalo olushilo.
- Xhuma isixhumi se-DisplayPort RX ekhadini lendodakazi le-Bitec emthonjeni wangaphandle we-DisplayPort, njengekhadi lezithombe ku-PC.
- Xhuma isixhumi se-DisplayPort TX ekhadini lendodakazi le-Bitec kusisetshenziswa sikasinki se-DisplayPort, njengesihlaziyo sevidiyo noma imonitha ye-PC.
- Qinisekisa ukuthi wonke amaswishi ebhodini lokuthuthukisa asesimweni sokuzenzakalelayo.
- Lungiselela idivayisi ye-Intel Agilex F-Tile ekhethiwe ebhodini lokuthuthukisa usebenzisa i-.sof ekhiqiziwe file (Amathuluzi ➤ Umklami ).
- Idivayisi kasinki ye-DisplayPort ibonisa ividiyo ekhiqizwe emthonjeni wevidiyo.
Ulwazi Oluhlobene
Intel Agilex I-Series FPGA Development Kit User Guide/
1.5.1. Ikhiqiza kabusha i-ELF File
Ngokuzenzakalelayo, i-ELF file ikhiqizwa uma ukhiqiza i-ex dynamic designample.
Nokho, kwezinye izimo, udinga ukuvuselela i-ELF file uma ushintsha isoftware file noma ukhiqize kabusha i-dp_core.qsys file. Ikhiqiza kabusha i-dp_core.qsys file ibuyekeza i-.sopcinfo file, okudinga ukuthi ukhiqize kabusha i-ELF file.
- Iya ku /software bese uhlela ikhodi uma kunesidingo.
- Iya ku /script bese ukhiphe iskripthi sokwakha esilandelayo: umthombo build_sw.sh
• Ku-Windows, sesha futhi uvule i-Nios II Command Shell. Ku-Nios II Command Shell, iya ku /script bese usebenzisa umthombo build_sw.sh.
Qaphela: Ukuze usebenzise iskripthi sokwakha ku-Windows 10, isistimu yakho idinga i-Windows Subsystems ye-Linux (WSL). Ukuze uthole ulwazi olwengeziwe mayelana nezinyathelo zokufaka i-WSL, bheka I-Nios II Software Developer Handbook.
• Ku-Linux, vula i-Platform Designer, bese uvule Amathuluzi ➤ I-Nios II Command Shell. Ku-Nios II Command Shell, iya ku /script bese usebenzisa umthombo build_sw.sh. - Qiniseka ukuthi i-.elf file ikhiqizwa ku /software/ dp_demo.
- Landa i-.elf eyenziwe file ku-FPGA ngaphandle kokubuyisela i-.sof file ngokusebenzisa umbhalo olandelayo: nios2-download /software/dp_demo/*.elf
- Cindezela inkinobho yokusetha kabusha ebhodini le-FPGA ukuze isofthiwe entsha isebenze.
1.6. I-DisplayPort Intel FPGA IP Design Example Amapharamitha
Ithebula 2. I-DisplayPort Intel FPGA IP Design Example QSF umkhawulo we-Intel Agilex Ftile Device
| I-QSF Constraint |
Incazelo |
| set_global_assignment -igama VERILOG_MACRO “__DISPLAYPORT_support__=1” |
Kusukela ku-Quartus 22.2 kuya phambili, lesi sivimbelo se-QSF siyadingeka ukuze unike amandla ukugeleza kwe-DisplayPort yangokwezifiso ye-SRC (Soft Reset Controller) |
Ithebula 3. I-DisplayPort Intel FPGA IP Design Example Amapharamitha we-Intel Agilex F-tile Device
| Ipharamitha | Inani | Incazelo |
| Idizayini Etholakalayo Example | ||
| Khetha i-Design | •Lutho •I-DisplayPort SST Parallel Loopback ngaphandle kwe-PCR •I-DisplayPort SST Parallel Loopback ene-AXIS Video Interface |
Khetha i-ex designample ezokwenziwa. •Lutho: Ayikho i-ex yedizayiniampi-le iyatholakala ekukhethweni kwepharamitha yamanje. •I-DisplayPort SST Parallel Loopback ngaphandle kwe-PCR: Lo mklamo exampI-le ibonisa i-loopback ehambisanayo isuka kusinki ye-DisplayPort iye emthonjeni we-DisplayPort ngaphandle kwemojuli ye-Pixel Clock Recovery (PCR) lapho uvula ipharamitha yokunika amandla Imbobo yesithombe sokufaka ividiyo. •I-DisplayPort SST Parallel Loopback ene-AXIS Video Interface: Lo mklamo exampI-le ibonisa i-loopback ehambisanayo isuka kusinki ye-DisplayPort iye emthonjeni we-DisplayPort ene-interface ye-AXIS Video lapho Ukunika amandla Iphrothokholi Yedatha Yevidiyo Esebenzayo kusethelwe ku-AXIS-VVP Egcwele. |
| I-Design Example Files | ||
| Ukulingisa | Khanyisa cisha | Vula le nketho ukuze ukhiqize okudingekayo files okwebhentshi lokulinganisa lokulingisa. |
| I-synthesis | Khanyisa cisha | Vula le nketho ukuze ukhiqize okudingekayo files yokuhlanganiswa kwe-Intel Quartus Prime kanye nokwakhiwa kwehadiwe. |
| Kwenziwe Ifomethi ye-HDL | ||
| Khiqiza File Ifomethi | I-Verilog, i-VHDL | Khetha ifomethi oyithandayo ye-HDL ye-ex yedizayini ekhiqiziweample filesetha. Qaphela: Le nketho inquma kuphela ifomethi yezinga eliphezulu le-IP elikhiqiziwe files. Konke okunye files (isbample testbenches kanye nezinga eliphezulu files yokuboniswa kwezingxenyekazi zekhompyutha) zikufomethi ye-Verilog HDL. |
| Ikhithi Yokuthuthukisa Okuqondisiwe | ||
| Khetha Ibhodi | •Ayikho Ikhithi Yokuthuthukisa •Intel Agilex I-Series Ikhithi Yokuthuthukisa |
Khetha ibhodi ye-ex yedizayini eqondisiweample. |
| Ipharamitha | Inani | Incazelo |
| •Ayikho Ikhithi Yokuthuthukisa: Le nketho ayifaki zonke izici zehadiwe ye-ex yedizayiniample. I-P core isetha yonke imisebenzi yephinikhodi kumaphinikhodi abonakalayo. •I-Intel Agilex I-Series FPGA Development Kit: Le nketho ikhetha ngokuzenzakalela idivayisi eqondiwe yephrojekthi ukuze ifane nedivayisi kule khithi yokuthuthukisa. Ungashintsha idivayisi eqondiwe usebenzisa ipharamitha yedivayisi eqondisiwe uma ukubuyekezwa kwebhodi lakho kunokwehlukile kwedivayisi. I-IP core isetha yonke imisebenzi yephinikhodi ngokuya ngekhithi yokuthuthukisa. Qaphela: Idizayini Yokuqala Exampi-le ayiqinisekiswanga ngokusebenza kwehadiwe kulokhu kukhishwa kwe-Quartus. •Ikhithi Yokuthuthukisa Ngokwezifiso: Le nketho ivumela i-ex yedizayiniample izohlolwa kukhithi yokuthuthukisa yenkampani yangaphandle nge-Intel FPGA. Ungase udinge ukusetha imisebenzi yephinikhodi uwedwa. |
||
| Idivayisi eqondiwe | ||
| Shintsha Idivayisi Eqondisiwe | Khanyisa cisha | Vula le nketho bese ukhetha ukwahluka kwedivayisi okuncamelayo kwekhithi yokuthuthukisa. |
I-Parallel Loopback Design ExampLes
I-DisplayPort Intel FPGA IP design exampLes sibonise i-loopback ehambisanayo kusukela kusibonelo se-DisplayPort RX kuya kusibonelo se-DisplayPort TX ngaphandle kwemojula ye-Pixel Clock Recovery (PCR).
Ithebula 4. I-DisplayPort Intel FPGA IP Design Example ye-Intel Agilex F-tile Device
| I-Design Example | Ukuqokwa | Isilinganiso Sedatha | Imodi Yesiteshi | Uhlobo lwe-Loopback |
| I-DisplayPort SST parallel loopback ngaphandle kwe-PCR | I-DisplayPort SST | I-RBR, HRB, HRB2, HBR3 | I-Simplex | Ihambisana ngaphandle kwe-PCR |
| I-DisplayPort SST parallel loopback ene-AXIS Video Interface | I-DisplayPort SST | I-RBR, HRB, HRB2, HBR3 | I-Simplex | Ihambisana ne-AXIS Video Interface |
2.1. I-Intel Agilex F-tile DisplayPort SST Parallel Loopback Design Izici
I-SST parallel loopback design exampfuthi sibonise ukuhanjiswa kokusakaza okukodwa kwevidiyo kusuka kusinki we-DisplayPort kuya emthonjeni we-DisplayPort.
Inkampani ye-Intel Wonke Amalungelo Agodliwe. I-Intel, ilogo ye-Intel, nezinye izimpawu ze-Intel yizimpawu zokuthengisa ze-Intel Corporation noma izinkampani ezingaphansi kwayo. I-Intel iqinisekisa ukusebenza kwe-FPGA yayo kanye nemikhiqizo yesemiconductor ekucacisweni kwamanje ngokuvumelana newaranti evamile ye-Intel, kodwa igodla ilungelo lokwenza izinguquko kunoma imiphi imikhiqizo namasevisi nganoma yisiphi isikhathi ngaphandle kwesaziso. I-Intel ayithathi mthwalo noma isikweletu esivele ngenxa yesicelo noma ukusetshenziswa kwanoma yiluphi ulwazi, umkhiqizo, noma isevisi echazwe lapha ngaphandle kwalapho okuvunyelwene ngakho ngokubhaliwe yi-Intel. Amakhasimende e-Intel ayelulekwa ukuthi athole inguqulo yakamuva yokucaciswa kwedivayisi ngaphambi kokuthembela kunoma yiluphi ulwazi olushicilelwe nangaphambi kokufaka ama-oda emikhiqizo noma amasevisi. *Amanye amagama namabhrendi angafunwa njengempahla yabanye.
I-ISO 9001:2015 Ibhalisiwe
Umfanekiso 6. I-Intel Agilex F-tile DisplayPort SST Parallel Loopback ngaphandle kwe-PCR
- Kulokhu okuhlukile, ipharamitha yomthombo we-DisplayPort, TX_SUPPORT_IM_ENABLE, iyavulwa futhi kusetshenziswa okusetshenziswa kubonwa isithombe sevidiyo.
- Isinki se-DisplayPort sithola ividiyo kanye noma ukusakazwa komsindo okuvela emthonjeni wamavidiyo wangaphandle njenge-GPU futhi iyihlukanise ibe isixhumi esibonakalayo sevidiyo esihambisanayo.
- I-DisplayPort sinki ephumayo yevidiyo ishayela ngokuqondile isixhumi esibonakalayo sevidiyo yomthombo we-DisplayPort futhi ibhale ngekhodi kusixhumanisi esikhulu se-DisplayPort ngaphambi kokuyidlulisela kusiqaphi.
- I-IOPLL ishayela womabili usinki we-DisplayPort kanye namawashi evidiyo yomthombo ngefrikhwensi engashintshi.
- Uma usinki we-DisplayPort kanye nepharamitha ye-MAX_LINK_RATE yomthombo ilungiselelwe ukuthi ibe yi-HBR3 futhi i-PIXELS_PER_CLOCK ilungiselelwe ukuthi ibe yi-Quad, iwashi levidiyo lisebenza ku-300 MHz ukuze lisekele izinga lamaphikiseli angu-8Kp30 (1188/4 = 297 MHz).
Umfanekiso 7. I-Intel Agilex F-tile DisplayPort SST Parallel Loopback enevidiyo ye-AXIS Isixhumi esibonakalayo
- Kulokhu okuhlukile, umthombo we-DisplayPort kanye nepharamitha yokucwila, khetha i-AXIS-VVP IGCWELE kokuthi VULA AMAPROTOCOLS EDATHA YEVIDIYO ESEBENZAYO ukuze unike amandla isixhumi esibonakalayo sedatha ye-Axis Video.
- Isinki se-DisplayPort sithola ividiyo kanye noma ukusakazwa komsindo okuvela emthonjeni wamavidiyo wangaphandle njenge-GPU futhi iyihlukanise ibe isixhumi esibonakalayo sevidiyo esihambisanayo.
- I-DisplayPort Sink iguqula ukusakazwa kwedatha yevidiyo ibe idatha yevidiyo ye-eksisi futhi ishayela isixhumi esibonakalayo sedatha ye-DisplayPort yomthombo wedatha ye-eksisi nge-VVP Video Frame Buffer. I-DisplayPort Source iguqula idatha yevidiyo ye-axis ibe isixhumanisi esikhulu se-DisplayPort ngaphambi kokuyidlulisela kusiqaphi.
- Kulokhu okuhlukile komklamo, kunamawashi evidiyo amathathu ayinhloko, okuyi-rx/tx_axi4s_clk, rx_vid_clk, kanye ne-tx_vid_clk. I-axi4s_clk isebenza ngo-300 MHz kuwo womabili amamojula we-AXIS kokuthi Umthombo kanye Nosinki. rx_vid_clk runsDP Sink Video pipeline at 300 MHz (ukuze isekele noma yikuphi ukulungiswa kufika ku-8Kp30 4PIPs), kuyilapho i-tx_vid_clk isebenzisa ipayipi le-DP Source Video kumafrikhwensi ewashi lePixel langempela (elihlukaniswa ngama-PIP).
- Lokhu okuhlukile komklamo kulungiselela imvamisa ye-tx_vid_clk ngohlelo lwe-I2C ukuya ku-SI5391B OSC ebhodini lapho umklamo uthola iswishi ekulungisweni.
- Lokhu kwehluka kwedizayini kubonisa kuphela inani elinqunyiwe lezinqumo njengoba kuchazwe ngaphambilini kusofthiwe ye-DisplayPort, okungukuthi:
— 720p60, RGB
— 1080p60, RGB
— 4K30, RGB
— 4K60, RGB
2.2. Uhlelo Lokuvala
Uhlelo lwewashi lubonisa izizinda zewashi kumklamo we-DisplayPort Intel FPGA IP example.
Umfanekiso 8. Isikimu sewashi se-Intel Agilex F-tile DisplayPort Transceiver
Ithebula 5. Izimpawu Zohlelo Lokuvala
| Iwashi kumdwebo |
Incazelo |
| I-SysPLL ifaka kabusha | Iwashi lereferensi le-F-tile System PLL okungaba yinoma iyiphi ifrikhwensi yewashi ehlukaniseka nge-System PLL yaleyo frikhwensi yokuphumayo. Kulo mklamo example, system_pll_clk_link kanye ne-rx/tx refclk_link yabelana nge-150 MHz SysPLL refclk efanayo. |
| Iwashi kumdwebo | Incazelo |
| Kumelwe kube iwashi eligijima lamahhala elixhunywe kwiphinikhodi yereferensi ye-transceiver ezinikele embobeni yewashi yokufaka ye-Reference kanye ne-System PLL Clocks IP, ngaphambi kokuxhuma imbobo yokukhiphayo ehambisanayo ne-DisplayPort Phy Top. Qaphela: Lesi sibonelo somklamoample, lungiselela isilawuli sewashi i-GUI Si5391A OUT6 ukuya ku-150 MHz. |
|
| system pll clk isixhumanisi | Ubuncane bemvamisa yokuphuma kweSistimu ye-PLL ukusekela sonke isilinganiso se-DisplayPort ngu-320 MHz. Lo mklamo exampI-le isebenzisa i-900 MHz (ephakeme kakhulu) yokuphumayo ukuze i-SysPLL refclk yabelwane ne-rx/tx refclk_link engu-150 MHz. |
| rx_cdr_refclk_link / tx_pll_refclk_link | I-Rx CDR ne-Tx PLL Link refclk egxilwe ku-150 MHz ukuze isekele lonke izinga ledatha ye-DisplayPort. |
| rx_ls_clkout / tx_ls_clkout | Iwashi lesivinini se-DisplayPort ukuze uwashi i-DisplayPort IP core. Imvamisa elilingana Nesilinganiso Sedatha hlukanisa ngobubanzi bedatha obuhambisanayo. Example: Imvamisa = isilinganiso sedatha / ububanzi bedatha = 8.1G (HBR3) / 40 bits = 202.5 MHz |
2.3. Ukulingisa Testbench
Ibhentshi lesivivinyo sokulingisa lilingisa i-DisplayPort TX serial loopback ku-RX.
Umfanekiso 9. I-DisplayPort Intel FPGA IP Simplex Mode Simulation Testbench Block Diagram
Ithebula 6. Izingxenye ze-Testbench
| Isakhi | Incazelo |
| Isiqophi Iphethini Generator | Le generator ikhiqiza amaphethini ebha yombala ongawalungiselela. Ungakwazi ukuhlukanisa isikhathi sefomethi yevidiyo. |
| I-Testbench Control | Leli bhulokhi lilawula ukulandelana kokuhlolwa kokulingisa futhi likhiqize amasiginali adingekayo e-TX core. Ibhulokhi yokulawula ye-testbench iphinda ifunde inani le-CRC kusuka kukho kokubili umthombo nosinki ukwenza iziqhathaniso. |
| I-RX Link Speed Clock Frequency Checker | Lesi sihloli siqinisekisa ukuthi i-transceiver ye-RX etholiwe imvamisa yewashi ifana yini nezinga ledatha elifiswayo. |
| I-TX Link Speed Clock Frequency Checker | Lesi sihloli siqinisekisa ukuthi i-TX transceiver etholiwe imvamisa yewashi ifana yini nenani ledatha elifunekayo. |
I-testbench yokulingisa yenza lokhu okulandelayo:
Ithebula 7. Ukuqinisekiswa kwe-Testbench
| Imibandela Yokuhlola |
Ukuqinisekisa |
| • Xhumanisa Ukuqeqeshwa Ngesilinganiso Sedatha HBR3 • Funda amarejista e-DPCD ukuze uhlole ukuthi Isimo se-DP siyasetha futhi sikala kokubili i-TX kanye ne-RX Link Speed frequency. |
Ihlanganisa i-Frequency Checker ukuze ilinganise isivinini sesixhumanisi ukuphuma kwefrikhwensi yewashi ku-TX kanye ne-RX transceiver. |
| • Sebenzisa iphethini yevidiyo usuka ku-TX uye ku-RX. • Qinisekisa i-CRC yakho kokubili umthombo nosinki ukuze uhlole ukuthi ayahambisana yini |
• Ixhuma ijeneretha yephethini yevidiyo kuMthombo we-DisplayPort ukuze ukhiqize iphethini yevidiyo. • Ukulawula kwe-Testbench ngokulandelayo kufunda kokubili i-Source ne-Sink CRC evela kumarejista e-DPTX kanye ne-DPRX futhi kuqhathaniswe ukuze kuqinisekiswe ukuthi womabili amanani e-CRC ayefana. Qaphela: Ukuze uqinisekise ukuthi i-CRC ibalwa, kufanele unike amandla ipharamitha yokuzenzakalelayo yokuhlola ye-CTS. |
Umlando Wokubuyekeza Idokhumenti we-F-Tile DisplayPort Intel FPGA IP Design Example Umhlahlandlela Womsebenzisi
| Inguqulo Yedokhumenti | Inguqulo ye-Intel Quartus Prime | Inguqulo ye-IP | Izinguquko |
| 2022.09.02 | 22. | 20.0.1 | •Kushintshwe isihloko sedokhumenti ukusuka ku-DisplayPort Intel Agilex F-Tile FPGA IP Design Example Umhlahlandlela Womsebenzisi ku-F-Tile DisplayPort Intel FPGA IP Design Example Umhlahlandlela Womsebenzisi. •Idizayini Yevidiyo ye-AXIS enikwe amandla Example okuhlukile. •Isuse idizayini Yesilinganiso Esiqinile futhi esikhundleni sayo kwafakwa i-Multi Rate Design Example. •Kukhishwe inothi ku-DisplayPort Intel FPGA IP Design Example Quick Start Guide ethi inguqulo yesoftware ye-Intel Quartus Prime 21.4 isekela kuphela i-Preliminary Design ExampLes. •Kushintshwe isibalo seSakhiwo sohla lwemibhalo ngesibalo esifanele. •Kwengezwe isigaba Ukukhiqiza kabusha i-ELF File ngaphansi Kokuhlanganisa Nokuhlola Idizayini. •Kubuyekezwe isigaba se-Hardware kanye Nezimfuneko Zesofthiwe ukuze kufakwe izingxenyekazi zekhompuyutha ezengeziwe izidingo. |
| 2021.12.13 | 21. | 20.0.0 | Ukukhishwa kokuqala. |
Inkampani ye-Intel Wonke Amalungelo Agodliwe. I-Intel, ilogo ye-Intel, nezinye izimpawu ze-Intel yizimpawu zokuthengisa ze-Intel Corporation noma izinkampani ezingaphansi kwayo. I-Intel iqinisekisa ukusebenza kwe-FPGA yayo kanye nemikhiqizo ye-semiconductor ekucacisweni kwamanje ngokuvumelana newaranti evamile ye-Intel, kodwa igodla ilungelo lokwenza izinguquko kunoma imiphi imikhiqizo namasevisi nganoma yisiphi isikhathi ngaphandle kwesaziso. I-Intel ayithathi mthwalo noma isikweletu esivele ngenxa yesicelo noma ukusetshenziswa kwanoma yiluphi ulwazi, umkhiqizo, noma isevisi echazwe lapha ngaphandle kwalapho okuvunyelwene ngakho ngokubhaliwe yi-Intel. Amakhasimende e-Intel ayelulekwa ukuthi athole inguqulo yakamuva yokucaciswa kwedivayisi ngaphambi kokuthembela kunoma yiluphi ulwazi olushicilelwe nangaphambi kokufaka ama-oda emikhiqizo noma amasevisi.
*Amanye amagama namabhrendi angafunwa njengempahla yabanye.
I-ISO 9001:2015 Ibhalisiwe
I-Online Version
Thumela Impendulo
UG-20347
Inombolo yepholisi: 709308
Inguqulo: 2022.09.02
Amadokhumenti / Izinsiza
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intel F-Tile DisplayPort FPGA IP Design Example [pdf] Umhlahlandlela Womsebenzisi I-F-Tile DisplayPort FPGA IP Design Example, F-Tile DisplayPort, DisplayPort, FPGA IP Design Example, IP Design Example, UG-20347, 709308 |
