Intel AN 837 Design Guidelines for HDMI FPGA IP
Imihlahlandlela yokudizayina ye-HDMI Intel® FPGA IP
Imihlahlandlela yokuklama ikusiza ukuthi usebenzise i-High-Definition Multimedia Interface (HDMI) Intel FPGA IPs usebenzisa amadivayisi e-FPGA. Le mihlahlandlela isiza imiklamo yebhodi ye-HDMI Intel® FPGA IP video interface.
- I-HDMI Intel FPGA IP User Guide
- I-AN 745: Imihlahlandlela yokudizayina ye-Intel FPGA DisplayPort Interface
I-HDMI Intel FPGA IP Design Guidelines
Isixhumi esibonakalayo se-HDMI Intel FPGA sinedatha ye-Transition Minimized Differential Differential (TMDS) namashaneli wewashi. I-interface iphinde iphathe i-Video Electronics Standards Association (VESA) Display Data Channel (DDC). Iziteshi ze-TMDS ziphethe ividiyo, umsindo, nedatha eyisizayo. I-DDC isuselwe kuphrothokholi ye-I2C. I-HDMI Intel FPGA IP core isebenzisa i-DDC ukufunda Idatha Eyengeziwe Yokuhlonza Isibonisi (EDID) kanye nokushintshanisa ukulungiselelwa nolwazi lwesimo phakathi komthombo we-HDMI nosinki.
I-HDMI Intel FPGA IP Board Design Amathiphu
Uma uklama uhlelo lwakho lwe-IP ye-HDMI Intel FPGA, cabangela amathiphu alandelayo wokuklama ibhodi.
- Ungasebenzisi izikhathi ezingaphezu kwezimbili ngomkhondo ngamunye futhi ugweme ngama-stubs
- Qondanisa i-impedance ehambisanayo nokubambezeleka kwesixhumi nokuhlanganisa ikhebula (100 ohm ±10%)
- Nciphisa i-inter-pair kanye ne-intra-pair skew ukuze uhlangabezane nemfuneko yesiginali ye-TMDS skew
- Gwema ukuhambisa ipheya ehlukile phezu kwegebe endizeni engaphansi
- Sebenzisa izinqubo zokuklama ezijwayelekile ze-PCB ezinesivinini esiphezulu
- Sebenzisa ama-level shifters ukuhlangabezana nemithetho kagesi kukho kokubili i-TX ne-RX
- Sebenzisa izintambo eziqinile, njengekhebuli ye-Cat2 ye-HDMI 2.0
Imidwebo yohlelo
Imidwebo yohlelo lwe-Bitec kuzixhumanisi ezinikeziwe ibonisa i-topology yamabhodi okuthuthukisa we-Intel FPGA. Ukusebenzisa i-HDMI 2.0 link topology kudinga ukuthi uhlangabezane nemithetho kagesi engu-3.3 V. Ukuze uhlangabezane nokuthobela okungu-3.3 V kumadivayisi we-Intel FPGA, udinga ukusebenzisa isishintshi sezinga. Sebenzisa i-DC-coupled redriver noma i-retimer njengesishintshi seleveli yesidluliseli nomamukeli.
Amadivayisi omthengisi wangaphandle yi-TMDS181 ne-TDP158RSBT, womabili asebenza kuzixhumanisi ezihlanganisiwe ze-DCcoupled. Udinga ukudonsa okufanele kolayini be-CEC ukuze uqinisekise ukusebenza lapho usebenzisana namanye amadivaysi okulawula okude. Imidwebo yeskimu ye-Bitec iqinisekisiwe nge-CTS. Isitifiketi, nokho, siqondene nezinga lomkhiqizo. Abaklami benkundla bayelulekwa ukuthi baqinisekise umkhiqizo wokugcina ukuze usebenze ngendlela efanele.
Ulwazi Oluhlobene
- I-Schematic Diagram ye-HSMC HDMI Ukubuyekezwa Kwekhadi Lendodakazi 8
- Umdwebo Owuhlelo we-FMC HDMI Ukubuyekezwa Kwekhadi Lendodakazi 11
- Umdwebo Owuhlelo we-FMC HDMI Ukubuyekezwa Kwekhadi Lendodakazi 6
I-Hot-Plug Detect (HPD)
Isignali ye-HPD incike kusiginali yamandla ye-+5V engenayo, ngokwesiboneloampNokho, iphinikhodi ye-HPD ingase igonyelwe kuphela uma isignali Yamandla +5V evela emthonjeni itholwa. Ukuze uxhumane ne-FPGA, udinga ukuhumusha isignali ye-5V HPD iye ku-FPGA I/O vol.tage level (VCCIO), usebenzisa i-voltagUmhumushi wezinga we-e ofana ne-TI TXB0102, ongenazo izinto zokuphikisa zokudonsa ezihlanganisiwe. Umthombo we-HDMI udinga ukuwisa isiginali ye-HPD ukuze ukwazi ukwehlukanisa ngokwethembekile phakathi kwesiginali ye-HPD entantayo kanye nevolumu ephezulu.tagisignali ye-HPD yezinga. I-HDMI usinki +5V Isiginali yamandla kufanele ihunyushwe ku-FPGA I/O voltage level (VCCIO). Isignali kumele yehliswe kancane ngesixhasi (10K) ukuze kuhlukaniswe isignali yamandla entantayo engu-+5V uma ingashayelwa umthombo we-HDMI. Umthombo we-HDMI +5V Isiginali yamandla inokuvikelwa kwamanje okungaphezu kuka-0.5A.
Isiteshi sedatha se-HDMI Intel FPGA IP Display (DDC)
I-HDMI Intel FPGA IP DDC isekelwe kumasiginali we-I2C (SCL ne-SDA) futhi idinga izimelambi zokudonsa. Ukuze uxhumane ne-Intel FPGA, udinga ukuhumusha izinga lesignali le-5V SCL kanye ne-SDA liye ku-FPGA I/O vol.tage level (VCCIO) usebenzisa i-voltagIsihumushi se-e, esifana ne-TI TXS0102 njengoba sisetshenziswa ekhadini lendodakazi le-Bitec HDMI 2.0. Idatha ye-TI TXS0102 voltagIdivayisi yesihumushi yeleveli ye-e ihlanganisa izinto eziphikisayo zokudonsa phezulu ukuze kungabikho ukumelana nokudonsa phezulu okudingekayo.
Umlando Wokubuyekeza Idokhumenti we-AN 837: Izinkombandlela Zokuklama ze-HDMI Intel FPGA IP
| Inguqulo Yedokhumenti | Izinguquko |
| 2019.01.28 |
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| Usuku | Inguqulo | Izinguquko |
| Januwari 2018 | 2018.01.22 | Ukukhishwa kokuqala.
Qaphela: Lo mbhalo uqukethe imihlahlandlela yokuklama ye-HDMI Intel FPGA eyasuswa ku-AN 745: Izinkombandlela Zokuklama ze-DisplayPort kanye ne-HDMI Interfaces futhi yaqanjwa kabusha ngokuthi AN 745: Iziqondiso Zokuklama ze-Intel FPGA DisplayPort Interface. |
Inkampani ye-Intel Wonke Amalungelo Agodliwe. I-Intel, ilogo ye-Intel, nezinye izimpawu ze-Intel yizimpawu zokuthengisa ze-Intel Corporation noma izinkampani ezingaphansi kwayo. I-Intel iqinisekisa ukusebenza kwe-FPGA yayo kanye nemikhiqizo ye-semiconductor ezicacisweni zamanje ngokuhambisana newaranti evamile ye-Intel kodwa igodla ilungelo lokwenza izinguquko kunoma imiphi imikhiqizo namasevisi nganoma yisiphi isikhathi ngaphandle kwesaziso. I-Intel ayithathi mthwalo noma isikweletu esivele ngenxa yesicelo noma ukusetshenziswa kwanoma yiluphi ulwazi, umkhiqizo, noma isevisi echazwe lapha ngaphandle kwalapho okuvunyelwene ngakho ngokubhaliwe yi-Intel. Amakhasimende e-Intel ayelulekwa ukuthi athole inguqulo yakamuva yokucaciswa kwedivayisi ngaphambi kokuthembela kunoma yiluphi ulwazi olushicilelwe nangaphambi kokufaka ama-oda emikhiqizo noma amasevisi.
Amanye amagama namabhrendi angafunwa njengempahla yabanye.
I-ID: 683677
Inguqulo: 2019-01-28
Amadokhumenti / Izinsiza
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Intel AN 837 Design Guidelines for HDMI FPGA IP [pdf] Umhlahlandlela Womsebenzisi AN 837 Design Guidelines for HDMI FPGA IP, AN 837, Design Guidelines for HDMI FPGA IP, Guidelines for HDMI FPGA IP, HDMI FPGA IP |
