Intel UG-20093 ModelSim FPGA Edition Ukulingisa

I-ModelSim* – I-Intel® FPGA Edition Simulation Quick-Start Intel® Quartus® Prime Pro Edition

Lo mbhalo ubonisa indlela yokulingisa umklamo we-Intel® Quartus® Prime Pro Edition ku-ModelSim* - isifanisi se-Intel FPGA Edition. Ukulingisa idizayini kuqinisekisa umklamo wakho ngaphambi kokuhlelwa kwedivayisi. Isoftware ye-Intel Quartus Prime ikhiqiza ukulingisa files yezifanisi ze-EDA ezisekelwayo ngesikhathi sokuhlanganiswa komklamo.
Umfanekiso 1. I-ModelSim - I-Intel FPGA Edition

Ukulingisa kwedizayini kuhlanganisa ukukhiqiza ukulingisa files, ukuhlanganisa amamodeli okulingisa, ukusebenzisa isifaniso, kanye viewngemiphumela. Izinyathelo ezilandelayo zichaza lokhu kugeleza:

1. Vula i-Example Design ekhasini 4
2. Cacisa Izilungiselelo Zethuluzi Le-EDA ekhasini lesi-4
3. Khiqiza Isifanekiso Seskripthi Sokusetha Isilingisi ekhasini lesi-5
4. Lungisa Iskripthi Sokusetha Isilingisi ekhasini lesi-6
5. Hlanganisa futhi Ulingise Umklamo ekhasini lesi-8
6. View I-Signal Waveforms ekhasini lesi-9
7. Engeza Amasignali Ekulingiseni ekhasini 11
8. Qalisa kabusha Ukulingisa ekhasini le-12
9. Lungisa iSimulation Testbench ekhasini 12

Vula i-Example Design

I-PLL_RAM exampi-le design ifaka phakathi ama-Intel FPGA IP cores ukukhombisa ukugeleza kokulingisa okuyisisekelo. Landa i-example design files bese uvula iphrojekthi ku-Intel Quartus Prime software.
Qaphela: Lokhu Quick-Start kudinga ukuqonda okuyisisekelo kwe-syntax yolimi lwezingxenyekazi zekhompuyutha kanye nokugeleza komklamo we-Intel Quartus Prime, njengoba i-Intel Quartus Prime Pro Edition Foundation Online Training ichaza.

1. Dawuniloda futhi uvule iziphu yomklamo we-Quartus_Pro_PLL_RAM.zip example.
2. Yethula isoftware ye-Intel Quartus Prime Pro Edition engu-19.4 noma eyakamuva.
3. Ukuvula i-example design project, chofoza File ➤ Vula iphrojekthi, khetha iphrojekthi ye-pll_ram.qpf file, bese uchofoza okuthi KULUNGILE.

Umfanekiso 2. pll_ram Project ku-Intel Quartus Prime Pro Edition

Cacisa Izilungiselelo Zethuluzi Le-EDA

Cacisa izilungiselelo zethuluzi le-EDA ukuze ukhiqize ukulingisa files yezifanisi ezisekelwayo.

1. Kuhlelo lwe-Intel Quartus Prime, chofoza Izabelo ➤ Izilungiselelo ➤ Izilungiselelo Zethuluzi Le-EDA.
2. Ngaphansi Kokulingisa, khetha i-ModelSim-Intel FPGA njengegama Lethuluzi. Gcina izilungiselelo ezimisiwe Zefomethi yohlu lwe-netlist oluphumayo kanye nohla lwemibhalo Lokukhiphayo.

Khiqiza Isifanekiso Sesikripthi Sokusetha Isilingisi

Imibhalo yokusetha isifanisi ikusiza ukuthi ulingise ama-IP cores ekwakhiweni kwakho. Landela lezi zinyathelo ukuze ukhiqize ithempulethi yokusetha yesifanisi esiqondene nomthengisi kumamojula we-IP ku-example design. Ungakwazi ke ukwenza lesi sifanekiso ngendlela oyifisayo ukuze uthole izinhloso zakho zokulingisa ezithile.

1. Ukuze uhlanganise umklamo, chofoza Ukucubungula ➤ Qala Ukuhlanganisa. Iwindi lemilayezo libonisa ukuthi ukuhlanganisa kuqediwe nini.
2. Chofoza Amathuluzi ➤ Khiqiza Iskripthi Sokusetha Isifanisi se-IP. Gcina uhla lwemibhalo oluzenzakalelayo Lokukhipha futhi Sebenzisa izindlela ezihlobene noma nini lapho kungenzeka khona ukulungiselelwa kombhalo wokusetha file. Isifanekiso sombhalo wokusetha sikhiqiza kuhla lwemibhalo olucacisayo.

Umfanekiso 3. Khiqiza Ibhokisi Lengxoxo Yengxoxo Yezikripthi Zesifanisi Se-IP

Lungisa Iskripthi Sokusetha Isilingisi

Lungisa iskripthi sokusetha sesifanisi esikhiqiziwe ukuze unike amandla imiyalo ethile elingisa ama-IP cores kuphrojekthi.

1. Kumhleli wombhalo, vula i-/PLL_RAM/mentor/msim_setup.tcl file.
2. Dala umbhalo omusha file negama mentor_example.do bese uyigcina kuhlu lwemibhalo /PLL_RAM/mentor/.
3. Ku-msim_setup.tcl file, kopisha ingxenye yekhodi efakwe ngaphakathi kwe-TOP-LEVEL TEMPLATE - BEGIN kanye ne-TOP-LEVEL TEMPLATE - END amazwana, bese unamathisele le khodi ku-mentor_ex entshaample.do file.
4. Ku-mentor_example.do file, susa iphawundi elilodwa (#) izinhlamvu ezandulele imigqa egqanyisiwe elandelayo ukuze unike amandla imiyalo yokuhlanganisa:

Umfanekiso 4. Ukungaphawuli Okugqanyisiwe Imiyalo Yokulingisa Kuskripthi

1. Shintshanisa imigqa elandelayo ku-mentor_exampiskripthi se-le.do:

Ithebula 1. Cacisa Amanani ku-mentor_example.do Script

Faka esikhundleni lo Layini	Ngalo Layini
setha i-QSYS_SIMDIR	../
i-vlog files>	vlog -vlog01compat -work work ../PLL_RAM.v vlog -vlog01compat -work work ../UP_COUNTER_IP/UP_COUNTER_IP.v vlog -vlog01compat -work work ../DOWN_COUNTER_IP/DOWN_COUNTER_IP.v vlog -vlog01compat -work work ../ClockPLL/ClockPLL.v vlog -vlog01compat -work work ../RAMhub/RAMhub.v vlog -vlog01compat -work work ../testbench_1.v
setha i-TOP_LEVEL_NAME	setha i-TOP_LEVEL_NAME tb
gijima -a	engeza igagasi * view isakhiwo view izimpawu zigijima - zonke

1. Londoloza /PLL_RAM/mentor/mentor_example.do file. Umfanekiso olandelayo ubonisa umeluleki_example.do file ngemva kokuqedwa kokubuyekezwa:

Umfanekiso 5. Kuqedwe Isikripthi Sokusetha Sezinga Eliphezulu Lokulingisa I-IP

Hlanganisa futhi Ulingise Idizayini

Qalisa i-mentor_ex yezinga eliphezuluample.do kusofthiwe ye-ModelSim - Intel FPGA Edition ukuze uhlanganise futhi ulingise umklamo wakho.

1. Yethula isofthiwe ye-ModelSim - Intel FPGA Edition. I-ModelSim - Intel FPGA Edition GUI ihlela izici zokulingiswa kwakho zibe amawindi namathebhu ahlukene.
2. Kusuka kunkomba yephrojekthi ye-PLL_RAM, vula i-testbench_1.v file. Ngokufanayo, vula umeluleki/umeluleki_example.do file.
3. Ukuze ubonise iwindi Lokulotshiweyo, chofoza View ➤ Okulotshiweyo. Ungafaka imiyalo ye-ModelSim - Intel FPGA Edition ngqo efasiteleni le-Transcript.
4. Thayipha umyalo olandelayo efasiteleni le-Transcript bese ucindezela u-Enter: do mentor_example.do

Idizayini ihlanganisa futhi ilingise, ngokuya ngezicaciso zakho ku-mentor_example.no script. Isibalo esilandelayo sibonisa i-ModelSim - Intel FPGA Edition simulator:

Umfanekiso 6. I-ModelSim - I-Intel FPGA Edition GUI

View Signal Waveforms

Landela lezi zinyathelo ukuze view amasignali ku-testbench_1.v sekulingisa i-waveform:

1. Chofoza iwindi le-Wave. I-waveform yokulingisa iphetha ngo-11030 ns, njengoba i-testbench icacisa. Iwindi le-Wave liklelisa amasiginali we-CLOCK, WE, OFFSET, RESET_N, kanye ne-RD_DATA.

Umfanekiso 7. ModelSim - Intel FPGA Edition Wave Window

1. Kuya view amasignali kumklamo wezinga eliphezulu we-pll_ram.v, chofoza ithebhu ye-Sim. Iwindi le-Sim livumelanisa nefasitela leZinto.

Umfanekiso 8. I-ModelSim - I-Intel FPGA Edition Sim and Objects Windows

1. Kuya view amasignali emojuli yezinga eliphezulu, nweba ifolda ye-tb kuthebhu ethi Izinto. Ngokufanayo, nweba ifolda ye-Test1. Iwindi Lezinto libonisa UP_module, DOWN_module, PLL_module, kanye namasignali emojula ye-RAM.
2. Ewindini le-Sim, chofoza imojula ngaphansi kwe-Test1 ukuze ubonise amasiginali wemojuli efasiteleni Lezinto.
3. View umtapo wokulingisa files efasiteleni leLabhulali.

Umfanekiso 9. I-ModelSim - Iwindi le-Intel FPGA Edition Library

Engeza Amasignali Ekulingiseni

Amasiginali we-CLOCK, WE, OFFSET, RESET_N, kanye ne-RD_DATA avela ngokuzenzakalelayo efasiteleni le-Wave ngoba umklamo wezinga eliphezulu uchaza lezi I/O. Ngaphezu kwalokho, ungakwazi ngokukhetha ukwengeza amasignali angaphakathi ekufanisweni.

1. Ewindini Lezinto, thola UP_module, DOWN_module, PLL_module, kanye ne-RAM_module.
2. Ewindini Lezinto, khetha i-RAM_module. Okokufaka kanye nokuphumayo kwemojuli kukhona
3. isibonisi.

Umfanekiso 10. Engeza Amasignali Ukuze Uzulise Iwindi

1. Ukwengeza amasiginali angaphakathi phakathi kwemojuli ye-RAM ephansi kanye nezimbobo ezimbili, chofoza kwesokudla okuthi rdaddress bese uchofoza okuthi Engeza i-Wave.
2. Ukwengeza amasiginali angaphakathi phakathi kwemojula ye-RAM ephezulu kanye nezimbobo ezimbili, chofoza kwesokudla i-wraddress bese uchofoza okuthi Engeza i-Wave. Kungenjalo, ungahudula futhi uwise lawa masiginali ukusuka efasiteleni Lezinto uye efasiteleni le-Wave.
3. Ukuze ukhiqize amagagasi amasignali amasha owangezayo, chofoza okuthi Lingisa ➤ Run ➤ Qhubeka.

Qalisa kabusha Ukulingisa

Kumelwe uqalise kabusha ukulingisa uma wenza izinguquko ekusetheni kokulingisa, njengokwengeza amasiginali efasiteleni le-Wave, noma ukulungisa i-testbench_1.v file. Landela lezi zinyathelo ukuze uqalise kabusha ukulingisa:

1. Kusifanisi se-ModelSim - Intel FPGA Edition, chofoza Lingisa ➤ Qala kabusha. Gcina izinketho ezizenzakalelayo bese uchofoza okuthi KULUNGILE. Lezi zinketho zisula amagagasi futhi ziqale kabusha isikhathi sokulingisa, kuyilapho kugcinwa amasiginali adingekayo nezilungiselelo.
   Qaphela: Kungenjalo, ungaphinda uqalise /PLL_RAM/mentor/mentor_exampiskripthi se-le.do sokuqalisa kabusha ukulingisa emugqeni womyalo.
2. Chofoza Lingisa ➤ Run ➤ Run -konke. I-testbench_1.v file ilingisa ngokuya ngemininingwane ye-testbench. Ukuze uqhubeke nokulingisa, chofoza Lingisa ➤ Run ➤ Qhubeka. Lo myalo uqhubeka nokulingisa uze uchofoze inkinobho ethi Misa.

Shintsha i-Simulation Testbench

I-testbench_1.v exampI-testbench ihlola kuphela isethi ethile yezimo namacala okuhlola. Ungakwazi ukuhlela ngokwakho i-testbench_1.v file ku-ModelSim - Intel FPGA Edition simulator ukuhlola amanye amacala nezimo:

1. Vula i-testbench_1.v file ku-ModelSim - i-Intel FPGA Edition simulator.
2. Chofoza kwesokudla ku-testbench_1.v file ukuze uqinisekise ukuthi file ayisethiwe kokuthi Funda Kuphela.
3. Faka futhi ulondoloze noma imaphi amapharamitha ebhentshi engeziwe ku-testbench_1.v file.
4. Ukuze wakhe ama-waveform ebhentshi lokuhlola olishintshayo, chofoza okuthi Lingisa ➤ Qala kabusha.
5. Chofoza Lingisa ➤ Run ➤ Run -konke.

I-ModelSim – I-Intel FPGA Edition yokulingisa Umlando Wokubuyekeza Okusheshayo

Inguqulo Yedokhumenti	Inguqulo ye-Intel Quartus Prime	Izinguquko
2019.12.30	19.4	• Izinyathelo ezibuyekeziwe nezithombe-skrini ze-Intel Quartus Prime Pro Edition 19.4. • Idizayini ebuyekeziwe isibample file isixhumanisi nokuqukethwe.
2018.09.25	18.0	Kulungiswe amaphutha e-syntax ku-mentor_example.do Script.
2018.05.07	18.0	Kususwe isinyathelo esingadingekile kusuka Qalisa Ukulingisa ku-Command Line inqubo.
2017.07.15	17.1	Ukukhishwa kokuqala.

Inkampani ye-Intel Wonke Amalungelo Agodliwe. I-Intel, ilogo ye-Intel, nezinye izimpawu ze-Intel yizimpawu zokuthengisa ze-Intel Corporation noma izinkampani ezingaphansi kwayo. I-Intel iqinisekisa ukusebenza kwe-FPGA yayo kanye nemikhiqizo ye-semiconductor ekucacisweni kwamanje ngokuvumelana newaranti evamile ye-Intel, kodwa igodla ilungelo lokwenza izinguquko kunoma imiphi imikhiqizo namasevisi nganoma yisiphi isikhathi ngaphandle kwesaziso. I-Intel ayithathi mthwalo noma isikweletu esivele ngenxa yesicelo noma ukusetshenziswa kwanoma yiluphi ulwazi, umkhiqizo, noma isevisi echazwe lapha ngaphandle kwalapho okuvunyelwene ngakho ngokubhaliwe yi-Intel. Amakhasimende e-Intel ayelulekwa ukuthi athole inguqulo yakamuva yokucaciswa kwedivayisi ngaphambi kokuthembela kunoma yiluphi ulwazi olushicilelwe nangaphambi kokufaka ama-oda emikhiqizo noma amasevisi.

• Amanye amagama namabhrendi angafunwa njengempahla yabanye.

Amadokhumenti / Izinsiza

Intel UG-20093 ModelSim FPGA Edition Ukulingisa [pdf] Umhlahlandlela Womsebenzisi UG-20093 ModelSim FPGA Edition Ukulingisa, UG-20093, ModelSim FPGA Edition Ukulingisa, FPGA Edition Ukulingisa, Edition Simulation

Izithenjwa

• Imaniwali yosebenzisayo