I-HDMI Arria 10 FPGA IP Design Example
Umhlahlandlela WomsebenzisiI-HDMI Intel® Arria 10 FPGA IP
I-Design Example Umhlahlandlela Womsebenzisi
Ibuyekezelwe i-Intel®Quartus®
I-Prime Design Suite: 22.4
Inguqulo ye-IP: 19.7.1

I-HDMI Intel® FPGA IP Design Example Quick Start Guide yamadivayisi e-Intel® Arria® 10

Amadivayisi e-HDMI Intel® 10 afaka ibhentshi lokuhlola elilingisayo kanye nedizayini yezingxenyekazi zekhompuyutha esekela ukuhlanganiswa nokuhlolwa kwehadiwe.
I-FPGA IP design example ye-Intel Arria®
I-HDMI Intel FPGA IP inikeza i-ex design elandelayoampkancane:

• Idizayini yokudlulisa kabusha i-HDMI 2.1 RX-TX enemodi yesilinganiso esingaguquki (FRL) enikwe amandla
• Idizayini yokudlulisa kabusha i-HDMI 2.0 RX-TX enemodi ye-FRL ivaliwe
• Idizayini ye-HDCP phezu kwe-HDMI 2.0

Qaphela: Isici se-HDCP asifakiwe kusofthiwe ye-Intel® Quartus Prime Pro Edition.
Ukuze ufinyelele isici se-HDCP, xhumana ne-Intel ku- https://www.intel.com/content/www/us/en/broadcast/products/programmable/applications/connectivity-solutions.html.
Uma udala i-ex designample, umhleli wepharamitha udala ngokuzenzakalelayo i filekudingekile ukulingisa, ukuhlanganisa, nokuhlola idizayini kuhadiwe.
Umfanekiso 1. Izinyathelo ZokuthuthukiswaUlwazi Oluhlobene
I-HDMI Intel FPGA IP User Guide
1.1. Ikhiqiza Umklamo
Sebenzisa isihleli sepharamitha ye-HDMI Intel FPGA IP kusofthiwe ye-Intel Quartus Prime ukuze ukhiqize i-ex yedizayiniampLes. Inkampani ye-Intel Wonke Amalungelo Agodliwe. I-Intel, ilogo ye-Intel, nezinye izimpawu ze-Intel yizimpawu zokuthengisa ze-Intel Corporation noma izinkampani ezingaphansi kwayo. I-Intel iqinisekisa ukusebenza kwe-FPGA yayo kanye nemikhiqizo ye-semiconductor ekucacisweni kwamanje ngokuvumelana newaranti evamile ye-Intel, kodwa igodla ilungelo lokwenza izinguquko kunoma imiphi imikhiqizo namasevisi nganoma yisiphi isikhathi ngaphandle kwesaziso. I-Intel ayithathi mthwalo noma isikweletu esivele ngenxa yesicelo noma ukusetshenziswa kwanoma yiluphi ulwazi, umkhiqizo, noma isevisi echazwe lapha ngaphandle kwalapho okuvunyelwene ngakho ngokubhaliwe yi-Intel. Amakhasimende e-Intel ayelulekwa ukuthi athole inguqulo yakamuva yokucaciswa kwedivayisi ngaphambi kokuthembela kunoma yiluphi ulwazi olushicilelwe nangaphambi kokufaka ama-oda emikhiqizo noma amasevisi. *Amanye amagama namabhrendi angafunwa njengempahla yabanye.
Iqala ngamaNios® II EDS enguqulweni yesoftware ye-Intel Quartus Prime Pro Edition 19.2 kanye nesoftware ye-Intel Quartus Prime Standard Edition engu-19.1, i-Intel isuse ingxenye ye-Cygwin kunguqulo ye-Windows* ye-Nios II EDS, esikhundleni sayo yafaka i-Windows* Subsytem ye-Linux (WSL). Uma ungumsebenzisi we-Windows*, udinga ukufaka i-WSL ngaphambi kokukhiqiza i-ex yakho yedizayiniample.
Umfanekiso 2. Ukukhiqiza Ukugeleza Komklamo

1. Dala iphrojekthi eqondise umndeni wedivayisi ye-Intel Arria 10 bese ukhetha idivayisi oyifunayo.
2. Kukhathalogi ye-IP, thola futhi uchofoze kabili I-Interface Protocols ➤ Umsindo Nevidiyo ➤ HDMI Intel FPGA IP. Iwindi elisha le-IP Variant noma iwindi elisha lokushintshashintsha kwe-IP liyavela.
3. Cacisa igama lezinga eliphezulu lokuhluka kwakho kwe-IP yangokwezifiso. Umhleli wepharamitha ugcina izilungiselelo zokuhlukahluka kwe-IP ku-a file okuthiwa .ip noma .qsys.
4. Chofoza okuthi KULUNGILE. Umhleli wepharamitha uyavela.
5. Kuthebhu ye-IP, lungiselela imingcele oyifunayo yakho kokubili i-TX ne-RX.
6. Vula ipharamitha yokusekela ye-FRL ukuze ukhiqize i-HDMI 2.1 design example kwimodi ye-FRL. Ivale ukuze ukhiqize i-HDMI 2.0 design exampngaphandle kwe-FRL.
7. Ku-Design Exampkuthebhu, khetha i-Arria 10 HDMI RX-TX Retransmit.
8. Khetha Ukulingisa ukuze ukhiqize ibhentshi lokuhlola, bese ukhetha i-Synthesis ukuze ukhiqize i-ex ye-hardware designample.Kufanele ukhethe okungenani eyodwa yalezi zinketho ukuze ukhiqize i-ex yomklamoample files. Uma ukhetha kokubili, isikhathi sokukhiqiza siba side.
9. Okokukhiqiza File Fometha, khetha i-Verilog noma i-VHDL.
10. Ngekhithi Yokuthuthukiswa Kwethagethi, khetha i-Intel Arria 10 GX FPGA Development Kit. Uma ukhetha ikhithi yokuthuthukisa, idivayisi eqondiwe (ekhethwe esinyathelweni sesi-4) iyashintsha ukuze ifane nedivayisi esebhodini eliqondiwe. Nge-Intel Arria 10 GX FPGA Development Kit, idivayisi ezenzakalelayo yi-10AX115S2F4I1SG.
11. Chofoza okuthi Khiqiza Isibample Design.

Ulwazi Oluhlobene
Ifakwa kanjani i-Windows* Subsystem ye-Linux* (WSL) ku-Windows* OS?
1.2. Ukulingisa Umklamo
Ibhentshi lokuhlola le-HDMI lilingisa idizayini ye-serial loopback ukusuka kusibonelo se-TX kuye kusibonelo se-RX. Ijeneretha yephethini yevidiyo yangaphakathi, umsindo sampi-le generator, i-sideband data generator, namamojula asizayo akhiqiza idatha ashayela isibonelo se-HDMI TX futhi okukhiphayo kwe-serial okuvela kusibonelo se-TX kuxhumeke kusenzakalo se-RX ebhentshini lokuhlola.
Umfanekiso 3. Ukugeleza Kokulingisa Komklamo

1. Iya kufolda yokufanisa oyifunayo.
2. Qalisa iskripthi sokulingisa sesifanisi esisekelwayo ozikhethele sona. Umbhalo uhlanganisa futhi uqhube ibhentshi lokuhlola kusifanisi.
3. Hlaziya imiphumela.

Ithebula 1. Izinyathelo Zokuqalisa Ukulingisa

Isifanisi	Uhlu Lokusebenza	Iziyalezo
I-Riviera-PRO*	/sekulingisa/aldec	Emugqeni womyalo, thayipha
		vsim -c -do aldec.do
ImodeliSim*	/sekulingisa/umeluleki	Emugqeni womyalo, thayipha
		vsim -c -do mentor.do
VCS*	/simulation/synopsy/vcs	Emugqeni womyalo, thayipha
		umthombo vcs_sim.sh
I-VCS MX	/simulation/synopsy/ vcsmx	Emugqeni womyalo, thayipha
		umthombo vcsmx_sim.sh
I-Xcelium* Parallel	/sekulingisa/xcelium	Emugqeni womyalo, thayipha
		umthombo xcelium_sim.sh

Ukulingisa okuyimpumelelo kugcina ngomlayezo olandelayo:
# IZIMPAWU_NGEWASHI = 2
#VIC = 4
# FRL_RATE = 0
#BPP =0
# I-AUDIO_FREQUENCY (kHz) = 48
# I-AUDIO_CHANNEL = 8
# Iphasi yokulingisa
1.3. Ukuhlanganisa Nokuhlola Idizayini

Ukuhlanganisa nokusebenzisa ukuhlolwa kokubonisa ku-hardware example design, landela lezi zinyathelo:

1. Qinisekisa i-hardware exampi-design generation iqedile.
2. Yethula isofthiwe ye-Intel Quartus Prime bese uvule i-.qpf file.
   • I-HDMI 2.1 design example nge-FRL Yokusekela inikwe amandla: umkhombandlela wephrojekthi/quartus/a10_hdmi21_frl_demo.qpf
   • I-HDMI 2.0 design example nge-FRL Yokusekela ikhutshaziwe: irectory/quartus/a10_hdmi2_demo.qpf eqanjiwe
3. Chofoza Ukucubungula ➤ Qala Ukuhlanganisa.
4. Ngemva kokuhlanganiswa ngempumelelo, i-.sof file izokwenziwa ku-quartus/output_files lwemibhalo.
5. Xhuma embotsheni ye-FMC esebhodini B (J2):
   • I-HDMI 2.1 design example enokusekelwa kwe-FRL inikwe amandla: I-Bitec HDMI 2.1 FMC Ikhadi Lendodakazi Rev 9
   Qaphela: Ungakhetha ukubuyekezwa kwekhadi lakho lendodakazi ye-Bitec HDMI. Ngaphansi Komklamo Example thebhu, setha Ukubuyekezwa Kwekhadi Lendodakazi ye-HDMI libe yi-Revision 9, Revision noma elingenalo ikhadi lendodakazi. Inani elizenzakalelayo yi-Revision 9.
   • I-HDMI 2.0 design example nge-Support FRL ikhutshaziwe: I-Bitec HDMI 2.0 FMC Ikhadi Lendodakazi Rev 11
6. Xhuma i-TX (P1) yekhadi lendodakazi le-Bitec FMC emthonjeni wamavidiyo wangaphandle.
7. Xhuma i-RX (P2) yekhadi lendodakazi le-Bitec FMC kusinki wangaphandle wevidiyo noma isihlaziyi sevidiyo.
8. Qinisekisa ukuthi wonke amaswishi ebhodini lokuthuthukisa asesimweni sokuzenzakalelayo.
9. Lungiselela idivayisi ye-Intel Arria 10 ekhethiwe ebhodini lokuthuthukisa usebenzisa i-.sof ekhiqiziwe file (Amathuluzi ➤ Umklami ).
10. Umhlaziyi kufanele abonise ividiyo ekhiqizwe emthonjeni.

Ulwazi Oluhlobene
I-Intel Arria 10 FPGA Development Kit User Guide
1.4. I-HDMI Intel FPGA IP Design Example Amapharamitha
Ithebula 2.
I-HDMI Intel FPGA IP Design Example Amapharamitha we-Intel Arria 10 Amadivayisi Lezi zinketho zitholakala kumadivayisi we-Intel Arria 10 kuphela.

Ipharamitha	Inani	Incazelo
Idizayini Etholakalayo Example
Khetha i-Design	I-Arria 10 HDMI RX-TX Retransmit	Khetha i-ex designample ezokwenziwa.

I-Design Example Files
Ukulingisa	Khanyisa cisha	Vula le nketho ukuze ukhiqize okudingekayo files okwebhentshi lokulinganisa lokulingisa.
I-synthesis	Khanyisa cisha	Vula le nketho ukuze ukhiqize okudingekayo files yokuhlanganiswa kwe-Intel Quartus Prime kanye nokuboniswa kwehadiwe.

Kwenziwe Ifomethi ye-HDL
Khiqiza File Ifomethi	I-Verilog, i-VHDL	Khetha ifomethi oyithandayo ye-HDL ye-ex yedizayini ekhiqiziweample filesetha. Qaphela: Le nketho inquma kuphela ifomethi yeleveli ephezulu ye-IP ekhiqiziwe files. Konke okunye files (isbample testbenches kanye nezinga eliphezulu files yokuboniswa kwezingxenyekazi zekhompyutha) zikufomethi ye-Verilog HDL

Ikhithi Yokuthuthukisa Okuqondisiwe
Khetha Ibhodi	Ayikho Ikhithi Yokuthuthukisa,	Khetha ibhodi ye-ex yedizayini eqondisiweample.
	I-Arria 10 GX FPGA Development Kit, Ikhithi Yokuthuthukisa Ngokwezifiso	• Ayikho Ikhithi Yokuthuthukisa: Le nketho ayifaki zonke izici zehadiwe ye-ex yedizayiniample. I-IP core isetha yonke imisebenzi yephinikhodi kumaphinikhodi abonakalayo. • I-Arria 10 GX FPGA Development Kit: Le nketho ikhetha ngokuzenzakalelayo idivayisi eqondiwe yephrojekthi ukuze ifane nedivayisi ekule khithi yokuthuthukisa. Ungashintsha idivayisi eqondiwe usebenzisa i Shintsha Idivayisi Eqondisiwe ipharamitha uma ukubuyekezwa kwebhodi lakho kunokwehlukile kwedivayisi. I-IP core isetha yonke imisebenzi yephinikhodi ngokuya ngekhithi yokuthuthukisa.
		•Ikhithi Yokuthuthukisa Ngokwezifiso: Le nketho ivumela i-ex yedizayiniample izohlolwa kukhithi yokuthuthukisa yenkampani yangaphandle nge-Intel FPGA. Ungase udinge ukusetha imisebenzi yephinikhodi uwedwa.

Idivayisi eqondiwe
Shintsha Idivayisi Eqondisiwe	Khanyisa cisha	Vula le nketho bese ukhetha ukwahluka kwedivayisi okuncamelayo kwekhithi yokuthuthukisa.

I-HDMI 2.1 Design Example (Ukusekela i-FRL = 1)

I-HDMI 2.1 design exampI-le kumodi ye-FRL ibonisa i-loopback eyodwa ye-HDMI ehambisanayo ehlanganisa iziteshi ezine ze-RX neziteshi ezine ze-TX.
Ithebula 3. HDMI 2.1 Design Example ye-Intel Arria 10 Amadivayisi

I-Design Example	Isilinganiso Sedatha	Imodi Yesiteshi	Uhlobo lwe-Loopback
I-Arria 10 HDMI RX-TX Retransmit	• 12 Gbps (FRL) • 10 Gbps (FRL) • 8Gbps (FRL) • 6 Gbps (FRL) • 3 Gbps (FRL) • <6 Gbps (TMDS)	I-Simplex	Ihambisana ne-FIFO buffer

Izici

• Idizayini iqinisekisa amabhafa e-FIFO ukuthi enze ukudlula kokusakaza kwevidiyo ye-HDMI eqondile phakathi kukasinki we-HDMI 2.1 nomthombo.
• Idizayini iyakwazi ukushintsha phakathi kwemodi ye-FRL nemodi ye-TMDS phakathi nesikhathi sokusebenza.
• Idizayini isebenzisa isimo se-LED ukulungisa amaphutha kwangaphambi kwesikhathitage.
• Idizayini iza nezimo ze-HDMI RX kanye ne-TX.
• Idizayini ibonisa ukufakwa nokuhlunga kwe-Dynamic Range and Mastering (HDR) InfoFrame kumojula yesixhumanisi ye-RX-TX.
• Idizayini ixoxisana ngenani le-FRL phakathi kukasinki oxhunywe ku-TX kanye nomthombo oxhunywe ku-RX. Idizayini idlula ku-EDID isuka kusinki yangaphandle iye ku-RX esebhodini ekucushweni okuzenzakalelayo. Iphrosesa ye-Nios II ixoxisana ngesisekelo sesixhumanisi emandleni kasinki oxhunywe ku-TX. Ungaphinda uguqule iswishi ye-user_dipsw ebhodini ukuze ulawule mathupha amandla e-TX kanye ne-RX FRL.
• Umklamo uhlanganisa izici ezimbalwa zokulungisa iphutha.
  Isibonelo se-RX sithola umthombo wevidiyo ovela kujeneretha yevidiyo yangaphandle, bese idatha idlula ku-loopback FIFO ngaphambi kokuba idluliselwe esibonelweni se-TX. Udinga ukuxhuma isihlaziyi sevidiyo sangaphandle, imonitha, noma ithelevishini enoxhumano lwe-HDMI kumongo we-TX ukuze uqinisekise ukusebenza.

2.1. I-HDMI 2.1 RX-TX Retransmit Design Block Diagram
I-HDMI RX-TX yokudlulisa kabusha idizayini exampI-le ibonisa i-loopback ehambisanayo kumodi yesiteshi elula ye-HDMI 2.1 nge-Support FRL enikwe amandla.
Umfanekiso 4. HDMI 2.1 RX-TX Retransmit Block Diagram2.2. Idala i-RX-Only noma i-TX-Only Designs
Kubasebenzisi abathuthukile, ungasebenzisa idizayini ye-HDMI 2.1 ukuze udale idizayini ye-TX- noma ye-RX kuphela.
Umfanekiso wesi-5. Izingxenye ezidingekayo ku-RX-Only noma i-TX-Only DesignUkuze usebenzise i-RX- noma izingxenye ze-TX kuphela, susa amabhulokhi angabalulekile ekwakhiweni.
Ithebula 4. I-RX-Only kanye ne-TX-Only Design Izidingo

Izidingo Zomsebenzisi	Gcina	Susa	Engeza
I-HDMI RX kuphela	I-RX ephezulu	• TX Phezulu • Isixhumanisi se-RX-TX • Isistimu engaphansi ye-CPU • I-Transceiver Arbiter	–
I-HDMI TX kuphela	•TX Phezulu •I-CPU Sub-System	•RX Phezulu • Isixhumanisi se-RX-TX •I-Transceiver Arbiter	Ijeneretha Yephethini Yevidiyo(imojula yangokwezifiso noma ekhiqizwe ku-Video and Image Processing (VIP) Suite)

Ngaphandle kwezinguquko ze-RTL, udinga futhi ukuhlela umbhalo we-main.c.
• Ngemiklamo ye-HDMI TX kuphela, yehlisa ukulinda isimo sokukhiya i-HDMI RX ngokususa imigqa elandelayo bese ufaka esikhundleni sayo.
tx_xcvr_reconfig(tx_frl_rate);
rx_hdmi_lock = READ_PIO(PIO_IN0_BASE, PIO_RX_LOCKED_OFFSET,
PIO_RX_LOCKED_WIDTH);
ngenkathi (rx_hdmi_lock == 0) {
uma (check_hpd_isr()) {break; }
// rx_vid_lock = READ_PIO(PIO_IN0_BASE, PIO_VID_LOCKED_OFFSET,
PIO_VID_LOCKED_WIDTH);
rx_hdmi_lock = READ_PIO(PIO_IN0_BASE, PIO_RX_LOCKED_OFFSET,
PIO_RX_LOCKED_WIDTH);
// Hlela kabusha i-Tx ngemuva kokuthi i-rx ikhiyiwe
uma (rx_hdmi_lock == 1) {
uma (READ_PIO(PIO_IN0_BASE, PIO_LOOPBACK_MODE_OFFSET,
PIO_LOOPBACK_MODE_WIDTH) == 1) {
rx_frl_rate = READ_PIO(PIO_IN0_BASE, PIO_RX_FRL_RATE_OFFSET,
PIO_RX_FRL_RATE_WIDTH);
tx_xcvr_reconfig(rx_frl_rate);
} okunye {
tx_xcvr_reconfig(tx_frl_rate);
}}}
• Ngemiklamo ye-HDMI RX kuphela, gcina kuphela imigqa elandelayo kusikripthi esikhulu.c:
I-REDRIVER_INIT();
hdmi_rx_init();
2.3. Izingxenyekazi zekhompuyutha nezidingo zeSoftware
I-Intel isebenzisa izingxenyekazi zekhompuyutha ezilandelayo nesofthiwe ukuhlola i-ex yedizayiniample.
Izingxenyekazi zekhompuyutha

• I-Intel Arria 10 GX FPGA Development Kit
• Umthombo we-HDMI 2.1 (I-Quantum Data 980 48G Generator)
• I-HDMI 2.1 Sink (I-Quantum Data 980 48G Analyzer)
• Ikhadi lendodakazi le-Bitec HDMI FMC 2.1 (Isibuyekezo 9)
• Izintambo ze-HDMI 2.1 Isigaba 3 (zihlolwe ngekhebuli ye-Belkin 48Gbps HDMI 2.1)

Isofthiwe

• Isoftware ye-Intel Quartus Prime Pro Edition engu-20.1

2.4. Ukwakheka Kwemibhalo
Izikhombisi ziqukethe okukhiqiziwe files ye-HDMI Intel FPGA IP design example.
Umfanekiso 6. Ukwakheka Kwemibhalo Yomklamo ExampleIthebula 5. I-RTL Ekhiqiziwe Files

Amafolda	Files/Amafolda angaphansi
evamile	clock_control.ip
	clock_crosser.v
	dcfifo_inst.v
	i-edge_detector.sv
	i-fifo.ip
	output_buf_i2c.ip

	test_pattern_gen.v
	tpg.v
	tpg_data.v
gxb	gxb_rx.ip
	gxb_rx_reset.ip
	gxb_tx.ip
	gxb_tx_fpll.ip
	gxb_tx_reset.ip
i-hdmi_rx	hdmi_rx.ip
	hdmi_rx_top.v
	Panasonic.hex
i-hdmi_tx	hdmi_tx.ip
	hdmi_tx_top.v
i2c_isigqila	i2c_avl_mst_intf_gen.v
	i2c_clk_cnt.v
	i2c_condt_det.v
	i2c_databuffer.v
	i2c_rxshifter.v
	i2c_slvfsm.v
	i2c_spksuppp.v
	i2c_txout.v
	i2c_txshifter.v
	i2cslave_to_avlmm_bridge.v
i-pl	pll_hdmi_reconfig.ip
	pll_frl.ip
	pll_reconfig_ctrl.v
	pll_tmds.ip
	pll_vidclk.ip
	i-quartus.ini
rxtx_isixhumanisi	i-altera_hdmi_hdr_infoframe.v
	aux_mux.qsys
	aux_retransmit.v
	aux_src_gen.v
	ext_aux_filter.v

	rxtx_link.v
	scfifo_vid.ip
lungisa kabusha	mr_rx_iopll_tmds/
	mr_rxphy/
	mr_tx_fpll/
	altera_xcvr_functions.sv
	mr_compare.sv
	mr_rate_detect.v
	mr_rx_rate_detect_top.v
	mr_rx_rcfg_ctrl.v
	mr_rx_reconfig.v
	mr_tx_rate_detect_top.v
	mr_tx_rcfg_ctrl.v
	mr_tx_reconfig.v
	rcfg_array_streamer_iopll.sv
	rcfg_array_streamer_rxphy.sv
	rcfg_array_streamer_rxphy_xn.sv
	rcfg_array_streamer_txphy.sv
	rcfg_array_streamer_txphy_xn.sv
	rcfg_array_streamer_txpll.sv
sdc	a10_hdmi2.sdc
	jtag.sdc

Ithebula 6. Ukulingisa Okukhiqiziwe Files
Bheka ku- Ukulingisa Testbench ingxenye ukuze uthole ulwazi olwengeziwe

Amafolda	Files
i-aldec	/aldec.do
	/rivierapro_setup.tcl
i-cadence	/cds.lib
	/hdl.var
umeluleki	/mentor.do
	/msim_setup.tcl
ama-synopsy	/vcs/fileuhlu.f
	/vcs/vcs_setup.sh

	/vcs/vcs_sim.sh
	/vcsmx/synopsys_sim_setup
	/vcsmx/vcsmx_setup.sh
	/vcsmx/vcsmx_sim.sh
xcelium	/cds.lib
	/hdl.var
	/xcelium_setup.sh
	/xcelium_sim.sh
evamile	/imodeli_files.tcl
	/riviera_files.tcl
	/vcs_files.tcl
	/vcsmx_files.tcl
	/xcelium_files.tcl
i-hdmi_rx	/hdmi_rx.ip
	/Panasonic.hex
i-hdmi_tx	/hdmi_tx.ip

Ithebula 7. Isoftware Ekhiqiziwe Files

Amafolda	Files
tx_control_src Qaphela: Ifolda ye-tx_control iqukethe nezimpinda zalokhu files.	global.h
	hdmi_rx.c
	hdmi_rx.h
	hdmi_tx.c
	hdmi_tx.h
	hdmi_tx_read_edid.c
	hdmi_tx_read_edid.h
	Intel_fpga_i2c.c
	Intel_fpga_i2c.h
	main.c
	pio_funda_bhala.c
	pio_funda_bhala.h

2.5. Izingxenye Zokuklama
I-HDMI Intel FPGA IP design exampi-le iqukethe izingxenye ezijwayelekile zezinga eliphezulu kanye nezingxenye eziphezulu ze-HDMI TX ne-RX.
2.5.1. Izingxenye ze-HDMI TX
Izingxenye eziphezulu ze-HDMI TX zifaka izingxenye ze-TX eziyinhloko ezisezingeni eliphezulu, kanye ne-IOPLL, isilawuli sokusetha kabusha i-transceiver PHY, i-transceiver yomdabu i-PHY, i-TX PLL, ukuphathwa kabusha kwe-TX, kanye namabhulokhi webhafa okukhiphayo.
Umfanekiso 7. Izingxenye eziphezulu ze-HDMI TXIthebula 8. Izingxenye eziphezulu ze-HDMI TX

Imojuli	Incazelo
I-HDMI TX Core	I-IP ithola idatha yevidiyo esuka ezingeni eliphezulu futhi yenza ukufakwa kwekhodi kwedatha okuyisizayo, ukubhala ngekhodi kwedatha yomsindo, ukubhala ngekhodi kwedatha yevidiyo, ukukrweca, ukubhala ngekhodi kwe-TMDS noma ukupakisha.
I-IOPLL	I-IOPLL (iopll_frl) ikhiqiza iwashi le-FRL le-TX core. Leli washi eliyireferensi lithola iwashi lokuphumayo le-TX FPLL. Ifrikhwensi yewashi le-FRL = Izinga ledatha ngomzila ngamunye x 4 / (izinhlamvu ze-FRL ngewashi ngalinye x 18)
I-Transceiver PHY Setha Kabusha Isilawuli	Isilawuli sokusetha kabusha i-Transceiver PHY siqinisekisa ukuqaliswa okuthembekile kwama-transceiver e-TX. Ukusetha kabusha okokufaka kwalesi silawuli kuqalwa kusuka ezingeni eliphezulu, futhi kukhiqiza isignali ehambisanayo yokusetha kabusha i-analog nedijithali kubhulokhi ye-Transceiver Native PHY ngokuya ngohlelo lokusetha kabusha ngaphakathi kwebhulokhi. Isignali ephumayo engu-tx_ready esuka kule bhulokhi iphinde isebenze njengesignali yokusetha kabusha ku-HDMI Intel FPGA IP ukukhombisa ukuthi i-transceiver iyasebenza, futhi isilungele ukwamukela idatha kusuka kumongo.
I-Transceiver Native PHY	I-Hard transceiver block ethola idatha ehambisanayo evela kumongo we-HDMI TX futhi ihlela idatha ngokuyidlulisela. Qaphela: Ukuze uhlangabezane nemfuneko ye-HDMI TX inter-channel skew, setha inketho yemodi yebhondi yesiteshi se-TX kusihleli sepharamitha ye-Intel Arria 10 Transceiver Native PHY ukuze Ukuhlanganiswa kwe-PMA ne-PCS. Udinga futhi ukwengeza imfuneko enkulu ye-skew (set_max_skew) kusignali yokusetha kabusha idijithali evela kusilawuli sokusetha kabusha i-transceiver (tx_digitalreset) njengoba kunconyiwe ku- Intel Arria 10 Transceiver PHY Umhlahlandlela Womsebenzisi.
I-TX PLL	Ibhulokhi yokudlulisa i-PLL inikeza iwashi elisheshayo le-serial kubhulokhi ye-Transceiver Native PHY. Kulo mklamo we-HDMI Intel FPGA IP example, fPLL isetshenziswa njenge-TX PLL. I-TX PLL inamawashi ayizethenjwa amabili. • Iwashi eliyireferensi elingu-0 lixhunywe ku-oscillator ehlelekayo (enefrikhwensi yewashi le-TMDS) yemodi ye-TMDS. Kulo mklamo example, iwashi le-RX TMDS lisetshenziselwa ukuxhuma ewashini eliyinkomba 0 lemodi ye-TMDS. I-Intel incoma ukuthi usebenzise i-oscillator ehlelekayo enefrikhwensi yewashi le-TMDS ngewashi eliyireferensi elingu-0. • Iwashi eliyisithenjwa 1 lixhunywe ewashini elingashintshi le-100 MHz lemodi ye-FRL.
Ukuphathwa Kabusha kwe-TX	•Kumodi ye-TMDS, ibhulokhi yokuphatha ukulungiselelwa kabusha kwe-TX iphinda ilungise i-TX PLL ukuze uthole amafrikhwensi ewashi okukhiphayo okuhlukile ngokuya ngefrikhwensi yewashi le-TMDS levidiyo ethile. •Kumodi ye-FRL, ibhulokhi yokulawula ukulungiselelwa kabusha kwe-TX iphinda ilungise i-TX PLL ukuze inikeze iwashi elisheshayo le-serial lika-3 Gbps, 6 Gbps, 8 Gbps, 10 Gbps kanye no-12 Gbps ngokuya ngenkambu ye-FRL_Rate kurejista ye-SCDC engu-0x31. •Ibhulokhi yokulawula ukumiswa kabusha kwe-TX ishintsha iwashi lesithenjwa le-TX PLL phakathi kwewashi eliyinkomba elingu-0 kumodi ye-TMDS kanye newashi eliyireferensi 1 kumodi ye-FRL.
I-buffer yokukhipha	Le buffer isebenza njengesixhumi esibonakalayo sokusebenzisana ne-I2C interface ye-HDMI DDC kanye nezingxenye zokushayela kabusha.

Ithebula 9.Izinga ledatha ye-Transceiver kanye nama-OverampIsici Iwashi Ngalinye Ibanga Lefrequency

Imodi	Isilinganiso Sedatha	overampingxenye 1 (2x overample)	overampingxenye 2 (4x overample)	overample Isici	overampLed Data Rate (Mbps)
TMDS	250–1000	On	On	8	2000–8000
TMDS	1000–6000	On	Valiwe	2	2000–12000
I-FRL	3000	Valiwe	Valiwe	1	3000
I-FRL	6000	Valiwe	Valiwe	1	6000

I-FRL	8000	Valiwe	Valiwe	1	8000
I-FRL	10000	Valiwe	Valiwe	1	10000
I-FRL	12000	Valiwe	Valiwe	1	12000

Umfanekiso 8. Ukugeleza Kokulandelana Kokuhlelwa kabusha kwe-TX2.5.2. Izingxenye ze-HDMI RX
Izingxenye eziphezulu ze-HDMI RX zifaka izingxenye ze-RX eziyinhloko ezingeni eliphezulu, isigqila se-I²C esingakhethwa kanye ne-EDID RAM, i-IOPLL, isilawuli sokusetha kabusha i-transceiver PHY, i-RX yomdabu PHY, kanye namabhulokhi okuphatha ukulungisa kabusha kwe-RX.
Umfanekiso 9. Izingxenye eziphezulu ze-HDMI RXIthebula 10. Izingxenye eziphezulu ze-HDMI RX

Imojuli	Incazelo
I-HDMI RX Core	I-IP ithola idatha ye-serial evela ku-Transceiver Native PHY futhi yenza ukuqondanisa kwedatha, i-channel deskew, ukuqoshwa kwe-TMDS, ukuqoshwa kwedatha eyinsiza, ukuqoshwa kwedatha yevidiyo, ukuqoshwa kwedatha yomsindo, nokuhlehlisa.
I2C Isigqila	I-I2C isixhumi esibonakalayo esisetshenziselwa iSink Display Data Channel (DDC) kanye Nesimo Nesiteshi Sedatha (SCDC). Umthombo we-HDMI usebenzisa i-DDC ukuze unqume amandla nezici zikasinki ngokufunda Uhlaka Lwedatha Yokuhlonza Isibonisi Esithuthukisiwe (E-EDID). Amakheli esigqila angu-8-bit I2C e-E-EDID athi 0xA0 kanye no-0xA1. I-LSB ikhombisa uhlobo lokufinyelela: 1 ukufunda no-0 ukubhala. Uma kwenzeka umcimbi we-HPD, isigqila se-I2C siphendula idatha ye-E-EDID ngokufunda ku-chip Isilawuli sesigqila kuphela se-I2C siphinde sisekele i-SCDC ye-HDMI 2.0 kanye no-2.1 Ikheli lesigqila le-9-bit I2C le-SCDC ngu-0xA8 no-0xA9. Uma kwenzeka umcimbi we-HPD, isigqila se-I2C senza umsebenzi wokubhala noma wokufunda ukuya noma ukusuka kusixhumanisi esibonakalayo se-SCDC somongo we-HDMI RX. Inqubo yokuqeqesha yokuxhumanisa ye-Fixed Rate Link (FRL) nayo yenzeka nge-I2C Phakathi nomcimbi we-HPD noma lapho umthombo ubhala inani elihlukile le-FRL kurejista ye-FRL Rate (i-SCDC ibhalisa i-0x31 bit[3:0]), inqubo yokuqeqesha isixhumanisi iyaqala. Qaphela: Lesi silawuli se-I2C sesigqila kuphela se-SCDC asidingeki uma ngabe i-HDMI 2.0 noma i-HDMI 2.1 ingahlosiwe.

I-EDID RAM

Idizayini igcina imininingwane ye-EDID isebenzisa i-RAM 1-Port IP. Intambo evamile enezintambo ezimbili (iwashi nedatha) iphrothokholi yebhasi yochungechunge (I2C isilawuli sesigqila kuphela) idlulisela ukwakheka kwedatha ye-CEA-861-D Ethobelana ne-E-EDID. Le EDID RAM igcina imininingwane ye-E-EDID. •Uma ukumodi ye-TMDS, idizayini isekela ukudlula kwe-EDID ukusuka ku-TX kuye ku-RX. Ngesikhathi sokudlula kwe-EDID, lapho i-TX ixhunywe kusinki wangaphandle, iphrosesa ye-Nios II ifunda i-EDID kusinki yangaphandle bese ibhalela i-EDID RAM. • Uma ikumodi ye-FRL, iphrosesa ye-Nios II ibhala i-EDID emiswe ngaphambili ngezinga ngalinye lesixhumanisi ngokusekelwe kupharamitha ye-HDMI_RX_MAX_FRL_RATE kusikripthi se-global.h. Sebenzisa okokufaka okulandelayo kwe-HDMI_RX_MAX_FRL_RATE ngenani elisekelwayo le-FRL: • 1: 3G 3 Imizila • 2: 6G 3 Imizila •3: 6G 4 Imizila • 4: 8G 4 Imizila •5: 10G 4 Lanes (okuzenzakalelayo) •6: 12G 4 Imizila

I-IOPLL

I-HDMI RX isebenzisa ama-IOPLL amabili. • I-IOPLL yokuqala (pll_tmds) ikhiqiza iwashi lesithenjwa le-RX CDR. Le IOPLL isetshenziswa kuphela kumodi ye-TMDS. Iwashi eliyireferensi lale IOPLL lithola iwashi le-TMDS. Imodi ye-TMDS isebenzisa le-IOPLL ngoba i-CDR ayikwazi ukuthola amawashi ayizethenjwa angaphansi kuka-50 MHz futhi imvamisa yewashi le-TMDS isukela ku-25 MHz kuya ku-340 MHz. Le IOPLL ihlinzeka ngefrikhwensi yewashi izikhathi ezi-5 zewashi lesithenjwa sokufakwa kwebanga lemvamisa phakathi kuka-25 MHz kuya ku-50 MHz futhi inikeza ifrikhwensi yewashi efana newashi eliyinkomba okokufaka lebanga lemvamisa phakathi kuka-50 MHz kuya ku-340 MHz. •I-IOPLL yesibili (iopll_frl) ikhiqiza iwashi le-FRL le-RX core. Leli washi eliyireferensi lithola iwashi elitholiwe le-CDR. Ifrikhwensi yewashi le-FRL = Izinga ledatha ngomzila ngamunye x 4 / (izinhlamvu ze-FRL ngewashi ngalinye x 18)

I-Transceiver PHY Setha Kabusha Isilawuli	Isilawuli sokusetha kabusha i-Transceiver PHY siqinisekisa ukuqaliswa okuthembekile kwama-transceivers e-RX. Ukusetha kabusha okokufaka kwalesi silawuli kuqalwa ukulungiswa kabusha kwe-RX, futhi kukhiqiza isignali ehambisanayo yokusetha kabusha i-analog nedijithali kubhulokhi ye-Transceiver Native PHY ngokuya ngohlelo lokusetha kabusha ngaphakathi kwebhulokhi.
I-RX Native PHY	I-Hard transceiver block ethola idatha ye-serial emthonjeni wangaphandle wevidiyo. Isusa idatha ye-serial kudatha ehambisanayo ngaphambi kokudlulisa idatha kumongo we-HDMI RX. Leli bhulokhi lisebenza kuma-PCS athuthukisiwe kumodi ye-FRL. I-RX CDR inamawashi ayizethenjwa amabili. • Iwashi eliyireferensi elingu-0 lixhunywe ewashini elikhiphayo le-IOPLL TMDS (pll_tmds), elisuselwa ewashini le-TMDS. • Iwashi eliyisithenjwa 1 lixhunywe ewashini elingashintshi le-100 MHz. Kumodi ye-TMDS, i-RX CDR ihlelwa kabusha ukuze ikhethe iwashi eliyinkomba 0, futhi kumodi ye-FRL, i-RX CDR ihlelwa kabusha ukuze kukhethwe iwashi eliyinkomba 1.
I-RX Reconfiguration Management	Kumodi ye-TMDS, ibhulokhi yokuphatha yokulungiswa kabusha kwe-RX isebenzisa ukujikeleza kokutholwa kwesilinganiso nge-HDMI PLL ukuze ishayele i-transceiver ye-RX ukuze isebenze nganoma yimaphi amanani esixhumanisi angenasizathu asuka ku-250 Mbps kuya ku-6,000 Mbps. Kumodi ye-FRL, ibhulokhi yokulawula ukulungisa kabusha i-RX iphinda ilungise i-transceiver ye-RX ukuthi isebenze ku-3 Gbps, 6 Gbps, 8 Gbps, 10 Gbps, noma 12 Gbps kuye ngenani le-FRL kunkambu yokubhalisa ye-SCDC_FRL_RATE (0x31[3:0]). Ibhulokhi yokuphatha ukulungisa kabusha i-RX ishintsha phakathi kwe-Standard PCS/RX ngemodi ye-TMDS kanye ne-PCS ethuthukisiwe yemodi ye-FRL.Bheka ku Umfanekiso 10 ekhasini lesi-22.

Umfanekiso 10. Ukugeleza Kokulandelana Kokuhlelwa Kabusha kwe-RX
Isibalo sibonisa ukugeleza kokulandelana kokuhlelwa kabusha kwezilinganiso eziningi kwesilawuli lapho sithola ukusakaza kwedatha yokokufaka kanye nemvamisa yewashi lesithenjwa, noma uma i-transceiver ivuliwe.2.5.3. Amabhulokhi Ajwayelekile Wezinga eliphezulu
Amabhulokhi ajwayelekile asezingeni eliphezulu afaka i-transceiver arbiter, i-RX-TX link components, kanye ne-subsystem ye-CPU.
Ithebula 11. Amabhulokhi Ajwayelekile Ezinga eliphezulu

Imojuli

Incazelo

I-Transceiver Arbiter

Le block esebenzayo ivimbela ama-transceiver ekuzilungiseni kabusha ngesikhathi esisodwa lapho ama-transceiver e-RX noma e-TX ngaphakathi kwesiteshi esingokoqobo esifanayo edinga ukulungiswa kabusha. Ukulungisa kanyekanye kuthinta izinhlelo zokusebenza lapho ama-transceiver e-RX ne-TX ngaphakathi kwesiteshi esifanayo abelwa ekusetshenzisweni okuzimele kwe-IP. Lesi sixazululi se-transceiver siyisandiso sesinqumo esinconyelwe ukuhlanganisa i-simplex TX ne-simplex RX esiteshini esifanayo somzimba. Lesi sixazululi se-transceiver futhi siyasiza ekuhlanganiseni nasekuxazululeni izicelo ze-Avalon® ezifakwe kumephu yenkumbulo ye-RX kanye ne-TX yokuhlela kabusha eziqondiswe kuma-transceivers e-simplex RX kanye ne-TX ngaphakathi kwesiteshi njengoba imbobo yokuhlanganisa yokuhlela kabusha yama-transceivers ingafinyelelwa ngokulandelana. Ukuxhumana phakathi kwe-transceiver arbiter kanye ne-TX/RX Native PHY/PHY Setha Kabusha Isilawuli kuvimbe kulesi sici somklamo.ampI-le ibonisa imodi ejwayelekile esebenza kunoma iyiphi inhlanganisela ye-IP kusetshenziswa i-transceiver arbiter. I-transceiver arbiter ayidingeki uma kuphela i-RX noma i-TX transceiver esetshenziswa esiteshini. Umxazululi we-transceiver uhlonza umfakisicelo wokumiswa kabusha ngokusebenzisa i-Avalon yayo yokuhlelwa kabusha kwemephu yenkumbulo yokusebenzelana futhi iqinisekisa ukuthi okuhambisanayo tx_reconfig_cal_busy noma rx_reconfig_cal_busy kufakwe isango ngokufanele. Kuzinhlelo zokusebenza ze-HDMI, i-RX kuphela eqala ukumisa kabusha. Ngokuhambisa isicelo sokumisa kabusha okufakwe kumephu yenkumbulo ye-Avalon ngomxazululi, umxazululi ukhomba ukuthi isicelo sokumisa kabusha sisuka ku-RX, ebese ivula i-tx_reconfig_cal_busy ekugomeni futhi ivumele i-rx_reconfig_cal_busy ukuthi igomele. Isango livimbela i-transceiver ye-TX ukuthi ihanjiswe kumodi yokulinganisa ngokungenhloso. Qaphela: Ngenxa yokuthi i-HDMI idinga ukulungiswa kabusha kwe-RX kuphela, amasiginali we-tx_reconfig_mgmt_* avaliwe. Futhi, isixhumi esibonakalayo esinemephu yenkumbulo ye-Avalon ayidingeki phakathi kwe-arbiter kanye nebhulokhi ye-TX Native PHY. Amabhulokhi abelwa ku-interface ku-ex designample ukukhombisa ukuxhumana kwe-generic transceiver arbiter ku-TX/RX Native PHY/PHY Isilawuli Sokusetha Kabusha

Isixhumanisi se-RX-TX

• Idatha yevidiyo ephumayo namasignali okuvumelanisa asuka ku-HDMI RX core loop nge-DCFIFO kuzo zonke izizinda zewashi levidiyo ye-RX ne-TX. • Imbobo yedatha eyisiza ye-HDMI TX core ilawula idatha eyisizayo egeleza ku-DCFIFO ngokucindezela emuva. I-backpressure iqinisekisa ukuthi alikho iphakethe elisizayo elingaphelele kuchweba ledatha elisizayo. • Le block futhi yenza ukuhlunga kwangaphandle: — Ihlunga idatha yomsindo nephakethe lokuvuselela iwashi elisuka emfudlaneni wedatha oyisizayo ngaphambi kokudlulisela embobeni yedatha eyinsiza ye-HDMI TX. - Ihlunga i-High Dynamic Range (HDR) InfoFrame isuka kudatha ye-HDMI RX eyisiza bese ifaka i-ex.ample HDR InfoFrame kudatha eyisilekeleli ye-HDMI TX ngokusebenzisa i-Avalon yokusakaza i-multiplexer.

Isistimu engaphansi ye-CPU

I-subsystem ye-CPU isebenza njengezilawuli ze-SCDC ne-DDC, kanye nesilawuli sokusetha kabusha umthombo. • Isilawuli se-SCDC somthombo siqukethe isilawuli esiyinhloko se-I2C. Isilawuli esiyinhloko se-I2C sidlulisela ukwakheka kwedatha ye-SCDC ukusuka kumthombo we-FPGA kuya kusinki wangaphandle ukuze usebenze nge-HDMI 2.0. Okwesiboneloampfuthi, uma ukusakazwa kwedatha okuphumayo kungu-6,000 Mbps, iphrosesa ye-Nios II iyala isilawuli esiyinhloko se-I2C ukuthi sibuyekeze amabhithi e-TMDS_BIT_CLOCK_RATIO kanye ne-SCRAMBLER_ENABLE erejista yokucushwa ye-TMDS kasinki ibe ngu-1. • I-I2C master efanayo iphinde idlulise ukwakheka kwedatha ye-DDC (E-EDID) phakathi komthombo we-HDMI nosinki wangaphandle. • I-Nios II CPU isebenza njengesilawuli sokuhlela kabusha somthombo we-HDMI. I-CPU incike ekutholweni kwesilinganiso sezikhathi ezithile kusuka kumojula Yokulawula Ukulungisa Kabusha kwe-RX ukuze inqume ukuthi i-TX idinga ukulungiswa kabusha. Umhumushi wesigqila ofakwe kumephu yenkumbulo ye-Avalon unikeza ukuxhumana phakathi kwephrosesa ye-Nios II ye-Avalon ebalazwe ngenkumbulo eyinhloko yesixhumi esibonakalayo kanye ne-Avalon yenkumbulo yesigqila esixhunywe kwimemori ye-IOPLL yomthombo wangaphandle we-HDMI ye-IOPLL kanye ne-TX Native PHY. • Yenza ukuqeqeshwa kwesixhumanisi ngokusebenzisa i-I2C master interface enosinki wangaphandle

2.6. I-Dynamic Range and Mastering (HDR) Ukufakwa Nokuhlunga Kwe-InfoFrame
I-HDMI Intel FPGA IP design example ihlanganisa ukuboniswa kokufakwa kwe-HDR InfoFrame kusistimu ye-loopback ye-RX-TX.
Inguqulo ye-HDMI Specification 2.0b ivumela i-Dynamic Range kanye ne-Mastering InfoFrame ukuthi idluliselwe ngokusakaza okuwusizo kwe-HDMI. Embukisweni, ibhulokhi ye-Axiliary Packet Generator isekela ukufakwa kwe-HDR. Udinga kuphela ukufometha iphakethe le-HDR InfoFrame elihlosiwe njengoba kucaciswe kuthebula lohlu lwesiginali yemojuli kanye nokufakwa kwe-HDR InfoFrame kwenzeka kanye ngozimele wevidiyo.
Kulesi example ukucushwa, ezimeni lapho ukusakaza okuyisizayo okungenayo sekuvele kufaka i-HDR InfoFrame, okuqukethwe kwe-HDR okusakazwayo kuyahlungwa. Ukuhlunga kugwema ukungqubuzana kwe-HDR InfoFrames ukuthi idluliselwe futhi kuqinisekisa ukuthi amanani kuphela ashiwo ku-HDR S.ample Data module zisetshenziswa.
Umfanekiso 11. Isixhumanisi se-RX-TX ne-Dynamic Range kanye nokufakwa kwe-Mastering InfoFrame
Isibalo sibonisa umdwebo webhlokhi wesixhumanisi se-RX-TX ohlanganisa i-Dynamic Range kanye nokufakwa kwe-Mastering InfoFrame ekusakazeni okuyinhloko kwe-HDMI TX.Ithebula 12. I-Axiliary Data Insertion Block (aux_retransmit) Amasignali

Isiginali	Isiqondiso	Ububanzi	Incazelo
Iwashi bese usetha kabusha
clk	Okokufaka	1	Okokufaka kwewashi. Leli washi kufanele lixhunywe ewashini levidiyo.
setha kabusha	Okokufaka	1	Setha kabusha okokufaka.

Izimpawu Zephakethe Lokusiza
tx_aux_idatha	Okukhiphayo	72	Iphakethe le-TX elisizayo eliphuma ku-multiplexer.
tx_aux_valid	Okukhiphayo	1
tx_aux_ready	Okukhiphayo	1
tx_aux_sop	Okukhiphayo	1
tx_aux_eop	Okukhiphayo	1
rx_aux_idatha	Okokufaka	72	Idatha yokusiza ye-RX idluliselwe kumojula yesihlungi sephakethe ngaphambi kokufaka i-multiplexer.
rx_aux_valid	Okokufaka	1
rx_aux_sop	Okokufaka	1
rx_aux_eop	Okokufaka	1

Isiginali Yokulawula
hdmi_tx_vsync	Okokufaka	1	I-HDMI TX Video Vsync. Lesi siginali kufanele ivunyelaniswe esizindeni sewashi lejubane lesixhumanisi.Umongo ufaka i-HDR InfoFrame ekusakazeni okuyisizayo emaphethelweni akhuphukayo alesi siginali.

Ithebula 13. I-HDR Data Module (altera_hdmi_hdr_infoframe) Amasignali

Isiginali	Isiqondiso	Ububanzi	Incazelo
hb0	Okukhiphayo	8	I-header byte 0 ye-Dynamic Range kanye ne-Mastering InfoFrame: ikhodi yohlobo lwe-InfoFrame.
hb1	Okukhiphayo	8	I-header byte 1 ye-Dynamic Range kanye ne-Mastering InfoFrame: inombolo yenguqulo ye-InfoFrame.
hb2	Okukhiphayo	8	I-header byte 2 ye-Dynamic Range kanye ne-Mastering InfoFrame: Ubude be-InfoFrame.
pb	Okokufaka	224	Idatha byte ye-Dynamic Range kanye ne-Mastering InfoFrame.

Ithebula 14. I-Dynamic Range kanye ne-Mastering InfoFrame Data Byte Bundle Bit-Fields

I-Bit-Field	Incazelo	Uhlobo 1 lwemethadatha emile
7:0	Idatha Byte 1: {5'h0, EOTF[2:0]}
15:8	Idatha Byte 2: {5'h0, Static_Metadata_Descriptor_ID[2:0]}
23:16	Ibhayithi Yedatha 3: Static_Metadata_Descriptor	display_primaries_x[0], LSB
31:24	Ibhayithi Yedatha 4: Static_Metadata_Descriptor	display_primaries_x[0], MSB
39:32	Ibhayithi Yedatha 5: Static_Metadata_Descriptor	display_primaries_y[0], LSB
47:40	Ibhayithi Yedatha 6: Static_Metadata_Descriptor	display_primaries_y[0], MSB
55:48	Ibhayithi Yedatha 7: Static_Metadata_Descriptor	display_primaries_x[1], LSB
63:56	Ibhayithi Yedatha 8: Static_Metadata_Descriptor	display_primaries_x[1], MSB
71:64	Ibhayithi Yedatha 9: Static_Metadata_Descriptor	display_primaries_y[1], LSB
79:72	Ibhayithi Yedatha 10: Static_Metadata_Descriptor	display_primaries_y[1], MSB
87:80	Ibhayithi Yedatha 11: Static_Metadata_Descriptor	display_primaries_x[2], LSB
95:88	Ibhayithi Yedatha 12: Static_Metadata_Descriptor	display_primaries_x[2], MSB
103:96	Ibhayithi Yedatha 13: Static_Metadata_Descriptor	display_primaries_y[2], LSB
111:104	Ibhayithi Yedatha 14: Static_Metadata_Descriptor	display_primaries_y[2], MSB
119:112	Ibhayithi Yedatha 15: Static_Metadata_Descriptor	white_point_x, LSB
127:120	Ibhayithi Yedatha 16: Static_Metadata_Descriptor	white_point_x, MSB
135:128	Ibhayithi Yedatha 17: Static_Metadata_Descriptor	white_point_y, LSB
143:136	Ibhayithi Yedatha 18: Static_Metadata_Descriptor	white_point_y, MSB
151:144	Ibhayithi Yedatha 19: Static_Metadata_Descriptor	max_display_mastering_luminance, LSB

159:152	Ibhayithi Yedatha 20: Static_Metadata_Descriptor	max_display_mastering_luminance, MSB
167:160	Ibhayithi Yedatha 21: Static_Metadata_Descriptor	min_display_mastering_luminance, LSB
175:168	Ibhayithi Yedatha 22: Static_Metadata_Descriptor	min_display_mastering_luminance, MSB
183:176	Ibhayithi Yedatha 23: Static_Metadata_Descriptor	Izinga Lokukhanya Lokuqukethwe Okuphezulu, LSB
191:184	Ibhayithi Yedatha 24: Static_Metadata_Descriptor	Izinga Lokukhanya Lokuqukethwe Okuphezulu, i-MSB
199:192	Ibhayithi Yedatha 25: Static_Metadata_Descriptor	I-Maximum Frame-average Light Level, LSB
207:200	Ibhayithi Yedatha 26: Static_Metadata_Descriptor	Ileveli Yokukhanya Okumaphakathi Okumaphakathi, i-MSB
215:208	Igodliwe
223:216	Igodliwe

Ikhubaza Ukufakwa Nokuhlunga kwe-HDR
Ukukhubaza ukufakwa nesihlungi se-HDR kukwenza ukwazi ukuqinisekisa ukudluliswa kabusha kokuqukethwe kwe-HDR osekuvele kutholakala kumthombo wokusakaza osizayo ngaphandle kokuguqulwa kwanoma yikuphi ukuguqulwa ku-design ye-RX-TX Retransmit ex.ample.
Ukuze ukhubaze ukufakwa nokuhlunga kwe-HDR InfoFrame:

1. Setha i-block_ext_hdr_infoframe ibe ngu-1'b0 kokuthi rxtx_link.v file ukuze uvimbele ukuhlungwa kwe-HDR InfoFrame kusukela ekusakazeni kwe-Axiliary.
2. Setha i-multiplexer_in0_valid ye-avalon_st_multiplexer ku-altera_hdmi_aux_hdr.v file kuya ku-1'b0 ukuze kuvinjelwe i-Axiliary Packet Generator ekwenzeni futhi ifake i-HDR InfoFrame eyengeziwe ekusakazeni kwe-TX kwe-Axiliary.

2.7. I-Design Software Flow
Ekugelezeni kwesoftware eyinhloko, iphrosesa ye-Nios II ilungiselela ukulungiselelwa komshayeli kabusha we-TI futhi iqalise izindlela ze-TX ne-RX lapho kunyuswa amandla.
Umfanekiso 12. Ukugeleza Kwesofthiwe ku-main.c Script
Isofthiwe isebenzisa iluphu yesikhashana ukuze igade usinki kanye nezinguquko zomthombo, kanye nokusabela ezinguqukweni. Isofthiwe ingase iqalise ukulungiswa kabusha kwe-TX, ukuqeqeshwa kwesixhumanisi se-TX futhi iqale ukudlulisa ividiyo.
Umfanekiso 13. I-TX Path Ukuqalisa Ishadi Eligelezayo Qalisa Umzila We-TXUmfanekiso 14. Ishadi Eligelezayo Lokuqalisa Umzila we-RXUmfanekiso 15. I-TX Reconfiguration kanye ne-Link Training FlowchartUmfanekiso 16. Xhumanisa Ukuqeqeshwa kwe-LTS: Inqubo ye-3 ku-Specific FRL Rate FlowchartUmfanekiso 17. I-HDMI TX Video Transmission Flowchart2.8. Isebenzisa Idizayini Ngamazinga Ahlukene e-FRL
Ungasebenzisa idizayini yakho ngamanani ahlukene e-FRL, ngaphandle kwesilinganiso se-FRL esimisiwe sikasinki wangaphandle.
Ukuze uqalise umklamo ngamanani ahlukene we-FRL:

1. Guqula i-on-board user_dipsw0 shintshela ku-VULIWE isikhundla.
2. Vula igobolondo lomyalo we-Nios II, bese uthayipha i-nios2-terminal
3. Faka imiyalo elandelayo bese ucindezela u-Enter ukuze usebenzise.

Umyalo	Incazelo
h	Bonisa imenyu yosizo.
r0	Buyekeza amandla e-RX aphezulu e-FRL abe yisilinganiso se-FRL esingu-0 (TMDS kuphela).
r1	Buyekeza amandla e-RX aphezulu e-FRL kuya ku-FRL isilinganiso 1 (3 Gbps).
r2	Buyekeza amandla e-RX aphezulu e-FRL abe yisilinganiso se-FRL esingu-2 (6 Gbps, imizila emi-3).
r3	Buyekeza amandla e-RX aphezulu e-FRL abe yisilinganiso se-FRL esingu-3 (6 Gbps, imizila emi-4).
r4	Buyekeza amandla e-RX aphezulu e-FRL kuya ku-FRL isilinganiso 4 (8 Gbps).
r5	Buyekeza amandla e-RX aphezulu e-FRL kuya ku-FRL isilinganiso 5 (10 Gbps).
r6	Buyekeza amandla e-RX aphezulu e-FRL kuya ku-FRL isilinganiso 6 (12 Gbps).
t1	I-TX ilungiselela izinga lokuxhumanisa libe yisilinganiso se-FRL esingu-1 (3 Gbps).
t2	I-TX ilungiselela izinga lokuxhumanisa libe yizinga le-FRL elingu-2 (6 Gbps, imizila emi-3).
t3	I-TX ilungiselela izinga lokuxhumanisa libe yizinga le-FRL elingu-3 (6 Gbps, imizila emi-4).
t4	I-TX ilungiselela izinga lokuxhumanisa libe yisilinganiso se-FRL esingu-4 (8 Gbps).
t5	I-TX ilungiselela izinga lokuxhumanisa libe yisilinganiso se-FRL esingu-5 (10 Gbps).
t6	I-TX ilungiselela izinga lokuxhumanisa libe yisilinganiso se-FRL esingu-6 (12 Gbps).

2.9. Uhlelo Lokuvala
Isikimu sewashi sibonisa izizinda zewashi ku-HDMI Intel FPGA IP design example.
Umfanekiso 18. HDMI 2.1 Design Example Clock SchemeIthebula 15. Izimpawu Zohlelo Lokuvala

Iwashi	Igama Lesiginali Kudizayini	Incazelo
Iwashi Lokuphatha	mgmt_clk	Iwashi elisebenza mahhala elingu-100 MHz kulezi zingxenye: • Izixhumanisi ze-Avalon-MM ukuze zilungiswe kabusha - Imfuneko yobubanzi befrikhwensi iphakathi kuka-100-125 MHz. • I-PHY setha kabusha isilawuli sokulandelana kokusetha kabusha kwe-transceiver - Imfuneko yobubanzi befrikhwensi iphakathi kuka-1-500 MHz. • Ukumiswa kabusha kwe-IOPLL - Imvamisa yewashi ephezulu ngu-100 MHz. • Ukulawulwa Kokuhlela Kabusha kwe-RX • Ukuphathwa Kabusha kwe-TX • CPU • I-I2C Master
I2C Iwashi	i2c_cl	Okokufaka kwewashi okungu-100 MHz okufaka isigqila se-I2C, amabhafa okukhiphayo, amarejista e-SCDC, kanye nenqubo yokuqeqesha exhumanisa kumongo we-HDMI RX, kanye ne-EDID RAM.
TX PLL Reference Clock 0	tx_tmds_clk	Iwashi lereferensi 0 ku-TX PLL. Ifrikhwensi yewashi iyafana nefrikhwensi yewashi ye-TMDS elindelwe evela esiteshini sewashi se-HDMI TX TMDS. Leli washi eliyireferensi lisetshenziswa kumodi ye-TMDS. Kulo mklamo we-HDMI exampfuthi, leli washi lixhunywe ewashini le-RX TMDS ngenjongo yokubonisa. Kuhlelo lwakho lokusebenza, udinga ukunikeza iwashi elizinikele elinefrikhwensi yewashi le-TMDS kusuka ku-oscillator ehlelekayo ukuze uthole ukusebenza okungcono kwe-jitter.

		Qaphela: Ungasebenzisi i-transceiver RX pin njengewashi lereferensi le-TX PLL. Idizayini yakho izohluleka ukulingana uma ubeka i-HDMI TX refclk kuphinikhodi ye-RX.
TX PLL Reference Clock 1	txfpll_refclk1/ rxphy_cdr_refclk1	Iwashi eliyinkomba ku-TX PLL ne-RX CDR, kanye ne-IOPLL ye-vid_clk. Imvamisa yewashi ngu-100 MHz.
TX PLL Serial Clock	tx_bonding_clocks	Iwashi le-serial elisheshayo elakhiwe yi-TX PLL. Ifrikhwensi yewashi isethwe ngokusekelwe esilinganisweni sedatha.
Iwashi le-TX Transceiver Out	tx_clk	Iwashi eliphumayo elitholiwe ku-transceiver, futhi imvamisa iyahlukahluka kuye ngezinga ledatha nezimpawu ngewashi ngalinye. I-TX transceiver clock out frequency = Isilinganiso sedatha ye-Transceiver/ Ububanzi be-Transceiver Kulo mklamo we-HDMI example, iwashi le-TX transceiver eliphuma esiteshini 0 liwashi iwashi le-TX transceiver core input (tx_coreclkin), iwashi lereferensi lesixhumanisi le-IOPLL (pll_hdmi), kanye newashi eliyireferensi levidiyo ne-FRL IOPLL (pll_vid_frl).
Iwashi levidiyo	tx_vid_clk/rx_vid_clk	Iwashi levidiyo eliya ku-TX kanye ne-RX core. Iwashi lisebenza ngemvamisa engaguquki engu-225 MHz.
Iwashi le-TX/RX FRL	tx_frl_clk/rx_frl_clk	Iwashi le-FRL eliya ku-TX kanye ne-RX core.
Iwashi le-RX TMDS	rx_tmds_clk	Ishaneli yewashi ye-TMDS esuka kusixhumi se-HDMI RX futhi ixhuma ku-IOPLL ukuze ikhiqize iwashi lesithenjwa lewashi lereferensi le-CDR 0. Umongo usebenzisa leli washi uma likumodi ye-TMDS.
RX CDR Reference Clock 0	rxphy_cdr_refclk0	Iwashi eliyinkomba 0 ukuya ku-RX CDR. Leli washi lisuselwa ewashini le-RX TMDS. Imvamisa yewashi le-RX TMDS isukela ku-25 MHz kuya ku-340 MHz kuyilapho ubuncane bewashi lereferensi ye-RX CDR ingu-50 MHz. I-IOPLL isetshenziselwa ukukhiqiza imvamisa yewashi elingu-5 wewashi le-TMDS phakathi kuka-25 MHz kuya ku-50 MHz futhi ikhiqize imvamisa yewashi efanayo yewashi le-TMDS phakathi kuka-50 MHz - 340 MHz.
I-RX Transceiver Clock Out	rx_clk	Iwashi eliphumayo elitholiwe ku-transceiver, futhi imvamisa iyahlukahluka kuye ngezinga ledatha nobubanzi be-transceiver. I-RX transceiver clock out frequency = Isilinganiso sedatha ye-Transceiver/ Ububanzi be-Transceiver Kulo mklamo we-HDMI example, iwashi le-transceiver ye-RX eliphuma esiteshini 1 liwashi iwashi lereferensi le-RX transceiver core (rx_coreclkin) kanye newashi eliyireferensi le-FRL IOPLL (pll_frl).

2.10. Izimpawu Zokuxhumana
Amathebula aklelisa amasiginali we-HDMI design example ene-FRL inikwe amandla.
Ithebula 16. Izimpawu Zezinga eliphezulu

Isiginali	Isiqondiso	Ububanzi	Incazelo
Isiginali ye-Oscillator esebhodini
clk_fpga_b3_p	Okokufaka	1	100 MHz iwashi eligijima lamahhala lewashi eliyinkomba eliyinhloko.
refclk4_p	Okokufaka	1	100 MHz iwashi eligijima lamahhala lewashi lereferensi ye-transceiver.

Izinkinobho Zokusunduza Zomsebenzisi nama-LED
umsebenzisi_pb	Okokufaka	3	Cindezela inkinobho ukuze ulawule ukusebenza komklamo we-HDMI Intel FPGA IP.
cpu_resetn	Okokufaka	1	Ukusetha kabusha umhlaba.
umsebenzisi_led_g	Okukhiphayo	8	Isibonisi se-LED eluhlaza. Bukela ku Ukusethwa kwe-Hardware ekhasini 48 ukuze uthole ulwazi olwengeziwe mayelana nemisebenzi ye-LED.
umsebenzisi_dipsw	Okokufaka	1	Iswishi ye-DIP echazwe umsebenzisi. Bukela ku Ukusethwa kwe-Hardware ekhasini 48 ukuze uthole ulwazi olwengeziwe mayelana nemisebenzi yokushintsha i-DIP.

Izikhonkwane zekhadi lendodakazi le-HDMI le-FMC ku-FMC Port B
fmcb_gbtclk_m2c_p_0	Okokufaka	1	Iwashi le-HDMI RX TMDS.
fmcb_dp_m2c_p	Okokufaka	4	Iwashi le-HDMI RX, amashaneli edatha abomvu, aluhlaza, naluhlaza okwesibhakabhaka.
fmcb_dp_c2m_p	Okukhiphayo	4	Iwashi le-HDMI TX, amashaneli edatha abomvu, aluhlaza, naluhlaza okwesibhakabhaka.
fmcb_la_rx_p_9	Okokufaka	1	Ukutholwa kwamandla kwe-HDMI RX +5V.
fmcb_la_rx_p_8	Okukhiphayo	1	Ukutholwa kwepulagi eshisayo ye-HDMI RX.
fmcb_la_rx_n_8	Okokufaka	1	I-HDMI RX I2C SDA ye-DDC ne-SCDC.
fmcb_la_tx_p_10	Okokufaka	1	I-HDMI RX I2C SCL ye-DDC ne-SCDC.
fmcb_la_tx_p_12	Okokufaka	1	Ukutholwa kwepulaki eshisayo ye-HDMI TX.
fmcb_la_tx_n_12	Okokufaka	1	I-HDMI I2C SDA ye-DDC ne-SCDC.
fmcb_la_rx_p_10	Okokufaka	1	I-HDMI I2C SCL ye-DDC ne-SCDC.
fmcb_la_tx_n_9	Okokufaka	1	I-HDMI I2C SDA yokulawula umshayeli kabusha.
fmcb_la_rx_p_11	Okokufaka	1	I-HDMI I2C SCL yokulawula umshayeli kabusha.
fmcb_la_tx_n_13	Okukhiphayo	1	I-HDMI TX +5V Qaphela: Kutholakala kuphela uma Ukubuyekezwa kwekhadi lendodakazi le-Bitec HDMI 9 ikhethiwe.

Ithebula 17. Izimpawu ze-HDMI RX Zezinga eliphezulu

Isiginali	Isiqondiso	Ububanzi	Incazelo
Iwashi futhi Setha Kabusha Amasignali
mgmt_clk	Okokufaka	1	Okokufaka kwewashi lesistimu (100 MHz).
setha kabusha	Okokufaka	1	Okokufaka kokusetha kabusha isistimu.
rx_tmds_clk	Okokufaka	1	Iwashi le-HDMI RX TMDS.
i2c_cl	Okokufaka	1	Okokufaka kwewashi kwe-DDC ne-SCDC interface.

Iwashi futhi Setha Kabusha Amasignali
rxphy_cdr_refclk1	Okokufaka	1	Okokufaka kwewashi kwewashi lereferensi le-RX CDR 1. Ifrikhwensi yewashi ngu-100 MHz.
rx_vid_clk	Okukhiphayo	1	Okukhipha iwashi levidiyo.
sys_init	Okukhiphayo	1	Ukuqaliswa kwesistimu ukuze kusethwe kabusha isistimu lapho kucishwa amandla.

I-RX Transceiver kanye ne-IOPLL Signals
rxpll_tmds_locked	Okukhiphayo	1	Ikhombisa iwashi le-TMDS elithi IOPLL likhiyiwe.
rxpll_frl_ikhiyiwe	Okukhiphayo	1	Ikhombisa iwashi le-FRL i-IOPLL ikhiyiwe.
rxphy_serial_data	Okokufaka	4	Idatha ye-HDMI ye-serial eya ku-RX Native PHY.
rxphy_ready	Okukhiphayo	1	Ikhombisa ukuthi i-RX Native PHY isilungile.
rxphy_cal_busy_raw	Okukhiphayo	4	Ukulinganisa kwe-RX Native PHY kumatasa ku-transceiver arbiter.
rxphy_cal_busy_gated	Okokufaka	4	Isignali ematasa yokulinganisa isuka ku-transceiver arbiter iye ku-RX Native PHY.
rxphy_rcfg_slave_write	Okokufaka	4	I-Transceiver reconfiguration ye-Avalon memory-mapped interface kusuka ku-RX Native PHY kuya kumlamuli we-transceiver.
rxphy_rcfg_slave_read	Okokufaka	4
rxphy_rcfg_slave_address	Okokufaka	40
rxphy_rcfg_slave_writedata	Okokufaka	128
rxphy_rcfg_slave_readdata	Okukhiphayo	128
rxphy_rcfg_slave_waitrequest	Okukhiphayo	4

I-RX Reconfiguration Management
rxphy_rcfg_matasatasa	Okukhiphayo	1	I-RX Reconfiguration isignali ematasa.
rx_tmds_freq	Okukhiphayo	24	Isilinganiso sefrikhwensi yewashi le-HDMI RX TMDS (ngama-10 ms).
rx_tmds_freq_valid	Okukhiphayo	1	Ikhombisa ukuthi isilinganiso sefrikhwensi yewashi le-RX TMDS sivumelekile.
rxphy_os	Okukhiphayo	1	overampi-ling factor: •0: 1x ama-overampling • 1: 5× ngaphezuluampling
rxphy_rcfg_master_write	Okukhiphayo	1	Ukuphathwa kokulungiswa kabusha kwe-RX isixhumi esibonakalayo esinemephu yenkumbulo ye-Avalon ku-transceiver arbiter.
rxphy_rcfg_master_read	Okukhiphayo	1
rxphy_rcfg_master_address	Okukhiphayo	12
rxphy_rcfg_master_writedata	Okukhiphayo	32
rxphy_rcfg_master_readdata	Okokufaka	32
rxphy_rcfg_master_waitrequest	Okokufaka	1

Izimpawu ze-HDMI RX Core
rx_vid_clk_locked	Okokufaka	1	Ikhombisa ukuthi i-vid_clk izinzile.
rxcore_frl_isilinganiso	Okukhiphayo	4	Ibonisa izinga le-FRL elisetshenziswa yi-RX core. • 0: Imodi yefa (TMDS) • 1: 3 Gbps 3 imizila • 2: 6 Gbps 4 imizila • 3: 6 Gbps 4 imizila • 4: 8 Gbps 4 imizila • 5: 10 Gbps 4 imizila • 6: 12 Gbps 4 imizila • 7-15: Ibekelwe
rxcore_frl_locked	Okukhiphayo	4	Ibhithi ngalinye libonisa umzila othile ozuze ukukhiya kwe-FRL. I-FRL ikhiyiwe lapho i-RX core yenza ngempumelelo ukuqondanisa, ideskew, futhi ifinyelela ukukhiya komzila. • Ngemodi yomzila ongu-3, ​​ukukhiya umzila kufinyelelwa lapho i-RX core ithola i-Scrambler Reset (SR) noma i-Start-Super-Block (SSB) kuzo zonke izikhathi zezinhlamvu ezingu-680 FRL okungenani izikhathi ezingu-3. • Ngemodi yomzila ongu-4, ​​ukukhiya umzila kufinyelelwa lapho i-RX core ithola i-Scrambler Reset (SR) noma i-Start-Super-Block (SSB) kuzo zonke izikhathi zezinhlamvu ezingu-510 FRL okungenani izikhathi ezingu-3.
rxcore_frl_ffe_levels	Okukhiphayo	4	Ihambisana ne-FFE_level bit kurejista ye-SCDC 0x31 [7:4] kumongo we-RX.
rxcore_frl_flt_ready	Okokufaka	1	Ukugomela okukhombisa ukuthi i-RX isilungele ukuthi inqubo yokuqeqeshwa kwesixhumanisi iqale. Uma kugonyelwa, i-FLT_ready bit kurejista ye-SCDC ethi 0x40 bit 6 nayo iyagonyelwa.
rxcore_frl_src_test_config	Okokufaka	8	Icacisa ukulungiselelwa kokuhlolwa komthombo. Inani libhalwe kurejista Yokucushwa Kokuhlolwa kwe-SCDC kurejista ye-SCDC engu-0x35.
rxcore_tbcr	Okukhiphayo	1	Ibonisa isilinganiso sebhithi ye-TMDS yewashi; ihambisana nerejista ye-TMDS_Bit_Clock_Ratio kurejista ye-SCDC 0x20 bit 1. • Uma isebenza ngemodi ye-HDMI 2.0, le bhithi iyagonyelwa. Ibonisa isilinganiso sebhithi newashi se-TMDS esingu-40:1. • Uma isebenza ku-HDMI 1.4b, le bhithi ayigonyelwa. Ibonisa isilinganiso sebhithi newashi se-TMDS esingu-10:1. • Le bhithi ayisetshenziselwa imodi ye-FRL.
rxcore_scrambler_enable	Okukhiphayo	1	Ibonisa uma idatha etholiwe ihlanjalazwa; ihambisana nenkambu ethiScrambling_Vumela kurejista ye-SCDC 0x20 bit 0.
rxcore_audio_de	Okukhiphayo	1	Izixhumanisi zomsindo eziyinhloko ze-HDMI RX Bheka ku- Sink Interfaces isigaba ku I-HDMI Intel FPGA IP User Guide ukuze uthole ulwazi olwengeziwe.
idatha_yomsindo_ye-rxcore	Okukhiphayo	256
rxcore_audio_info_ai	Okukhiphayo	48

rxcore_audio_N	Okukhiphayo	20
rxcore_audio_CTS	Okukhiphayo	20
rxcore_audio_metadata	Okukhiphayo	165
rxcore_audio_format	Okukhiphayo	5
rxcore_aux_pkt_data	Okukhiphayo	72	Izixhumanisi eziyisiza eziyinhloko ze-HDMI RX Bheka ku- Sink Interfaces isigaba ku I-HDMI Intel FPGA IP User Guide ukuze uthole ulwazi olwengeziwe.
rxcore_aux_pkt_addr	Okukhiphayo	6
rxcore_aux_pkt_wr	Okukhiphayo	1
rxcore_aux_data	Okukhiphayo	72
rxcore_aux_sop	Okukhiphayo	1
rxcore_aux_eop	Okukhiphayo	1
rxcore_aux_valid	Okukhiphayo	1
rxcore_aux_error	Okukhiphayo	1
rxcore_gcp	Okukhiphayo	6	Amasiginali webhendi eseceleni ye-HDMI RX Bheka ku- Sink Interfaces isigaba ku I-HDMI Intel FPGA IP User Guide ukuze uthole ulwazi olwengeziwe.
rxcore_info_avi	Okukhiphayo	123
rxcore_info_vsi	Okukhiphayo	61
rxcore_locked	Okukhiphayo	1	Izimbobo zevidiyo eziwumgogodla we-HDMI RX Qaphela: N = amaphikseli iwashi ngalinye Bheka ku- Sink Interfaces isigaba ku I-HDMI Intel FPGA IP User Guide ukuze uthole ulwazi olwengeziwe.
idatha_ye-rxcore_vid	Okukhiphayo	N*48
rxcore_vid_vsync	Okukhiphayo	N
rxcore_vid_hsync	Okukhiphayo	N
rxcore_vid_de	Okukhiphayo	N
rxcore_vid_valid	Okukhiphayo	1
rxcore_vid_lock	Okukhiphayo	1
rxcore_mode	Okukhiphayo	1	Ukulawula okuyinhloko kwe-HDMI RX kanye nezimbobo zesimo. Qaphela: N = izimpawu iwashi ngalinye Bheka ku- Sink Interfaces isigaba ku I-HDMI Intel FPGA IP User Guide ukuze uthole ulwazi olwengeziwe.
rxcore_ctrl	Okukhiphayo	N*6
rxcore_color_depth_sync	Okukhiphayo	2
hdmi_5v_bona	Okokufaka	1	I-HDMI RX 5V ithola futhi ithole i-hotplug. Bheka ku- Sink Interfaces isigaba ku I-HDMI Intel FPGA IP User Guide ukuze uthole ulwazi olwengeziwe.
i-hdmi_rx_hpd	Okukhiphayo	1
rx_hpd_trigger	Okokufaka	1

I2C Izimpawu
hdmi_rx_i2c_sda	Okokufaka	1	I-HDMI RX DDC ne-SCDC interface.
i-hdmi_rx_i2c_scl	Okokufaka	1

Izimpawu ze-RX EDID RAM
edid_ram_access	Okokufaka	1	I-HDMI RX EDID RAM isixhumi esibonakalayo sokufinyelela.

edid_ram_address	Okokufaka	8	Funa i-edid_ram_access uma ufuna ukubhala noma ukufunda ku-EDID RAM, uma kungenjalo le signali kufanele igcinwe iphansi. Uma uthi i-edid_ram_access, isignali ye-hotplug i-desserts ukuvumela ukubhala noma ukufunda ku-EDID RAM. Uma ukufinyelela kwe-RAM ye-EDID kuqediwe, kufanele ukhiphe i-edid_ram_assess kanye nokugomela kwesignali ye-hotplug. Umthombo uzofunda i-EDID entsha ngenxa yokuguqulwa kwesignali ye-hotplug.
edid_ram_bhala	Okokufaka	1
i-ed_ram_read	Okokufaka	1
edid_ram_readdata	Okukhiphayo	8
edid_ram_writedata	Okokufaka	8
edid_ram_waitrequest	Okukhiphayo	1

Ithebula 18.HDMI TX Izimpawu Zezinga eliphezulu

Isiginali	Isiqondiso	Ububanzi	Incazelo
Iwashi futhi Setha Kabusha Amasignali
mgmt_clk	Okokufaka	1	Okokufaka kwewashi lesistimu (100 MHz).
setha kabusha	Okokufaka	1	Okokufaka kokusetha kabusha isistimu.
tx_tmds_clk	Okokufaka	1	Iwashi le-HDMI RX TMDS.
txfpll_refclk1	Okokufaka	1	Okokufaka kwewashi kwewashi lesithenjwa le-TX PLL 1. Ifrikhwensi yewashi ngu-100 MHz.
tx_vid_clk	Okukhiphayo	1	Okukhipha iwashi levidiyo.
tx_frl_clk	Okukhiphayo	1	Okukhipha iwashi le-FRL.
sys_init	Okokufaka	1	Ukuqaliswa kwesistimu ukuze kusethwe kabusha isistimu lapho kucishwa amandla.
tx_init_qedile	Okokufaka	1	Ukuqaliswa kwe-TX ukuze kusethwe kabusha ibhulokhi yokulawulwa kokumiswa kabusha kwe-TX kanye nesixhumi esibonakalayo sokulungiswa kabusha kwe-transceiver.

I-TX Transceiver kanye ne-IOPLL Signals
txpll_frl_locked	Okukhiphayo	1	Ibonisa iwashi lejubane lesixhumanisi futhi iwashi le-FRL i-IOPLL ikhiyiwe.
txfpll_locked	Okukhiphayo	1	Ikhombisa ukuthi i-TX PLL ikhiyiwe.
txphy_serial_data	Okukhiphayo	4	Idatha ye-HDMI ye-serial evela ku-TX Native PHY.
txphy_ready	Okukhiphayo	1	Ikhombisa ukuthi i-TX Native PHY isilungile.
txphy_cal_matasatasa	Okukhiphayo	1	Isiginali yokulinganisa ye-TX Native PHY.
txphy_cal_busy_raw	Okukhiphayo	4	Isignali yokulinganisa ematasa kumlamuli we-transceiver.
txphy_cal_busy_gated	Okokufaka	4	Isiginali yokulinganisa ematasatasa ukusuka ku-transceiver arbiter ukuya ku-TX Native PHY.
txphy_rcfg_matasatasa	Okukhiphayo	1	Ikhombisa ukuthi ukucushwa kabusha kwe-TX PHY kuyaqhubeka.
txphy_rcfg_slave_write	Okokufaka	4	I-Transceiver reconfiguration ye-Avalon memory-mapped interface kusuka ku-TX Native PHY kuya kumlamuli we-transceiver.
txphy_rcfg_slave_read	Okokufaka	4
txphy_rcfg_slave_address	Okokufaka	40
txphy_rcfg_slave_writedata Okokufaka 128 txphy_rcfg_slave_readdata Okukhiphayo 128 txphy_rcfg_slave_waitrequest Okukhiphayo 4

Ukuphathwa Kabusha kwe-TX
tx_tmds_freq	Okokufaka	24	Inani lemvamisa yewashi le-HDMI TX TMDS (ngama-10 ms).
tx_os	Okukhiphayo	2	overampi-ling factor: • 0: 1x ama-overampling •1:2× ngaphezuluampling •2: 8x ama-overampling
txphy_rcfg_master_write	Okukhiphayo	1	Ukuphathwa kokulungiswa kabusha kwe-TX Isixhumi esibonakalayo esinemephu yenkumbulo ye-Avalon kumnqamuli we-transceiver.
txphy_rcfg_master_read	Okukhiphayo	1
txphy_rcfg_master_address	Okukhiphayo	12
txphy_rcfg_master_writedata	Okukhiphayo	32
txphy_rcfg_master_readdata	Okokufaka	32
txphy_rcfg_master_waitrequest	Okokufaka	1
tx_reconfig_done	Okukhiphayo	1	Ibonisa ukuthi inqubo yokumisa kabusha i-TX isiqediwe.

Izimpawu ze-HDMI TX Core
tx_vid_clk_locked	Okokufaka	1	Ikhombisa ukuthi i-vid_clk izinzile.
txcore_ctrl	Okokufaka	N*6	Izixhumanisi zokulawula eziyinhloko ze-HDMI TX. Qaphela: N = amaphikseli iwashi ngalinye Bheka ku- Source Interfaces isigaba ku I-HDMI Intel FPGA IP User Guide ukuze uthole ulwazi olwengeziwe.
txcore_mode	Okokufaka	1
txcore_audio_de	Okokufaka	1	Izixhumanisi zomsindo eziyinhloko ze-HDMI TX. Bheka ku- Source Interfaces isigaba ku I-HDMI Intel FPGA IP User Guide ukuze uthole ulwazi olwengeziwe.
Thulisa_umsindo_we-txcore	Okokufaka	1
idatha_yomsindo_ye-txcore	Okokufaka	256
txcore_audio_info_ai	Okokufaka	49
txcore_audio_N	Okokufaka	20
txcore_audio_CTS	Okokufaka	20
txcore_audio_metadata	Okokufaka	166
txcore_audio_format	Okokufaka	5
txcore_aux_ready	Okukhiphayo	1	I-HDMI TX izixhumanisi eziyisiza eziyinhloko. Bheka ku- Source Interfaces isigaba ku I-HDMI Intel FPGA IP User Guide ukuze uthole ulwazi olwengeziwe.
txcore_aux_data	Okokufaka	72
txcore_aux_sop	Okokufaka	1
txcore_aux_eop	Okokufaka	1

txcore_aux_valid	Okokufaka	1
txcore_gcp	Okokufaka	6	I-HDMI TX amasiginali webhendi eseceleni. Bheka ku- Source Interfaces isigaba ku I-HDMI Intel FPGA IP User Guide ukuze uthole ulwazi olwengeziwe.
txcore_info_avi	Okokufaka	123
txcore_info_vsi	Okokufaka	62
txcore_i2c_master_write	Okokufaka	1	I-TX I2C master Avalon-mapped interface to I2C master ngaphakathi kwe-TX core. Qaphela: Lawa masignali atholakala kuphela uma uvula Faka i-I2C ipharamitha.
txcore_i2c_master_read	Okokufaka	1
txcore_i2c_master_address	Okokufaka	4
txcore_i2c_master_writedata	Okokufaka	32
txcore_i2c_master_readdata	Okukhiphayo	32
idatha_ye-txcore_vid	Okokufaka	N*48	Izimbobo zevidiyo ze-HDMI TX. Qaphela: N = amaphikseli ngewashiRef er kwe Source Interfaces isigaba ku I-HDMI Intel FPGA IP User Guide ukuze uthole ulwazi olwengeziwe.
txcore_vid_vsync	Okokufaka	N
txcore_vid_hsync	Okokufaka	N
txcore_vid_de	Okokufaka	N
txcore_vid_ready	Okukhiphayo	1
txcore_vid_chichima	Okukhiphayo	1
I-txcore_vid_valid	Okokufaka	1
txcore_frl_rate	Okokufaka	4	Izixhumanisi zerejista ye-SCDC.
txcore_frl_pattern	Okokufaka	16
txcore_frl_start	Okokufaka	1
txcore_scrambler_enable	Okokufaka	1
i-txcore_tbcr	Okokufaka	1

I2C Izimpawu
nios_tx_i2c_sda_in	Okukhiphayo	1	I-TX I2C Master interface ye-SCDC ne-DDC isuka kuphrosesa ye-Nios II iye kusigcinalwazi esikhiphayo. Qaphela: Uma uvula i- Faka i-I2C ipharamitha, lezi zimpawu zizofakwa ngaphakathi kwe-TX core futhi ngeke zibonakale kuleli zinga.
nios_tx_i2c_scl_in	Okukhiphayo	1
nios_tx_i2c_sda_oe	Okokufaka	1
nios_tx_i2c_scl_oe	Okokufaka	1
nios_ti_i2c_sda_in	Okukhiphayo	1	I-TX I2C Master interface kusukela kuphrosesa ye-Nios II kuya kusigcinalwazi esikhiphayo ukuze ulawule umshayeli kabusha we-TI ekhadini lendodakazi le-Bitec HDMI 2.1 FMC.
nios_ti_i2c_scl_in	Okukhiphayo	1
nios_ti_i2c_sda_oe	Okokufaka	1
nios_ti_i2c_scl_oe	Okokufaka	1
hdmi_tx_i2c_sda	Okokufaka	1	Izixhumanisi ze-TX I2C ze-SCDC ne-DDC zokusebenzelana zisuka kusigcinalwazi sokuphumayo ziye kusixhumi se-HDMI TX.
i-hdmi_tx_i2c_scl	Okokufaka	1
hdmi_tx_ti_i2c_sda	Okokufaka	1	I-TX I2C ixhuma kusuka kusigcinalwazi esikhiphayo kuya kusishayeli kabusha se-TI ekhadini lendodakazi le-Bitec HDMI 2.1 FMC.
i-hdmi_tx_ti_i2c_scl	Okokufaka	1

tx_hpd_req	Okukhiphayo	1	I-HDMI TX hotplug ibona izixhumi ezibonakalayo.
i-hdmi_tx_hpd_n	Okokufaka	1

Ithebula 19. Izimpawu ze-Transceiver Arbiter

Isiginali	Isiqondiso	Ububanzi	Incazelo
clk	Okokufaka	1	Iwashi lokumisa kabusha. Leli washi kufanele labelane ngewashi elifanayo namabhulokhi okuphatha ukulungisa kabusha.
setha kabusha	Okokufaka	1	Setha kabusha isignali. Lokhu kusetha kabusha kufanele kwabelane ngokusetha kabusha okufanayo namabhulokhi okuphatha ukulungisa kabusha.
rx_rcfg_zu	Okokufaka	1	Ukumiswa kabusha kwe-RX kuvumela isignali.
tx_rcfg_zu	Okokufaka	1	Ukumiswa kabusha kwe-TX kuvumela isignali.
rx_rcfg_ch	Okokufaka	2	Ibonisa ukuthi yisiphi isiteshi okufanele simiswe kabusha kumongo we-RX. Lesi siginali kufanele sihlale sigomele.
tx_rcfg_ch	Okokufaka	2	Ibonisa ukuthi yisiphi isiteshi okufanele simiswe kabusha kumongo we-TX. Lesi siginali kufanele sihlale sigomele.
rx_reconfig_mgmt_write	Okokufaka	1	Ukulungisa kabusha i-Avalon yenkumbulo efakwe kumephu yokuxhumana evela ekulawuleni ukulungiselelwa kabusha kwe-RX.
rx_reconfig_mgmt_read	Okokufaka	1
rx_reconfig_mgmt_address	Okokufaka	10
rx_reconfig_mgmt_writedata	Okokufaka	32
rx_reconfig_mgmt_readdata	Okukhiphayo	32
rx_reconfig_mgmt_waitrequest	Okukhiphayo	1
tx_reconfig_mgmt_write	Okokufaka	1	Ukulungisa kabusha i-Avalon memory-mapped interfaces kusuka ku-TX reconfiguration management.
tx_reconfig_mgmt_read	Okokufaka	1
tx_reconfig_mgmt_address	Okokufaka	10
tx_reconfig_mgmt_writedata	Okokufaka	32
tx_reconfig_mgmt_readdata	Okukhiphayo	32
tx_reconfig_mgmt_waitrequest	Okukhiphayo	1
reconfig_write	Okukhiphayo	1	Ukulungisa kabusha i-Avalon yenkumbulo efakwe kumephu yokusebenzelana ku-transceiver.
reconfig_read	Okukhiphayo	1
reconfig_address	Okukhiphayo	10
reconfig_writedata	Okukhiphayo	32
rx_reconfig_readdata	Okokufaka	32
rx_reconfig_waitrequest	Okokufaka	1
tx_reconfig_readdata	Okokufaka	1
tx_reconfig_waitrequest	Okokufaka	1

rx_cal_matasa	Okokufaka	1	Isignali yesimo sokulinganisa evela ku-transceiver ye-RX.
tx_cal_matasa	Okokufaka	1	Isignali yesimo sokulinganisa evela ku-transceiver ye-TX.
rx_reconfig_cal_busy	Okukhiphayo	1	Isignali yesimo sokulinganisa kusilawuli sokusetha kabusha i-RX transceiver PHY.
tx_reconfig_cal_busy	Okukhiphayo	1	Isignali yesimo sokulinganisa evela kusilawuli sokusetha kabusha se-TX transceiver PHY.

Ithebula 20. Izimpawu zokuxhumanisa i-RX-TX

Isiginali	Isiqondiso	Ububanzi	Incazelo
vid_clk	Okokufaka	1	Iwashi levidiyo le-HDMI.
rx_vid_lock	Okokufaka	3	Ibonisa isimo sokukhiya ividiyo ye-HDMI RX.
rx_vid_valid	Okokufaka	1	Izixhumanisi zevidiyo ze-HDMI RX.
rx_vid_de	Okokufaka	N
rx_vid_hsync	Okokufaka	N
rx_vid_vsync	Okokufaka	N
rx_vid_idatha	Okokufaka	N*48
rx_aux_eop	Okokufaka	1	Izixhumanisi ezisizayo ze-HDMI RX.
rx_aux_sop	Okokufaka	1
rx_aux_valid	Okokufaka	1
rx_aux_idatha	Okokufaka	72
tx_vid_de	Okukhiphayo	N	Izixhumanisi zevidiyo ye-HDMI TX. Qaphela: N = amaphikseli iwashi ngalinye
tx_vid_hsync	Okukhiphayo	N
tx_vid_vsync	Okukhiphayo	N
tx_vid_idatha	Okukhiphayo	I-N * 48
tx_vid_ivumelekile	Okukhiphayo	1
tx_vid_ready	Okokufaka	1
tx_aux_eop	Okukhiphayo	1	Izixhumanisi ze-HDMI TX ezisizayo.
tx_aux_sop	Okukhiphayo	1
tx_aux_valid	Okukhiphayo	1
tx_aux_idatha	Okukhiphayo	72
tx_aux_ready	Okokufaka	1

Ithebula 21. Izimpawu Zohlelo Lomklami Wenkundla

Isiginali	Isiqondiso	Ububanzi	Incazelo
cpu_clk_in_clk_clk	Okokufaka	1	Iwashi le-CPU.
cpu_rst_in_reset_reset	Okokufaka	1	Ukusetha kabusha i-CPU.

edid_ram_slave_translator_avalon_anti_slave_0_address	Okukhiphayo	8	Izixhumanisi zokufinyelela ze-EDID RAM.
edid_ram_slave_translator_avalon_anti_slave_0_write	Okukhiphayo	1
edid_ram_slave_translator_avalon_anti_slave_0_read	Okukhiphayo	1
edid_ram_slave_translator_avalon_anti_slave_0_readdata	Okokufaka	8
edid_ram_slave_translator_avalon_anti_slave_0_writedata	Okukhiphayo	8
edid_ram_slave_translator_avalon_anti_slave_0_waitrequest	Okokufaka	1
hdmi_i2c_master_i2c_serial_sda_in	Okokufaka	1	I-I2C Master interfaces isuka kuphrosesa ye-Nios II iye kusigcinalwazi sokuphumayo sokulawula i-DDC ne-SCDC.
hdmi_i2c_master_i2c_serial_scl_in	Okokufaka	1
hdmi_i2c_master_i2c_serial_sda_oe	Okukhiphayo	1
hdmi_i2c_master_i2c_serial_scl_oe	Okukhiphayo	1
redriver_i2c_master_i2c_serial_sda_in	Okokufaka	1	I-I2C Master ixhumanisa isuka kuphrosesa ye-Nios II iye kusigcinalwazi sokuphumayo sokucushwa kwesilungiselelo somshayeli kabusha we-TI.
redriver_i2c_master_i2c_serial_scl_in	Okokufaka	1
redriver_i2c_master_i2c_serial_sda_oe	Okukhiphayo	1
redriver_i2c_master_i2c_serial_scl_oe	Okukhiphayo	1
pio_in0_external_connection_export	Okokufaka	32	Izixhumi ezibonakalayo zokukhiphayo ezihambisanayo. • Ibhithi 0: Ixhunywe kusiginali yomsebenzisi_dipsw ukuze ilawule imodi yokudlula ye-EDID. •Ibhithi 1: Isicelo se-TX HPD •I-Bit 2: I-transceiver ye-TX isilungile •I-Bits 3: Ukulungiswa kabusha kwe-TX kwenziwe •Amabhithi 4–7: Agciniwe • Ibhithi 8–11: Isilinganiso se-RX FRL • Ibhithi 12: Isilinganiso sewashi lebhithi le-RX TMDS • Amabhithi 13–16: I-RX FRL ikhiyiwe • Amabhithi 17–20: Amazinga e-RX FFE • Ibhithi 21: Ukuqondanisa kwe-RX kukhiyiwe

Isiginali	Isiqondiso	Ububanzi	Incazelo
			•I-Bit 22: Ilokhi yevidiyo ye-RX • Ibhithi 23: Inkinobho yokucindezela yomsebenzisi 2 ukuze ufunde amarejista e-SCDC kusinki wangaphandle •Amabhithi 24–31: Agciniwe
pio_out0_external_connection_export	Okukhiphayo	32	Izixhumi ezibonakalayo zokukhiphayo ezihambisanayo. •Bit 0: Ukuvuma kwe-TX HPD •Bit 1: Ukuqalisa kwe-TX kwenziwa • Izingcezu 2–7: Zibekelwe • Ibhithi 8–11: izinga le-TX FRL •Amabhithi angu-12–27: Iphethini yokuqeqeshwa yesixhumanisi se-TX FRL • Ibhithi 28: TX FRL iqala • Izingcezu 29–31: Zibekelwe
pio_out1_external_connection_export	Okukhiphayo	32	Izixhumi ezibonakalayo zokukhiphayo ezihambisanayo. • Ibhithi 0: Ukufinyelela kwe-RAM kwe-RX EDID • Ibhithi 1: I-RX FLT isilungile • Izingcezu 2–7: Zibekelwe • Ibhithi 8–15: Ukumiswa komthombo we-RX FRL wokuhlola •Amabhithi 16–31: Agciniwe

2.1. 1. Yakha amapharamitha e-RTL
Sebenzisa amapharamitha we-HDMI TX kanye ne-RX Top RTL ukuze wenze ngendlela oyifisayo i-ex yomklamoample.
Iningi lamapharamitha wokuklama ayatholakala ku- I-Design Example ithebhu yomhleli wepharamitha ye-HDMI Intel FPGA IP. Usengashintsha i-ex yedizayiniampnezilungiselelo ozenze kusihleli sepharamitha ngamapharamitha e-RTL.
Ithebula 22. Amapharamitha aphezulu we-HDMI RX

Ipharamitha	Inani	Incazelo
SUPPORT_DEEP_COLOR	• 0: Awukho umbala ojulile • : Umbala ojulile	Inquma ukuthi ingabe ingqikithi ingafaka amafomethi ombala ojulile.
SUPPORT_AUXILIARY	• 0: Ayikho i-AUX •1: AUX	Inquma ukuthi umbhalo oyisizayo wesiteshi ufakiwe yini.
SYMBOLS_PER_CLOCK	8	Isekela izimpawu eziyi-8 iwashi ngalinye kumadivayisi we-Intel Arria 10.
SUPPORT_AUDIO	• 0: Awukho umsindo • 1: Umsindo	Inquma ukuthi umgogodla ungabhala yini umsindo.

EDID_RAM_ADDR_WIDTH	8 (Inani elizenzakalelayo)	Isisekelo sokungena esingu-2 sikasayizi we-RAM we-EDID.
BITEC_DAUGHTER_CARD_REV	•0: Ayiqondisi noma yiliphi ikhadi lendodakazi ye-Bitec HDMI •4: Isekela ukubuyekezwa kwekhadi lendodakazi le-Bitec HDMI 4 •6: I-Targeting Bitec HDMI ikhadi lendodakazi lendodakazi 6 • 11: Ukubuyekezwa kwekhadi lendodakazi ye-Bitec HDMI 11 (okuzenzakalelayo)	Icacisa ukubuyekezwa kwekhadi lendodakazi le-Bitec HDMI elisetshenzisiwe. Uma ushintsha isibuyekezo, idizayini ingase ishintshe amashaneli e-transceiver futhi iguqule i-polarity ngokwezidingo zekhadi lendodakazi le-Bitec HDMI. Uma usetha ipharamitha ye-BITEC_DAUGHTER_CARD_REV ibe ngu-0, idizayini ayenzi izinguquko kumashaneli e-transceiver kanye ne-polarity.
POLARITY_INVERSION	• 0: Guqula i-polarity • 1: Ungaguquli i-polarity	Setha le pharamitha ku-1 ukuze uguqule inani lebhithi ngalinye ledatha yokufaka. Ukusetha le pharamitha kokuthi 1 kwabela i-4'b1111 kumbobo ye-rx_poliv ye-transceiver ye-RX.

Ithebula 23. Amapharamitha aphezulu we-HDMI TX

Ipharamitha	Inani	Incazelo
USE_FPLL	1	Isekela i-fPLL njenge-TX PLL kuphela kumadivayisi we-Intel Arria 10. Hlala usethe le pharamitha ku-1.
SUPPORT_DEEP_COLOR	•0: Awukho umbala ojulile • 1: Umbala ojulile	Inquma ukuthi ingabe ingqikithi ingafaka amafomethi ombala ojulile.
SUPPORT_AUXILIARY	• 0: Ayikho i-AUX • 1: AUX	Inquma ukuthi umbhalo oyisizayo wesiteshi ufakiwe yini.
SYMBOLS_PER_CLOCK	8	Isekela izimpawu eziyi-8 iwashi ngalinye kumadivayisi we-Intel Arria 10.
SUPPORT_AUDIO	• 0: Awukho umsindo • 1: Umsindo	Inquma ukuthi umgogodla ungabhala yini umsindo.
BITEC_DAUGHTER_CARD_REV	• 0: Ayiqondile noma yiliphi ikhadi lendodakazi le-Bitec HDMI • 4: Isekela ukubuyekezwa kwekhadi lendodakazi le-Bitec HDMI 4 • 6: I-Targeting Bitec HDMI ikhadi lendodakazi lendodakazi 6 • 11: Ukubuyekezwa kwekhadi lendodakazi ye-Bitec HDMI 11 (okuzenzakalelayo)	Icacisa ukubuyekezwa kwekhadi lendodakazi le-Bitec HDMI elisetshenzisiwe. Uma ushintsha isibuyekezo, idizayini ingase ishintshe amashaneli e-transceiver futhi iguqule i-polarity ngokwezidingo zekhadi lendodakazi le-Bitec HDMI. Uma usetha ipharamitha ye-BITEC_DAUGHTER_CARD_REV ibe ngu-0, idizayini ayenzi izinguquko kumashaneli e-transceiver kanye ne-polarity.
POLARITY_INVERSION	• 0: Guqula i-polarity • 1: Ungaguquli i-polarity	Setha le pharamitha ku-1 ukuze uguqule inani lebhithi ngalinye ledatha yokufaka. Ukusetha le pharamitha kokuthi 1 kwabela i-4'b1111 kumbobo ye-tx_polinv ye-transceiver ye-TX.

2.12. Ukusethwa kwe-Hardware
Umklamo onikwe amandla we-HDMI FRL exampi-HDMI 2.1 iyakwazi futhi yenza umboniso we-loopthrough wokusakaza okujwayelekile kwevidiyo ye-HDMI.
Ukuze uqalise ukuhlolwa kwezingxenyekazi zekhompuyutha, xhuma idivayisi enikwe amandla i-HDMI—njengekhadi lemifanekiso eline-HDMI isixhumi esibonakalayo—kokufakwayo kukasinki we-HDMI. Idizayini isekela kokubili umthombo we-HDMI 2.1 noma we-HDMI 2.0/1.4b nosinki.

1. Usinki we-HDMI uhlukanisa imbobo ibe ukusakaza kwevidiyo okuvamile futhi uyithumele kumongo wokutakula wewashi.
2. I-HDMI RX core inquma ividiyo, isilekeleli, nedatha yomsindo ezobuyiselwa emuva ngokuhambisana nomongo we-HDMI TX nge-DCFIFO.
3. Imbobo yomthombo ye-HDMI yekhadi lendodakazi ye-FMC idlulisela isithombe kusiqaphi.

Qaphela:
Uma ufuna ukusebenzisa elinye ibhodi lokuthuthukisa i-Intel FPGA, kufanele uguqule imisebenzi ezonikezwa idivayisi kanye nezabelo zamaphinikhodi. Isilungiselelo se-analog ye-transceiver sihlolelwa ikhithi yokuthuthukisa ye-Intel Arria 10 FPGA kanye nekhadi lendodakazi le-Bitec HDMI 2.1. Ungashintsha izilungiselelo zebhodi lakho.
Ithebula 24. Inkinobho Yokucindezela Esebhodini kanye Nemisebenzi ye-LED yomsebenzisi

Cindezela inkinobho/I-LED	Umsebenzi
cpu_resetn	Cindezela kanye ukuze wenze kabusha uhlelo.
umsebenzisi_dipsw	Iswishi ye-DIP echazwe umsebenzisi ukuze uguqule imodi yokudlula. •VALIWE (isikhundla esimisiwe) = Ukudlula I-HDMI RX ku-FPGA ithola i-EDID kusinki wangaphandle futhi iyethule emthonjeni ongaphandle exhunywe kuwo. • IVULIWE = Ungalawula isilinganiso esiphezulu se-RX se-FRL kutheminali ye-Nios II. Umyalo ulungisa i-RX EDID ngokukhohlisa inani eliphezulu lezinga le-FRL. Bheka Ekuqaliseni Idizayini Ngamazinga E-FRL Ahlukene ekhasini 33 ukuze uthole ulwazi olwengeziwe mayelana nokusetha amanani e-FRL ahlukene.
umsebenzisi_pb[0]	Cindezela kanye ukuze uguqule isignali ye-HPD iye emthonjeni ojwayelekile we-HDMI.
umsebenzisi_pb[1]	Igodliwe.
umsebenzisi_pb[2]	Cindezela kanye ukuze ufunde amarejista e-SCDC kusinki exhunywe ku-TX yekhadi lendodakazi le-Bitec HDMI 2.1 FMC. Qaphela: Ukuze unike amandla ukufunda, kufanele usethe i-DEBUG_MODE ibe ngu-1 kusofthiwe.
USER_LED[0]	Isimo sokukhiya iwashi le-RX TMDS PLL. •0 = Kuvuliwe • 1 = Ikhiyiwe
USER_LED[1]	Isimo esilungile se-transceiver ye-RX. •0 = Ayikalungi • 1 = Ilungile
USER_LED[2]	Iwashi lejubane lesixhumanisi se-RX PLL, kanye nevidiyo ye-RX kanye nesimo sokukhiya iwashi le-FRL PLL. • 0 = Noma iyiphi i-PLL yewashi le-RX ivuliwe • 1 = Womabili ama-PLL wewashi le-RX akhiyiwe
USER_LED[3]	Ukuqondanisa okuyisisekelo kwe-RX HDMI nesimo sokukhiya ideskew. • 0 = Okungenani ishaneli eyodwa ivuliwe • 1 = Wonke amashaneli avaliwe
USER_LED[4]	Isimo sokukhiya ividiyo ye-RX HDMI. • 0 = Ivuliwe • 1 = Ikhiyiwe
USER_LED[5]	Iwashi lejubane le-TX elixhumanisa i-PLL, kanye nevidiyo ye-TX kanye nesimo sokukhiya iwashi le-FRL PLL. •0 = Iwashi elilodwa le-TX PLL livuliwe • 1 = Womabili ama-PLL wewashi le-TX akhiyiwe
USER_LED[6] USER_LED[7]	Isimo esilungile se-transceiver. • 0 = Ayikalungi • 1 = Ilungile Isimo sokuqeqeshwa sesixhumanisi se-TX. • 0 = Yehlulekile • 1 = Kuphasisiwe

2.13. Ukulingisa Testbench
Ibhentshi lesivivinyo sokulingisa lilingisa i-HDMI TX serial loopback ku-RX core.
Qaphela:
Le bhentshi yokulingisa ayisekelwe kumadizayini anepharamitha ethi Faka i-I2C enikwe amandla.
Umfanekiso 19. I-HDMI Intel FPGA IP Simulation Testbench Block DiagramIthebula 25. Izingxenye ze-Testbench

Isakhi	Incazelo
Ividiyo ye-TPG	Ijeneretha yephethini yokuhlola ividiyo (TPG) inikeza isikhuthazo sevidiyo.
Umsindo Sample Gen	Umsindo sample generator inikeza umsindo sample stimus. Ijeneretha ikhiqiza iphethini yedatha yokuhlola ekhulayo ezodluliswa ngesiteshi somsindo.
Aux Sample Gen	I-aux sample generator inikeza isilekeleli sample stimus. Ijeneretha ikhiqiza idatha engaguquki ezodluliswa isuka kumthumeli.

Hlola CRC	Lesi sihloli siqinisekisa ukuthi i-TX transceiver etholiwe imvamisa yewashi ifana yini nenani ledatha elifunekayo.
Ukuhlola Idatha Yomsindo	Ukuhlolwa kwedatha yomsindo kuqhathanisa ukuthi ingabe iphethini yedatha yokuhlola ekhulayo iyamukelwe futhi iqoshwe ngendlela efanele.
Ukuhlola Idatha ye-Aux	Ukuhlolwa kwedatha ye-aux kuqhathanisa ukuthi idatha ye-aux elindelekile yamukelwe futhi yaqoshwa kahle yini ohlangothini lomamukeli.

I-HDMI simulation testbench yenza izivivinyo zokuqinisekisa ezilandelayo:

Isici se-HDMI	Ukuqinisekisa
Idatha yevidiyo	• Ibhentshi le-test lisebenzisa i-CRC ukuhlola okokufaka nokuphumayo kwevidiyo. • Ihlola inani le-CRC ledatha edlulisiwe iqhathaniswa ne-CRC ebalwa kudatha yevidiyo etholiwe. • Ibhentshi le-test libe selihlola ngemva kokuthola amasignali angu-4 azinzile e-V-SYNC kumamukeli.
Idatha yokusiza	• I-ax sampi-generator ye-le generator ikhiqiza idatha engaguquki ukuze idluliselwe ku-transmitter. • Ohlangothini lomamukeli, ijeneretha iqhathanisa ukuthi idatha eyisisizi elindelekile yamukelwe futhi yaqoshwa ngendlela efanele yini.
Idatha yomsindo	•Umsindo sampi-le generator ikhiqiza iphethini yedatha yokuhlola ekhulayo ezodluliselwa ngesiteshi somsindo. • Ohlangothini lomamukeli, isihloli sedatha yomsindo sihlola futhi siqhathanise ukuthi iphethini yedatha yokuhlola ekhulayo yamukelwe futhi iqoshwe ngendlela efanele yini.

Ukulingisa okuyimpumelelo kugcina ngomlayezo olandelayo:
# IZIMPAWU_NGEWASHI = 2
#VIC = 4
# FRL_RATE = 0
#BPP =0
# I-AUDIO_FREQUENCY (kHz) = 48
# I-AUDIO_CHANNEL = 8
# Iphasi yokulingisa
Ithebula 26. HDMI Intel FPGA IP Design Example Izilingisi ezisekelwayo

Isifanisi	I-HDL ye-Verilog	I-VHDL
I-ModelSim – Intel FPGA Edition/ ModelSim – Intel FPGA Starter Edition	Yebo	Yebo
I-VCS/VCS MX	Yebo	Yebo
I-Riviera-PRO	Yebo	Yebo
I-Xcelium Parallel	Yebo	Cha

2.14. Ukulinganiselwa Kwedizayini
Udinga ukucabangela imikhawulo ethile lapho ufaka i-HDMI 2.1 design example.

• I-TX ayikwazi ukusebenza ngemodi ye-TMDS uma ikumodi yokungadluli. Ukuze uhlole kumodi ye-TMDS, guqula ukushintsha komsebenzisi_dipsw ubuyele kumodi yokudlula.
• Iphrosesa ye-Nios II kufanele inikeze ukuqeqeshwa kwesixhumanisi se-TX ukuze kuqedwe ngaphandle kokuphazamiseka kwezinye izinqubo.

2.15. Izici zokulungisa iphutha
Lo mklamo exampi-le inikeza izici ezithile zokulungisa iphutha ukuze zikusize.
2.15.1. Umlayezo Wokulungisa Isofthiwe
Ungavula umlayezo wokulungisa iphutha kusofthiwe ukuze unikeze usizo lwesikhathi sokusebenza.
Ukuze uvule umlayezo wokulungisa iphutha kusofthiwe, landela lezi zinyathelo:

1. Shintsha i-DEBUG_MODE ibe ngu-1 kusikripthi se-global.h.
2. Qalisa iskripthi/build_sw.sh ku-Nios II Command Shell.
3. Hlela kabusha isofthiwe ekhiqiziwe/tx_control/tx_control.elf file ngokusebenzisa umyalo ku-Nios II Command Shell:
   nios2-landa -r -g software/tx_control/tx_control.elf
4. Qalisa umyalo wokugcina we-Nios II ku-Nios II Command Shell:
   nios2-theminali

Uma uvula umlayezo wokususa iphutha, ulwazi olulandelayo luyaphrinta:

• Izilungiselelo zokushayela kabusha kwe-TI kukho kokubili i-TX ne-RX ziyafundwa futhi ziboniswa kanye ngemva kokuhlela i-ELF file.
• Umlayezo wesimo sokucushwa kwe-RX EDID nenqubo ye-hotplug
• Isixazululo esinolwazi noma ngaphandle kwe-FRL yosekelo olukhishwe ku-EDID kusinki oxhunywe ku-TX. Lolu lwazi luboniswa kuwo wonke ama-hotplug we-TX.
• Umlayezo wesimo senqubo yokuqeqeshwa kwesixhumanisi se-TX phakathi nokuqeqeshwa kwesixhumanisi se-TX.

2.15.2. Ulwazi lwe-SCDC olusuka kusinki oluxhunywe ku-TX
Ungasebenzisa lesi sici ukuze uthole ulwazi lwe-SCDC.

1. Qalisa umyalo wokugcina we-Nios II ku-Nios II Command Shell: nios2-terminal
2. Cindezela okuthi user_pb[2] kukhithi yokuthuthukisa ye-Intel Arria 10 FPGA.

Isofthiwe ifunda futhi ibonise imininingwane ye-SCDC kusinki exhunywe ku-TX kutheminali ye-Nios II.
2.15.3. Iwashi Ukukalwa Frequency
Sebenzisa lesi sici ukuhlola imvamisa yamawashi ahlukene.

1. Ku-hdmi_rx_top naku-hdmi_tx_top files, susa amazwana “//`chaza DEBUG_EN 1”.
2. Engeza isignali ye-refclock_measure kusukela kusenzakalo ngasinye se-mr_rate_detect ukuya ku-Signal Tap Logic Analyzer ukuze uthole imvamisa yewashi ngalinye (ngesikhathi esingu-10 ms).
3. Hlanganisa idizayini nge-Signal Tap Logic Analyzer.
4. Hlela i-SOF file bese usebenzisa i-Signal Tap Logic Analyzer.

Ithebula 27. Amawashi

Imojuli	mr_rate_detect Instance	Iwashi Lizokalwa
hdmi_rx_top	rx_pll_tmds	Iwashi lereferensi le-RX CDR 0
	rx_clk0_freq	Iwashi le-transceiver le-RX liphuma esiteshini 0
	rx_vid_clk_freq	Iwashi levidiyo le-RX
	rx_frl_clk_freq	Iwashi le-RX FRL
	rx_hsync_freq	Imvamisa ye-Hsync yozimele wevidiyo owamukelwe
i-hdmi_tx_top	tx_clk0_freq	Iwashi le-TX transceiver liphuma esiteshini 0
	vid_clk_freq	Iwashi levidiyo le-TX
	frl_clk_freq	Iwashi le-TX FRL
	tx_hsync_freq	Imvamisa ye-Hsync yozimele wevidiyo okufanele idluliselwe

2.16. Ukuthuthukisa Idizayini Yakho
Ithebula 28. I-HDMI Design Example Ukuhambisana Nenguqulo Yesoftware Yangaphambilini ye-Intel Quartus Prime Pro Edition

I-Design Example Okuhlukile	Amandla Wokuthuthukela ku-Intel Quartus Prime Pro Edition 20.3
I-HDMI 2.1 Design Example (Ukusekela i-FRL = 1)	Cha

Ngokwanoma yimuphi umklamo ongahambelani exampngezansi, udinga ukwenza lokhu okulandelayo:

1. Khiqiza i-ex yedizayini entshaample enguqulweni yamanje yesofthiwe ye-Intel Quartus Prime Pro Edition usebenzisa ukulungiselelwa okufanayo komklamo wakho okhona.
2. Qhathanisa yonke i-ex yomklamoample lwemibhalo ne-ex designampikhiqizwe kusetshenziswa inguqulo yesoftware ye-Intel Quartus Prime Pro Edition yangaphambilini. Thumela izinguquko ezitholiwe.

I-HDMI 2.0 Design Example (Ukusekela i-FRL = 0)

I-HDMI Intel FPGA IP design exampI-le ibonisa i-loopback eyodwa ye-HDMI ehambisanayo ehlanganisa iziteshi ezintathu ze-RX neziteshi ezine ze-TX.
Ithebula 29. HDMI Intel FPGA IP Design Example ye-Intel Arria 10 Amadivayisi

I-Design Example	Isilinganiso Sedatha	Imodi Yesiteshi	Uhlobo lwe-Loopback
I-Arria 10 HDMI RX-TX Retransmit	< 6,000 Mbps	I-Simplex	Ihambisana ne-FIFO buffer

Izici

• Idizayini iqinisekisa amabhafa e-FIFO ukuze enze ukudlula kokusakaza kwevidiyo ye-HDMI eqondile phakathi kukasinki we-HDMI nomthombo.
  
• Idizayini isebenzisa isimo se-LED ukulungisa amaphutha kwangaphambi kwesikhathitage.
• Idizayini iza nezinketho ze-RX ne-TX kuphela.
• Idizayini ibonisa ukufakwa nokuhlunga kwe-Dynamic Range and Mastering (HDR) InfoFrame kumojula yesixhumanisi ye-RX-TX.
• Idizayini ibonisa ukuphathwa kokudlula kwe-EDID kusuka kusinki wangaphandle we-HDMI kuya kumthombo wangaphandle we-HDMI uma ucushwa umcimbi we-TX hot-plug.
• Idizayini ivumela ukulawula kwesikhathi ngokushintsha kwe-DIP kanye nenkinobho yokucindezela ukuze ulawule amasiginali ayinhloko we-HDMI TX:
  — Isignali yemodi ukukhetha i-DVI noma i-HDMI encoded video frame
  — info_avi[47], info_vsi[61], kanye ne-audio_info_ai[48] amasiginali wokukhetha ukuthunyelwa kwephakethe elisizayo ngamabhande aseceleni noma izimbobo zedatha ezisizayo

Isibonelo se-RX sithola umthombo wevidiyo ovela kujeneretha yevidiyo yangaphandle, bese idatha idlula ku-loopback FIFO ngaphambi kokuba idluliselwe ku-TX.
Udinga ukuxhuma isihlaziyi sevidiyo sangaphandle, imonitha, noma ithelevishini enoxhumano lwe-HDMI kumongo we-TX ukuze uqinisekise ukusebenza.
3.1. I-HDMI 2.0 RX-TX Retransmit Design Block Diagram
I-HDMI 2.0 RX-TX yokuthumela kabusha umklamo exampI-le ibonisa i-loopback ehambisanayo kumodi yesiteshi elula ye-HDMI Intel FPGA IP.
Umfanekiso 20. I-HDMI RX-TX Retransmit Block Diagram (Intel Quartus Prime Pro Edition)Umfanekiso 21. I-HDMI RX-TX Retransmit Block Diagram (Intel Quartus Prime Standard Edition)Ulwazi Oluhlobene
I-Jitter ye-PLL Cascading noma Indlela Yewashi Engazinikele Yewashi Lereferensi ye-Arria 10 PLL Bheka kulesi sixazululo ukuze uthole umsebenzi uma amawashi akho okuklama ezwa okwengeziwe.
jitha.
3.2. Izingxenyekazi zekhompuyutha nezidingo zeSoftware
I-Intel isebenzisa izingxenyekazi zekhompuyutha ezilandelayo nesofthiwe ukuhlola i-ex yedizayiniample.
Izingxenyekazi zekhompuyutha

• I-Intel Arria 10 GX FPGA Development Kit
• Umthombo we-HDMI (Iyunithi Yephrosesa Yezithombe (GPU))
• I-HDMI Sink (Monitor)
• Ikhadi lendodakazi le-Bitec HDMI FMC 2.0 (Isibuyekezo 11)
• Izintambo ze-HDMI

Qaphela:
Ungakhetha ukubuyekezwa kwekhadi lakho lendodakazi ye-Bitec HDMI. Setha ipharamitha yendawo BITEC_DAUGHTER_CARD_REV ukuze ibe 4, 6, noma 11 ezingeni eliphezulu file (a10_hdmi2_demo.v). Uma ushintsha isibuyekezo, idizayini ingase ishintshe amashaneli e-transceiver futhi iguqule i-polarity ngokuya ngezidingo zekhadi lendodakazi ye-Bitec HDMI. Uma usetha ipharamitha ye-BITEC_DAUGHTER_CARD_REV ibe ngu-0, idizayini ayenzi izinguquko kumashaneli e-transceiver kanye ne-polarity. Okokuklama kwe-HDMI 2.1 examples, ngaphansi kwe-Design Example thebhu, setha Ukubuyekezwa Kwekhadi Lendodakazi ye-HDMI libe yi-Revision 9, Revision 4, noma lingabi nalo ikhadi lendodakazi. Inani elizenzakalelayo yi-Revision 9.
Isofthiwe

• Inguqulo ye-Intel Quartus Prime 18.1 nakamuva (yokuhlola ihadiwe)
• ModelSim – Intel FPGA Edition, ModelSim – Intel FPGA Starter Edition, , RivieraPRO, VCS (Verilog HDL kuphela)/VCS MX, noma Xcelium Parallel simulator

3.3. Ukwakheka Kwemibhalo
Izikhombisi ziqukethe okukhiqiziwe files ye-HDMI Intel FPGA IP design example.
Umfanekiso 22. Ukwakheka Kwemibhalo Yomklamo ExampleIthebula 30. I-RTL Ekhiqiziwe Files

Amafolda	Files
gxb	• /gxb_rx.qsys (Intel Quartus Prime Standard Edition) • /gxb_rx.ip (Intel Quartus Prime Pro Edition)
	• /gxb_rx_reset.qsys (Intel Quartus Prime Standard Edition) • /gxb_rx_reset.ip (Intel Quartus Prime Pro Edition)
	• /gxb_tx.qsys (Intel Quartus Prime Standard Edition) • /gxb_tx.ip (Intel Quartus Prime Pro Edition)
	• /gxb_tx_fpll.qsys (Intel Quartus Prime Standard Edition) • /gxb_tx_fpll.ip (Intel Quartus Prime Pro Edition)
	• /gxb_tx_reset.qsys (Intel Quartus Prime Standard Edition) • /gxb_tx_reset.ip (Intel Quartus Prime Pro Edition)
i-hdmi_rx	•/hdmi_rx.qsys (Intel Quartus Prime Standard Edition) •/hdmi_rx.ip (Intel Quartus Prime Pro Edition)
	/hdmi_rx_top.v
	/mr_clock_sync.v (Intel Quartus Prime Standard Edition)
	/mr_hdmi_rx_core_top.v (Intel Quartus Prime Standard Edition)
	/mr_rx_oversample.v (Intel Quartus Prime Standard Edition)
	/symbol_aligner.v
	I-Panasonic.hex (Intel Quartus Prime Pro Edition)
i-hdmi_tx	• /hdmi_tx.qsys (Intel Quartus Prime Standard Edition) •/hdmi_tx.ip (Intel Quartus Prime Pro Edition)

	/hdmi_tx_top.v
	/mr_ce.v (Intel Quartus Prime Standard Edition)
	/mr_hdmi_tx_core_top.v (Intel Quartus Prime Standard Edition)
	/mr_tx_oversample.v (Intel Quartus Prime Standard Edition)
i2c_master (Intel Quartus Prime Standard Edition)	/i2c_master_bit_ctrl.v
	/i2c_master_byte_ctrl.v
	/i2c_master_defines.v
	/i2c_master_top.v
	/oc_i2c_master.v
	/oc_i2c_master_hw.tcl
	/isilinganiso sesikhathi.v
i2c_isigqila	/edid_ram.qsys (Intel Quartus Prime Standard Edition)
	/Panasonic.hex (Intel Quartus Prime Standard Edition)
	/i2c_avl_mst_intf_gen.v
	/i2c_clk_cnt.v
	/i2c_condt_det.v
	/i2c_databuffer.v
	/i2c_rxshifter.v
	/i2c_slvfsm.v
	/i2c_spksuppp.v
	/i2c_txout.v
	/i2c_txshifter.v
	/i2cslave_to_avlmm_bridge.v
i-pl	• /pll_hdmi.qsys (Intel Quartus Prime Standard Edition) • /pll_hdmi.ip (Intel Quartus Prime Pro Edition)
	• /pll_hdmi_reconfig.qsys (Intel Quartus Prime Standard Edition) • /pll_hdmi_reconfig.ip (Intel Quartus Prime Pro Edition)
	i-quartus.ini
evamile	• /clock_control.qsys (Intel Quartus Prime Standard Edition) • /clock_control.ip (Intel Quartus Prime Pro Edition)
	• /fifo.qsys (Intel Quartus Prime Standard Edition) • /fifo.ip (Intel Quartus Prime Pro Edition)
	• /output_buf_i2c.qsys (Intel Quartus Prime Standard Edition) •/output_buf_i2c.ip (Intel Quartus Prime Pro Edition)
	/reset_controller.qsys (Intel Quartus Prime Standard Edition)
	/clock_crosser.v

	dcfifo_inst.v
	debouncer.sv (Intel Quartus Prime Pro Edition)
hdr	/altera_hdmi_aux_hdr.v
	/altera_hdmi_aux_snk.v
	/altera_hdmi_aux_src.v
	/altera_hdmi_hdr_infoframe.v
	/avalon_st_mutiplexer.qsys
reconfig_mgmt	/mr_compare_pll.v
	/mr_compare_rx.v
	/mr_rate_detect.v
	/mr_reconfig_master_pll.v
	/mr_reconfig_master_rx.v
	/mr_reconfig_mgmt.v
	/mr_rom_pll_dprioaddr.v
	/mr_rom_pll_valuemask_8bpc.v
	/mr_rom_pll_valuemask_10bpc.v
	/mr_rom_pll_valuemask_12bpc.v
	/mr_rom_pll_valuemask_16bpc.v
	/mr_rom_rx_dprioaddr_bitmask.v
	/mr_rom_rx_valuemask.v
	/mr_state_machine.v
sdc	/a10_hdmi2.sdc
	/mr_reconfig_mgmt.sdc
	/jtag.sdc
	/rxtx_link.sdc
	/mr_clock_sync.sdc (Intel Quartus Prime Standard Edition)

Ithebula 31. Ukulingisa Okukhiqiziwe Files
Bheka isigaba seSimulation Testbench ukuze uthole ulwazi olwengeziwe.

Amafolda	Files
i-aldec	/aldec.do
	/rivierapro_setup.tcl
i-cadence	/cds.lib
	/hdl.var
	<cds_libs ifolda>

umeluleki	/mentor.do
	/msim_setup.tcl
ama-synopsy	/vcs/fileuhlu.f
	/vcs/vcs_setup.sh
	/vcs/vcs_sim.sh
	/vcsmx/vcsmx_setup.sh
	/vcsmx/vcsmx_sim.sh
	/vcsmx/synopsys_sim_setup
xcelium (Intel Quartus Prime Pro Edition)	/cds.lib
	/hdl.var
	/xcelium_setup.sh
	/xcelium_sim.sh
evamile (Intel Quartus Prime Pro Edition)	/imodeli_files.tcl
	/riviera_files.tcl
	/vcs_files.tcl
	/vcsmx_files.tcl
	/xcelium_files.tcl
i-hdmi_rx	• /hdmi_rx.qsys (Intel Quartus Prime Standard Edition) • /hdmi_rx.ip (Intel Quartus Prime Pro Edition)
	/hdmi_rx.sopcinfo (Intel Quartus Prime Standard Edition)
	/Panasonic.hex (Intel Quartus Prime Pro Edition)
	/symbol_aligner.v (Intel Quartus Prime Pro Edition)
i-hdmi_tx	• /hdmi_tx.qsys (Intel Quartus Prime Standard Edition) • /hdmi_tx.ip (Intel Quartus Prime Pro Edition)
	/hdmi_tx.sopcinfo (Intel Quartus Prime Standard Edition)

Ithebula 32.Isoftware Ekhiqiziwe Files

Amafolda	Files
tx_control_src Qaphela: Ifolda ye-tx_control iqukethe nezimpinda zalokhu files.	/intel_fpga_i2c.c (Intel Quartus Prime Pro Edition)
	/intel_fpga_i2c.h (Intel Quartus Prime Pro Edition)
	/i2c.c (Intel Quartus Prime Standard Edition)
	/i2c.h (Intel Quartus Prime Standard Edition)
	/okuyinhloko.c
	/xcvr_gpll_rcfg.c /xcvr_gpll_rcfg.h /ti_i2c.c (Intel Quartus Prime Standard Edition) /ti_i2c.h (Intel Quartus Prime Standard Edition)

3.4. Izingxenye Zokuklama
I-HDMI Intel FPGA IP design example idinga lezi zingxenye.
Ithebula 33. Izingxenye eziphezulu ze-HDMI RX

Imojuli	Incazelo
I-HDMI RX Core	I-IP ithola idatha ye-serial evela ku-Transceiver Native PHY futhi yenza ukuqondanisa kwedatha, i-channel deskew, ukuqoshwa kwe-TMDS, ukuqoshwa kwedatha eyinsiza, ukuqoshwa kwedatha yevidiyo, ukuqoshwa kwedatha yomsindo, nokuhlehlisa.
I2	I-I2C isixhumi esibonakalayo esisetshenziselwa iSink Display Data Channel (DDC) kanye Nesimo Nesiteshi Sedatha (SCDC). Umthombo we-HDMI usebenzisa i-DDC ukuze unqume amandla nezici zikasinki ngokufunda Uhlaka Lwedatha Yokuhlonza Isibonisi Esithuthukisiwe (E-EDID). • Amakheli esigqila angu-8-bit I2C e-E-EDID athi 0xA0 kanye no-0xA1. I-LSB ikhombisa uhlobo lokufinyelela: 1 ukufunda no-0 ukubhala. Uma kwenzeka umcimbi we-HPD, isigqila se-I2C siphendula idatha ye-E-EDID ngokufunda ku-RAM eku-chip. • Isilawuli se-I2C sesigqila kuphela siphinde sisekele i-SCDC ekusebenzeni kwe-HDMI 2.0. Ikheli lesigqila le-8-bit I2C le-SCDC lithi 0xA8 kanye no-0xA9. Uma kwenzeka umcimbi we-HPD, isigqila se-I2C senza umsebenzi wokubhala noma wokufunda ukuya noma ukusuka kusixhumanisi esibonakalayo se-SCDC somongo we-HDMI RX. Qaphela: Lesi silawuli se-I2C sesigqila kuphela se-SCDC asidingeki uma ngabe i-HDMI 2.0b ingahlosiwe. Uma uvula i- Faka i-I2C ipharamitha, leli bhulokhi lizofakwa ngaphakathi kwengqikithi futhi ngeke libonakale kuleli zinga.
I-EDID RAM	Idizayini igcina imininingwane ye-EDID isebenzisa i-RAM 1-port IP core. Iphrothokholi yebhasi ewuchungechunge enezintambo ezimbili (iwashi nedatha) idlulisa uhlaka lwedatha ye-CEA-2-D Ethobelana ne-E-EDID. Le EDID RAM igcina imininingwane ye-E-EDID. Qaphela: Uma uvula i- Faka i-EDID RAM ipharamitha, leli bhulokhi lizofakwa ngaphakathi kwengqikithi futhi ngeke libonakale kuleli zinga.
I-IOPLL	I-IOPLL ikhiqiza iwashi lereferensi le-RX CDR, iwashi lejubane lesixhumanisi, newashi levidiyo yewashi le-TMDS engenayo. • Iwashi eliphumayo 0 (iwashi lereferensi le-CDR) • Iwashi eliphumayo 1 (Xhumanisa iwashi lesivinini) • Iwashi eliphumayo 2 (Iwashi levidiyo) Qaphela: Ukucushwa okuzenzakalelayo kwe-IOPLL akuvumelekile kunoma yikuphi ukulungiswa kwe-HDMI. I-IOPLL iphinda ilungiselwe izilungiselelo ezifanele uma ikhanyisa.
I-Transceiver PHY Setha Kabusha Isilawuli	Isilawuli sokusetha kabusha i-Transceiver PHY siqinisekisa ukuqaliswa okuthembekile kwama-transceivers e-RX. Ukusetha kabusha okokufaka kwalesi silawuli kuqalwa ukulungiswa kabusha kwe-RX, futhi kukhiqiza isignali ehambisanayo yokusetha kabusha i-analog nedijithali kubhulokhi ye-Transceiver Native PHY ngokuya ngohlelo lokusetha kabusha ngaphakathi kwebhulokhi.
I-RX Native PHY	I-Hard transceiver block ethola idatha ye-serial emthonjeni wangaphandle wevidiyo. Isusa idatha ye-serial kudatha ehambisanayo ngaphambi kokudlulisa idatha kumongo we-HDMI RX.
I-RX Reconfiguration Management	Ukuphathwa kokulungiswa kabusha kwe-RX okusebenzisa ukutholwa kwesilinganiso sokujikeleza nge-HDMI PLL ukuze kushayele i-transceiver ye-RX ukuze isebenze nganoma yimaphi amanani esixhumanisi angenasizathu asuka ku-250 Mbps kuya ku-6,000 Mbps. Bheka uMdwebo 23 ekhasini 63 ngezansi.

Ukucushwa kabusha kwe-IOPLL

Ibhulokhi yokumisa kabusha ye-IOPLL isiza ukulungiselelwa kabusha kwesikhathi sangempela okuguquguqukayo kwama-PLL ku-Intel FPGAs. Leli bhulokhi libuyekeza imvamisa yewashi eliphumayo kanye nomkhawulokudonsa we-PLL ngesikhathi sangempela, ngaphandle kokumisa kabusha yonke i-FPGA. Le block isebenza ku-100 MHz kumadivayisi we-Intel Arria 10. Ngenxa yomkhawulo wokucushwa kabusha kwe-IOPLL, sebenzisa i-Quartus INI permit_nf_pll_reconfig_out_of_lock=on ngesikhathi sokukhiqiza kabusha kwe-IOPLL IP. Ukuze usebenzise i-Quartus INI, faka “permit_nf_pll_reconfig_out_of_lock=on” ku-quartus.ini file kanye nendawo file i-Intel Quartus Prime project directory. Kufanele ubone umlayezo oyisixwayiso lapho uhlela ibhulokhi yokumisa kabusha ye-IOPLL (pll_hdmi_reconfig) kusofthiwe ye-Quartus Prime nge-INI. Qaphela: Ngaphandle kwale Quartus INI, ukulungiswa kabusha kwe-IOPLL akukwazi ukuqedelwa uma i-IOPLL ilahlekelwa ukukhiya phakathi nokulungiswa kabusha.

I-PIO

Ibhulokhi ye-parallel input/output (PIO) isebenza njengokulawula, isimo nokusetha kabusha ukuxhumana okuya noma ukusuka kusistimu engaphansi ye-CPU.

Umfanekiso 23. Ukugeleza Kokulandelana Kokuhlela Kabusha Kwezilinganiso Eziningi
Isibalo sibonisa ukugeleza kokulandelana kokuhlelwa kabusha kwezilinganiso eziningi kwesilawuli lapho sithola ukusakaza kwedatha yokokufaka kanye nemvamisa yewashi lesithenjwa, noma uma i-transceiver ivuliwe.Ithebula 34. Izingxenye eziphezulu ze-HDMI TX

Imojuli	Incazelo
I-HDMI TX Core	I-IP core ithola idatha yevidiyo esuka ezingeni eliphezulu futhi yenza umbhalo wekhodi we-TMDS, ukufakwa kwekhodi kwedatha eyisizayo, ukubhala ngekhodi kwedatha yomsindo, ukubhala ngekhodi idatha yevidiyo, nokuphenya.
I-I2C Master	I-I2C isixhumi esibonakalayo esisetshenziselwa iSink Display Data Channel (DDC) kanye Nesimo Nesiteshi Sedatha (SCDC). Umthombo we-HDMI usebenzisa i-DDC ukuze unqume amandla nezici zikasinki ngokufunda Uhlaka Lwedatha Yokuhlonza Isibonisi Esithuthukisiwe (E-EDID). • Njenge-DDC, i-I2C Master ifunda i-EDID kusinki wangaphandle ukuze ilungiselele ulwazi lwe-EDID i-EDID RAM ku-HDMI RX Top noma ukucubungula ividiyo. • Njenge-SCDC, i-I2C master idlulisela ukwakheka kwedatha ye-SCDC isuka kumthombo we-FPGA iye kusinki yangaphandle ukuze isebenze i-HDMI 2.0b. Okwesiboneloampfuthi, uma ukusakaza kwedatha okuphumayo kungaphezu kuka-3,400 Mbps, iphrosesa ye-Nios II iyala inkosi ye-I2C ukuthi ibuyekeze amabhithi e-TMDS_BIT_CLOCK_RATIO kanye ne-SCRAMBLER_ENABLE erejista yokucushwa ye-SCDC kasinki ibe ngu-1.
I-IOPLL	I-IOPLL ihlinzeka ngewashi lejubane lesixhumanisi newashi levidiyo kusuka ewashini le-TMDS engenayo. • Iwashi eliphumayo 1 (Xhumanisa iwashi lesivinini) • Iwashi eliphumayo 2 (Iwashi levidiyo) Qaphela: Ukucushwa okuzenzakalelayo kwe-IOPLL akuvumelekile kunoma yikuphi ukulungiswa kwe-HDMI. I-IOPLL iphinda ilungiselwe izilungiselelo ezifanele uma ikhanyisa.
I-Transceiver PHY Setha Kabusha Isilawuli	Isilawuli sokusetha kabusha i-Transceiver PHY siqinisekisa ukuqaliswa okuthembekile kwama-transceiver e-TX. Ukusetha kabusha okokufaka kwalesi silawuli kuqalwa kusuka ezingeni eliphezulu, futhi kukhiqiza isignali ehambisanayo yokusetha kabusha i-analog nedijithali kubhulokhi ye-Transceiver Native PHY ngokuya ngohlelo lokusetha kabusha ngaphakathi kwebhulokhi. Isignali ephumayo engu-tx_ready esuka kule bhulokhi iphinde isebenze njengesignali yokusetha kabusha ku-HDMI Intel FPGA IP ukukhombisa ukuthi i-transceiver iyasebenza, futhi isilungele ukwamukela idatha kusuka kumongo.
I-Transceiver Native PHY	I-Hard transceiver block ethola idatha ehambisanayo evela kumongo we-HDMI TX futhi ihlela idatha ngokuyidlulisela. Isixhumi esibonakalayo sokumisa kabusha sinikwe amandla kubhulokhi ye-TX Native PHY ukubonisa ukuxhumana phakathi kwe-TX Native PHY kanye ne-transceiver arbiter. Akukho ukucushwa kabusha okwenziwa ku-TX Native PHY. Qaphela: Ukuze uhlangabezane nemfuneko ye-HDMI TX inter-channel skew, setha inketho yemodi yebhondi yesiteshi se-TX kusihleli sepharamitha ye-Intel Arria 10 Transceiver Native PHY ukuze Ukuhlanganiswa kwe-PMA ne-PCS. Udinga futhi ukwengeza imfuneko enkulu ye-skew (set_max_skew) kusignali yokusetha kabusha idijithali evela kusilawuli sokusetha kabusha i-transceiver (tx_digitalreset) njengoba kunconyiwe ku- Intel Arria 10 Transceiver PHY Umhlahlandlela Womsebenzisi.
I-TX PLL	Ibhulokhi yokudlulisa i-PLL inikeza iwashi elisheshayo le-serial kubhulokhi ye-Transceiver Native PHY. Kulo mklamo we-HDMI Intel FPGA IP example, fPLL isetshenziswa njenge-TX PLL.
Ukucushwa kabusha kwe-IOPLL	Ibhulokhi yokumisa kabusha ye-IOPLL isiza ukulungiselelwa kabusha kwesikhathi sangempela okuguquguqukayo kwama-PLL ku-Intel FPGAs. Leli bhulokhi libuyekeza imvamisa yewashi eliphumayo kanye nomkhawulokudonsa we-PLL ngesikhathi sangempela, ngaphandle kokumisa kabusha yonke i-FPGA. Le block isebenza ku-100 MHz kumadivayisi we-Intel Arria 10. Ngenxa yomkhawulo wokucushwa kabusha kwe-IOPLL, sebenzisa i-Quartus INI permit_nf_pll_reconfig_out_of_lock=on ngesikhathi sokukhiqiza kabusha kwe-IOPLL IP. Ukuze usebenzise i-Quartus INI, faka “permit_nf_pll_reconfig_out_of_lock=on” ku-quartus.ini file kanye nendawo file i-Intel Quartus Prime project directory. Kufanele ubone umlayezo oyisixwayiso lapho uhlela ibhulokhi yokumisa kabusha ye-IOPLL (pll_hdmi_reconfig) kusofthiwe ye-Intel Quartus Prime nge-INI. Qaphela: Ngaphandle kwale Quartus INI, ukulungiswa kabusha kwe-IOPLL akukwazi ukuqedelwa uma i-IOPLL ilahlekelwa ukukhiya phakathi nokulungiswa kabusha.
I-PIO	Ibhulokhi ye-parallel input/output (PIO) isebenza njengokulawula, isimo nokusetha kabusha ukuxhumana okuya noma ukusuka kusistimu engaphansi ye-CPU.

Ithebula 35. Isilinganiso sedatha ye-Transceiver nama-OverampI-ling Factor ye-TMDS Clock Frequency Range Ngayinye

I-TMDS Clock Frequency (MHz)	Isilinganiso sewashi elincane le-TMDS	overampLing Factor	Isilinganiso sedatha ye-Transceiver (Mbps)
85–150	1	Akufaneleki	3400–6000
100–340	0	Akufaneleki	1000–3400
50–100	0	5	2500–5000
35–50	0	3	1050–1500
30–35	0	4	1200–1400
25–30	0	5	1250–1500

Ithebula 36. Amabhulokhi Ajwayelekile Ezinga eliphezulu

Imojuli

Incazelo

I-Transceiver Arbiter

Le block esebenzayo ivimbela ama-transceiver ekuzilungiseni kabusha ngesikhathi esisodwa lapho ama-transceiver e-RX noma e-TX ngaphakathi kwesiteshi esingokoqobo esifanayo edinga ukulungiswa kabusha. Ukulungisa kanyekanye kuthinta izinhlelo zokusebenza lapho ama-transceiver e-RX ne-TX ngaphakathi kwesiteshi esifanayo abelwa ekusetshenzisweni okuzimele kwe-IP. Lesi sixazululi se-transceiver siyisandiso sesinqumo esinconyelwe ukuhlanganisa i-simplex TX ne-simplex RX esiteshini esifanayo somzimba. Lesi sixazululi se-transceiver siphinde sisize ekuhlanganiseni nasekuxazululeni izicelo zokulungiswa kabusha kwe-Avalon-MM RX kanye ne-TX eziqondise ama-transceivers e-simplex RX kanye ne-TX ngaphakathi kwesiteshi njengoba imbobo yokuhlanganisa yokuhlela kabusha yama-transceivers ingafinyelelwa ngokulandelana. Ukuxhumana phakathi kwe-transceiver arbiter kanye ne-TX/RX Native PHY/PHY Setha Kabusha Isilawuli kuvimbe kulesi sici somklamo.ampi-le ibonisa imodi ejwayelekile esebenza kunoma iyiphi inhlanganisela ye-IP kusetshenziswa i-transceiver arbiter. I-transceiver arbiter ayidingeki uma kuphela i-RX noma i-TX transceiver esetshenziswa esiteshini. Umxazululi we-transceiver ukhomba umfakisicelo wokulungiselelwa kabusha ngokusebenzisa i-Avalon-MM yayo yokusetha kabusha interface futhi iqinisekisa ukuthi i-tx_reconfig_cal_busy ehambisanayo noma i-rx_reconfig_cal_busy ifakwe isango ngokufanele. Ngohlelo lwe-HDMI, i-RX kuphela eqala ukumisa kabusha. Ngokuthumela isicelo sokulungiswa kabusha kwe-Avalon-MM ngomxazululi, umlamuli ukhomba ukuthi isicelo sokumisa kabusha sisuka ku-RX, ebese ivula i-tx_reconfig_cal_busy ekugomeleni futhi ivumele i-rx_reconfig_cal_busy ukuthi igomele. Isango livimbela i-transceiver ye-TX ukuthi ihanjiswe kumodi yokulinganisa ngokungenhloso.

	Qaphela: Ngenxa yokuthi i-HDMI idinga ukulungiswa kabusha kwe-RX kuphela, amasiginali we-tx_reconfig_mgmt_* avaliwe. Futhi, isixhumi esibonakalayo se-Avalon-MM azidingeki phakathi kwe-arbiter kanye nebhulokhi ye-TX Native PHY. Amabhulokhi abelwa ku-interface ku-ex designample ukuze ubonise uxhumano lwe-generic transceiver arbiter ku-TX/RX Native PHY/PHY Isilawuli Sokusetha Kabusha.
Isixhumanisi se-RX-TX	• Idatha yevidiyo ephumayo namasignali okuvumelanisa asuka ku-HDMI RX core loop nge-DCFIFO kuzo zonke izizinda zewashi levidiyo ye-RX ne-TX. • I-General Control Packet (GCP), InfoFrames (AVI, VSI ne-AI), idatha eyisiza, ne-loop yedatha yomsindo ngama-DCFIFO kuzo zonke izizinda zewashi lejubane le-RX ne-TX. • Imbobo yedatha eyisiza ye-HDMI TX core ilawula idatha eyisizayo egeleza ku-DCFIFO ngokucindezela emuva. I-backpressure iqinisekisa ukuthi alikho iphakethe elisizayo elingaphelele kuchweba ledatha elisizayo. • Le block futhi yenza ukuhlunga kwangaphandle: — Ihlunga idatha yomsindo nephakethe lokuvuselela iwashi elisuka emfudlaneni wedatha oyisizayo ngaphambi kokudlulisela embobeni yedatha eyinsiza ye-HDMI TX. Qaphela: Ukuze ukhubaze lokhu kuhlunga, cindezela umsebenzisi_pb[2]. Nika amandla lokhu kuhlunga ukuze uqiniseke ukuthi ayikho impinda yedatha yomsindo nephakethe lokukhiqiza kabusha iwashi lomsindo ekusakazeni kabusha kwedatha eyinsiza. - Ihlunga i-High Dynamic Range (HDR) InfoFrame isuka kudatha ye-HDMI RX eyisiza bese ifaka i-ex.ample-HDR InfoFrame kudatha eyisiza ye-HDMI TX ngokusebenzisa i-multiplexer ye-Avalon ST.
I-CPU Sub-System	I-sub-system ye-CPU isebenza njengezilawuli ze-SCDC ne-DDC, nesilawuli sokusetha kabusha umthombo. • Isilawuli se-SCDC somthombo siqukethe isilawuli esiyinhloko se-I2C. Isilawuli esiyinhloko se-I2C sidlulisela ukwakheka kwedatha ye-SCDC ukusuka kumthombo we-FPGA kuya kusinki wangaphandle ukuze usebenze nge-HDMI 2.0b. Okwesiboneloampfuthi, uma ukusakazwa kwedatha okuphumayo kungu-6,000 Mbps, iphrosesa ye-Nios II iyala isilawuli esiyinhloko se-I2C ukuthi sibuyekeze amabhithi e-TMDS_BIT_CLOCK_RATIO kanye ne-SCRAMBLER_ENABLE erejista yokucushwa ye-TMDS kasinki ibe ngu-1. • I-I2C master efanayo iphinde idlulise ukwakheka kwedatha ye-DDC (E-EDID) phakathi komthombo we-HDMI nosinki wangaphandle. • I-Nios II CPU isebenza njengesilawuli sokuhlela kabusha somthombo we-HDMI. I-CPU incike ekutholweni kwesilinganiso sezikhathi ezithile kusuka kumojula Yokulawula Ukulungisa Kabusha kwe-RX ukuze inqume ukuthi i-TX idinga ukulungiswa kabusha. Umhumushi wesigqila we-Avalon-MM unikeza ukuxhumana phakathi kwephrosesa ye-Nios II ye-Avalon-MM master interface kanye ne-Avalon-MM yesigqila se-Avalon-MM yomthombo wangaphandle we-HDMI we-IOPLL kanye ne-TX Native PHY. • Ukugeleza kokulandelana kokuhlelwa kabusha kwe-TX kuyafana ne-RX, ngaphandle kokuthi ukulungiselelwa kabusha kwe-PLL ne-transceiver kanye nokulandelana kokusetha kabusha kwenziwa ngokulandelana. Bheka Umfanekiso 24 ekhasini 67.

Umfanekiso 24. Ukugeleza Kokulandelana Kokuhlela Kabusha
Isibalo sibonisa ukugeleza kwesoftware ye-Nios II ebandakanya izilawuli ze-I2C master kanye nomthombo we-HDMI.3.5. I-Dynamic Range and Mastering (HDR) Ukufakwa Nokuhlunga Kwe-InfoFrame
I-HDMI Intel FPGA IP design example ihlanganisa ukuboniswa kokufakwa kwe-HDR InfoFrame kusistimu ye-loopback ye-RX-TX.
Inguqulo ye-HDMI Specification 2.0b ivumela i-Dynamic Range kanye ne-Mastering InfoFrame ukuthi idluliselwe ngokusakaza okuwusizo kwe-HDMI. Embukisweni, ibhulokhi Yokufaka Idatha Esizayo isekela ukufakwa kwe-HDR. Udinga kuphela ukufometha iphakethe le-HDR InfoFrame elihlosiwe njengoba kucaciswe kuthebula lohlu lwesiginali yemojuli futhi usebenzise imojuli enikeziwe Yokulawula Ukufakwa Kwe-AUX ukuze uhlele ukufakwa kwe-HDR InfoFrame kanye nozimele wevidiyo.
Kulesi example ukucushwa, ezimeni lapho ukusakaza okuyisizayo okungenayo sekuvele kufaka i-HDR InfoFrame, okuqukethwe kwe-HDR okusakazwayo kuyahlungwa. Ukuhlunga kugwema ukungqubuzana kwe-HDR InfoFrames ukuthi idluliselwe futhi kuqinisekisa ukuthi amanani kuphela ashiwo ku-HDR S.ample Data module zisetshenziswa.
Umfanekiso 25. Isixhumanisi se-RX-TX ne-Dynamic Range kanye nokufakwa kwe-Mastering InfoFrame
Isibalo sibonisa umdwebo webhlokhi wesixhumanisi se-RX-TX ohlanganisa i-Dynamic Range kanye nokufakwa kwe-Mastering InfoFrame ekusakazeni okuyinhloko kwe-HDMI TX.
Ithebula 37. I-Axiliary Data Insertion Block (altera_hdmi_aux_hdr) Amasignali

Isiginali	Isiqondiso	Ububanzi	Incazelo
Iwashi bese usetha kabusha
clk	Okokufaka	1	Okokufaka kwewashi. Leli washi kufanele lixhunywe ewashi lesivinini sesixhumanisi.
setha kabusha	Okokufaka	1	Setha kabusha okokufaka.

I-Axiliary Packet Generator kanye ne-Multiplexer Signals
multiplexer_out_data	Okukhiphayo	72	Okuphumayo kokusakaza kwe-Avalon kusuka ku-multiplexer.
i-multiplexer_out_valid	Okukhiphayo	1
multiplexer_out_ready	Okukhiphayo	1
multiplexer_out_startofpacket	Okukhiphayo	1
multiplexer_out_endofpacket	Okukhiphayo	1
multiplexer_out_channel	Okukhiphayo	11
multiplexer_in_data	Okokufaka	72	Okokufaka kokusakaza kwe-Avalon ku-In1 port ye-multiplexer. I-HDMI TX Video Vsync. Lesi siginali kufanele ivunyelaniswe kusizinda sewashi lesivinini sesixhumanisi. Ingqikithi ifaka i-HDR InfoFrame ekusakazeni okuyisizayo emaphethelweni akhuphukayo ale siginali.
i-multiplexer_in_valid	Okokufaka	1
multiplexer_in_ready	Okokufaka	1
multiplexer_in_startofpacket	Okokufaka	1
multiplexer_in_endofpacket hdmi_tx_vsync	Okokufaka Okokufaka	1 1

Ithebula 38. I-HDR Data Module (altera_hdmi_hdr_infoframe) Amasignali

Isiginali	Isiqondiso	Ububanzi	Incazelo
hb0	Okukhiphayo	8	I-header byte 0 ye-Dynamic Range kanye ne-Mastering InfoFrame: ikhodi yohlobo lwe-InfoFrame.
hb1	Okukhiphayo	8	I-header byte 1 ye-Dynamic Range kanye ne-Mastering InfoFrame: inombolo yenguqulo ye-InfoFrame.
hb2	Okukhiphayo	8	I-header byte 2 ye-Dynamic Range kanye ne-Mastering InfoFrame: Ubude be-InfoFrame.
pb	Okokufaka	224	Idatha byte ye-Dynamic Range kanye ne-Mastering InfoFrame.

Ithebula 39. I-Dynamic Range kanye ne-Mastering InfoFrame Data Byte Bundle Bit-Fields

I-Bit-Field	Incazelo	Uhlobo 1 lwemethadatha emile
7:0	Idatha Byte 1: {5'h0, EOTF[2:0]}
15:8	Idatha Byte 2: {5'h0, Static_Metadata_Descriptor_ID[2:0]}
23:16	Ibhayithi Yedatha 3: Static_Metadata_Descriptor	display_primaries_x[0], LSB
31:24	Ibhayithi Yedatha 4: Static_Metadata_Descriptor	display_primaries_x[0], MSB
39:32	Ibhayithi Yedatha 5: Static_Metadata_Descriptor	display_primaries_y[0], LSB
47:40	Ibhayithi Yedatha 6: Static_Metadata_Descriptor	display_primaries_y[0], MSB
55:48	Ibhayithi Yedatha 7: Static_Metadata_Descriptor	display_primaries_x[1], LSB
63:56	Ibhayithi Yedatha 8: Static_Metadata_Descriptor	display_primaries_x[1], MSB
71:64	Ibhayithi Yedatha 9: Static_Metadata_Descriptor	display_primaries_y[1], LSB
79:72	Ibhayithi Yedatha 10: Static_Metadata_Descriptor	display_primaries_y[1], MSB
87:80	Ibhayithi Yedatha 11: Static_Metadata_Descriptor	display_primaries_x[2], LSB
95:88	Ibhayithi Yedatha 12: Static_Metadata_Descriptor	display_primaries_x[2], MSB
103:96	Ibhayithi Yedatha 13: Static_Metadata_Descriptor	display_primaries_y[2], LSB
111:104	Ibhayithi Yedatha 14: Static_Metadata_Descriptor	display_primaries_y[2], MSB
119:112	Ibhayithi Yedatha 15: Static_Metadata_Descriptor	white_point_x, LSB
127:120	Ibhayithi Yedatha 16: Static_Metadata_Descriptor	white_point_x, MSB
135:128	Ibhayithi Yedatha 17: Static_Metadata_Descriptor	white_point_y, LSB

143:136	Ibhayithi Yedatha 18: Static_Metadata_Descriptor	white_point_y, MSB
151:144	Ibhayithi Yedatha 19: Static_Metadata_Descriptor	max_display_mastering_luminance, LSB
159:152	Ibhayithi Yedatha 20: Static_Metadata_Descriptor	max_display_mastering_luminance, MSB
167:160	Ibhayithi Yedatha 21: Static_Metadata_Descriptor	min_display_mastering_luminance, LSB
175:168	Ibhayithi Yedatha 22: Static_Metadata_Descriptor	min_display_mastering_luminance, MSB
183:176	Ibhayithi Yedatha 23: Static_Metadata_Descriptor	Izinga Lokukhanya Lokuqukethwe Okuphezulu, LSB
191:184	Ibhayithi Yedatha 24: Static_Metadata_Descriptor	Izinga Lokukhanya Lokuqukethwe Okuphezulu, i-MSB
199:192	Ibhayithi Yedatha 25: Static_Metadata_Descriptor	I-Maximum Frame-average Light Level, LSB
207:200	Ibhayithi Yedatha 26: Static_Metadata_Descriptor	Ileveli Yokukhanya Okumaphakathi Okumaphakathi, i-MSB
215:208	Igodliwe
223:216	Igodliwe

Ikhubaza Ukufakwa Nokuhlunga kwe-HDR
Ukukhubaza ukufakwa nesihlungi se-HDR kukwenza ukwazi ukuqinisekisa ukudluliswa kabusha kokuqukethwe kwe-HDR osekuvele kutholakala kumthombo wokusakaza osizayo ngaphandle kokuguqulwa kwanoma yikuphi ukuguqulwa ku-design ye-RX-TX Retransmit ex.ample.
Ukuze ukhubaze ukufakwa nokuhlunga kwe-HDR InfoFrame:

1. Setha i-block_ext_hdr_infoframe ibe ngu-1'b0 kokuthi rxtx_link.v file ukuze uvimbele ukuhlungwa kwe-HDR InfoFrame kusukela ekusakazeni kwe-Axiliary.
2. Setha i-multiplexer_in0_valid ye-avalon_st_multiplexer ku-altera_hdmi_aux_hdr.v file kuya ku-1'b0 ukuze kuvinjelwe i-Axiliary Packet Generator ekwenzeni futhi ifake i-HDR InfoFrame eyengeziwe ekusakazeni kwe-TX kwe-Axiliary.
   

3.6. Uhlelo Lokuvala
Isikimu sewashi sibonisa izizinda zewashi ku-HDMI Intel FPGA IP design example.
Umfanekiso 26. HDMI Intel FPGA IP Design ExampI-le Clock Scheme (Intel Quartus Prime Pro Edition)Umfanekiso 27. HDMI Intel FPGA IP Design ExampI-le Clock Scheme (Intel Quartus Prime Standard Edition)Ithebula 40. Izimpawu Zohlelo Lokuvala

Iwashi	Igama Lesiginali Kudizayini	Incazelo
TX IOPLL/TX PLL Reference Clock 1	hdmi_clk_in	Iwashi lereferensi ku-TX IOPLL ne-TX PLL. Ifrikhwensi yewashi iyafana nefrikhwensi yewashi ye-TMDS elindelwe evela esiteshini sewashi se-HDMI TX TMDS. Kulo mklamo we-HDMI Intel FPGA IP exampfuthi, leli washi lixhunywe ewashini le-RX TMDS ngenjongo yokubonisa. Kuhlelo lwakho lokusebenza, udinga ukunikeza iwashi elizinikele elinefrikhwensi yewashi le-TMDS kusuka ku-oscillator ehlelekayo ukuze uthole ukusebenza okungcono kwe-jitter. Qaphela: Ungasebenzisi i-transceiver RX pin njengewashi lereferensi le-TX PLL. Idizayini yakho izohluleka ukulingana uma ubeka i-HDMI TX refclk kuphinikhodi ye-RX.
Iwashi le-TX Transceiver Out	tx_clk	Iwashi eliphumayo elitholiwe ku-transceiver, futhi imvamisa iyahlukahluka kuye ngezinga ledatha nezimpawu ngewashi ngalinye. I-TX transceiver clock out frequency = Isilinganiso sedatha ye-Transceiver/ (Uphawu ngewashi ngalinye*10)
TX PLL Serial Clock	tx_bonding_clocks	Iwashi le-serial elisheshayo elakhiwe yi-TX PLL. Ifrikhwensi yewashi isethwe ngokusekelwe esilinganisweni sedatha.
TX/RX Link Speed ​​Clock	ls_clk	Xhumanisa iwashi lesivinini. Ifrikhwensi yewashi lejubane lesixhumanisi incike kumafrikhwensi ewashi e-TMDS alindelekile, ama-oversampi-ling factor, izimpawu ngewashi ngalinye, kanye nesilinganiso sewashi lebhithi le-TMDS.

		I-TMDS Bit Clock Ratio	Xhumanisa Isivinini Sewashi Frequency
		0	Ubuningi bewashi le-TMDS/ Uphawu ngewashi ngalinye
		1	Imvamisa yewashi le-TMDS *4 / Uphawu ngewashi ngalinye
Iwashi levidiyo le-TX/RX	vid_clk	Iwashi ledatha yevidiyo. Imvamisa yewashi ledatha yevidiyo isuselwa ewashini lejubane lesixhumanisi se-TX ngokusekelwe ekujuleni kombala.
		I-TMDS Bit Clock Ratio	Iwashi Ledatha Yevidiyo
		0	Iwashi le-TMDS/ Uphawu ngewashi ngalinye/ Isici sokujula kombala
		1	Iwashi le-TMDS *4 / Uphawu ngewashi ngalinye/ Isici sokujula kombala
		Amabhithi ngombala ngamunye	Isici Sokujula Kombala
		8	1
		10	1.25
		12	1.5
		16	2.0
Iwashi le-RX TMDS	tmds_clk_in	Isiteshi sewashi se-TMDS sisuka ku-HDMI RX futhi sixhuma ewashini lesithenjwa ku-IOPLL.
I-RX CDR Reference Clock 0 /TX PLL Reference Clock 0	fr_clk	Iwashi lereferensi elisebenzayo lamahhala ku-RX CDR ne-TX PLL. Leli washi liyadingeka ukuze kulungiswe amandla.
RX CDR Reference Clock 1	iopll_outclk0	Iwashi eliyisethenjwa ku-RX CDR ye-transceiver ye-RX.
		Isilinganiso Sedatha	I-RX Reference Clock Frequency
		Izinga ledatha <1 Gbps	5× TMDS iwashi imvamisa
		1 Gbps< Izinga ledatha <3.4 Gbps	Imvamisa yewashi le-TMDS
		Izinga ledatha >3.4 Gbps	4× TMDS iwashi imvamisa
		• Izinga ledatha <1 Gbps: Okweqileampling ukuze uhlangabezane nemfuneko yesilinganiso esincane sedatha ye-transceiver. • Izinga Ledatha >3.4 Gbps: Ukunxephezela isilinganiso sebhithi ye-TMDS ukuya kwesilinganiso sewashi esingu-1/40 ukuze kugcinwe isilinganiso sedatha ye-transceiver kuya kusilinganiso sewashi ku-1/10. Qaphela: Ungasebenzisi iphinikhodi ye-transceiver RX njengewashi lereferensi le-CDR. Idizayini yakho izohluleka ukulingana uma ubeka i-HDMI RX refclk kuphinikhodi ye-RX.
I-RX Transceiver Clock Out	rx_clk	Iwashi eliphumayo elitholiwe ku-transceiver, futhi imvamisa iyahlukahluka kuye ngezinga ledatha nezimpawu ngewashi ngalinye. I-RX transceiver clock out frequency = Isilinganiso sedatha ye-Transceiver/ (Uphawu ngewashi ngalinye*10)
Iwashi Lokuphatha	mgmt_clk	Iwashi elisebenza mahhala elingu-100 MHz kulezi zingxenye:

		• Izixhumanisi ze-Avalon-MM ukuze zilungiswe kabusha - Imfuneko yobubanzi befrikhwensi iphakathi kuka-100-125 MHz. •, PHY setha kabusha isilawuli sokulandelana kokusetha kabusha kwe-transceiver - Imfuneko yobubanzi befrikhwensi iphakathi kuka-1-500 MHz. • Ukumiswa kabusha kwe-IOPLL - Imvamisa yewashi ephezulu ngu-100 MHz. • Ukumiswa kabusha kwe-RX kokuphatha • CPU • I-I2C Master
I2C Iwashi	i2c_cl	Okokufaka kwewashi okungu-100 MHz okufaka isigqila se-I2C, irejista ye-SCDC kumongo we-HDMI RX, kanye ne-EDID RAM.

Ulwazi Oluhlobene

• Kusetshenziswa i-Transceiver RX Pin njenge-CDR Reference Clock
• Kusetshenziswa i-Transceiver RX Pin njenge-TX PLL Reference Clock

3.7. Izimpawu Zokuxhumana
Amathebula aklelisa amasiginali we-HDMI Intel FPGA IP design example.
Ithebula 41. Izimpawu Zezinga eliphezulu

Isiginali	Isiqondiso	Ububanzi	Incazelo
Isiginali ye-Oscillator esebhodini
clk_fpga_b3_p	Okokufaka	1	100 MHz iwashi eligijima lamahhala lewashi eliyinkomba eliyinhloko
REFCLK_FMCB_P (Intel Quartus Prime Pro Edition)	Okokufaka	1	625 MHz iwashi eligijima lamahhala lewashi lereferensi ye-transceiver; leli washi lingaba lanoma iyiphi imvamisa

Izinkinobho Zokusunduza Zomsebenzisi nama-LED
umsebenzisi_pb	Okokufaka	1	Cindezela inkinobho ukuze ulawule ukusebenza komklamo we-HDMI Intel FPGA IP
cpu_resetn	Okokufaka	1	Ukusetha kabusha umhlaba
umsebenzisi_led_g	Okukhiphayo	4	Isibonisi se-LED eluhlaza Bheka Ukusethwa kwezingxenyekazi zekhompuyutha ekhasini 89 ukuze uthole ulwazi olwengeziwe mayelana nemisebenzi ye-LED.
umsebenzisi_led_r	Okukhiphayo	4	Isibonisi se-LED esibomvu Bheka Ukusethwa kwezingxenyekazi zekhompuyutha ekhasini 89 ukuze uthole ulwazi olwengeziwe mayelana nemisebenzi ye-LED.

Izikhonkwane zekhadi lendodakazi le-HDMI le-FMC ku-FMC Port B
fmcb_gbtclk_m2c_p_0	Okokufaka	1	Iwashi le-HDMI RX TMDS
fmcb_dp_m2c_p	Okokufaka	3	Iziteshi zedatha ze-HDMI RX ezibomvu, eziluhlaza, neziluhlaza okwesibhakabhaka • Ukubuyekezwa kwekhadi lendodakazi ye-Bitec 11 — [0]: Isiteshi 1 se-RX TMDS (Siluhlaza) — [1]: Isiteshi 2 se-RX TMDS (Bomvu) — [2]: RX TMDS Channel 0 (Blue) • Ukubuyekezwa kwekhadi lendodakazi le-Bitec 4 noma 6 — [0]: Isiteshi 1 se-RX TMDS (Esiluhlaza)— i-polarity ihlanekezelwe — [1]: RX TMDS Channel 0 (Blue)— i-polarity ihlanekezelwe — [2]: Isiteshi 2 se-RX TMDS (Okubomvu)— i-polarity ihlanekezelwe
fmcb_dp_c2m_p	Okukhiphayo	4	Iwashi le-HDMI TX, amashaneli edatha abomvu, aluhlaza, naluhlaza okwesibhakabhaka • Ukubuyekezwa kwekhadi lendodakazi ye-Bitec 11 — [0]: Isiteshi 2 se-TX TMDS (Bomvu) — [1]: Isiteshi 1 se-TX TMDS (Siluhlaza) — [2]: TX TMDS Channel 0 (Blue) — [3]: Isiteshi sewashi se-TX TMDS • Ukubuyekezwa kwekhadi lendodakazi le-Bitec 4 noma 6 — [0]: Isiteshi sewashi se-TX TMDS — [1]: TX TMDS Channel 0 (Blue) — [2]: Isiteshi 1 se-TX TMDS (Siluhlaza) — [3]: Isiteshi 2 se-TX TMDS (Bomvu)
fmcb_la_rx_p_9	Okokufaka	1	Ukutholwa kwamandla kwe-HDMI RX +5V
fmcb_la_rx_p_8	Inout	1	Ukutholwa kwepulagi eshisayo ye-HDMI RX
fmcb_la_rx_n_8	Inout	1	I-HDMI RX I2C SDA ye-DDC ne-SCDC
fmcb_la_tx_p_10	Okokufaka	1	I-HDMI RX I2C SCL ye-DDC ne-SCDC
fmcb_la_tx_p_12	Okokufaka	1	Ukutholwa kwepulaki eshisayo ye-HDMI TX
fmcb_la_tx_n_12	Inout	1	I-HDMI I2C SDA ye-DDC ne-SCDC
fmcb_la_rx_p_10	Inout	1	I-HDMI I2C SCL ye-DDC ne-SCDC
fmcb_la_tx_p_11	Inout	1	I-HDMI I2C SDA yokulawula umshayeli kabusha
fmcb_la_rx_n_9	Inout	1	I-HDMI I2C SCL yokulawula umshayeli kabusha

Ithebula 42. Izimpawu ze-HDMI RX Zezinga eliphezulu

Isiginali	Isiqondiso	Ububanzi	Incazelo
Iwashi futhi Setha Kabusha Amasignali
mgmt_clk	Okokufaka	1	Okokufaka kwewashi lesistimu (100 MHz)
fr_clk (Intel Quartus Prime Pro Edition)	Okokufaka	1	Iwashi eligijima lamahhala (625 MHz) lewashi lereferensi ye-transceiver eyinhloko. Leli washi liyadingeka ekulinganisweni kwe-transceiver ngesikhathi sokuphakama kwamandla. Leli washi lingaba lanoma iyiphi imvamisa.
setha kabusha	Okokufaka	1	Okokufaka kokusetha kabusha isistimu

Isiginali	Isiqondiso	Ububanzi	Incazelo
Iwashi futhi Setha Kabusha Amasignali
reset_xcvr_powerup (Intel Quartus Prime Pro Edition)	Okokufaka	1	Okokufaka kokusetha kabusha i-Transceiver. Le signali igonyelwa phakathi nenqubo yokushintsha amawashi ayizethenjwa (kusuka ewashini eligijima lamahhala ukuya kuwashi le-TMDS) esimweni sokukhulisa amandla.
tmds_clk_in	Okokufaka	1	Iwashi le-HDMI RX TMDS
i2c_cl	Okokufaka	1	Okokufaka kwewashi kwe-DDC ne-SCDC interface
vid_clk_out	Okukhiphayo	1	Okukhipha iwashi levidiyo
ls_clk_out	Okukhiphayo	1	Xhumanisa ukuphuma kwewashi lesivinini
sys_init	Okukhiphayo	1	Ukuqaliswa kwesistimu ukuze kusethwe kabusha isistimu lapho kucishwa amandla

I-RX Transceiver kanye ne-IOPLL Signals
rx_serial_data	Okokufaka	3	Idatha ye-HDMI ye-serial eya ku-RX Native PHY
gxb_rx_ready	Okukhiphayo	1	Ikhombisa i-RX Native PHY isilungile
gxb_rx_cal_busy_out	Okukhiphayo	3	Ukulinganisa kwe-RX Native PHY kumatasa ku-transceiver arbiter
gxb_rx_cal_busy_in	Okokufaka	3	Isignali ematasa yokulinganisa isuka ku-transceiver arbiter iye ku-RX Native PHY
iopll_locked	Okukhiphayo	1	Khomba ukuthi i-IOPLL ikhiyiwe
gxb_reconfig_write	Okokufaka	3	Ukulungiswa kabusha kwe-Transceiver interface ye-Avalon-MM kusuka ku-RX Native PHY kuya kumnqamuli we-transceiver
gxb_reconfig_read	Okokufaka	3
gxb_reconfig_address	Okokufaka	30
gxb_reconfig_writedata	Okokufaka	96
gxb_reconfig_readdata	Okukhiphayo	96
gxb_reconfig_waitrequest	Okukhiphayo	3

I-RX Reconfiguration Management
rx_reconfig_zu	Okukhiphayo	1	Ukucushwa kabusha kwe-RX kunika amandla isiginali
isilinganiso	Okukhiphayo	24	Isilinganiso sefrikhwensi yewashi le-HDMI RX TMDS (ku-10 ms)
isilinganiso_sivumelekile	Okukhiphayo	1	Ikhombisa ukuthi isignali yokulinganisa ivumelekile
os	Okukhiphayo	1	overampi-ling factor: • 0: Awekho ama-overampling • 1: 5× ngaphezuluampling
reconfig_mgmt_write	Okukhiphayo	1	Ukuphathwa kokulungiswa kabusha kwe-RX isixhumi esibonakalayo esinemephu yenkumbulo ye-Avalon ku-transceiver arbiter
reconfig_mgmt_read	Okukhiphayo	1
reconfig_mgmt_address	Okukhiphayo	12

reconfig_mgmt_writedata	Okukhiphayo	32
reconfig_mgmt_readdata	Okokufaka	32
reconfig_mgmt_waitrequest	Okokufaka	1

Izimpawu ze-HDMI RX Core
TMDS_Bit_clock_Ratio	Okukhiphayo	1	Izixhumanisi zerejista ye-SCDC
audio_de	Okukhiphayo	1	Izixhumanisi zomsindo eziyinhloko ze-HDMI RX Bheka isigaba se-Sink Interfaces ku-HDMI Intel FPGA IP User Guide ukuze uthole ulwazi olwengeziwe.
idatha_yomsindo	Okukhiphayo	256
audio_info_ai	Okukhiphayo	48
okulalelwayo_N	Okukhiphayo	20
okulalelwayo_CTS	Okukhiphayo	20
imethadatha_yomsindo	Okukhiphayo	165
ifomethi_yomsindo	Okukhiphayo	5
aux_pkt_data	Okukhiphayo	72	Izixhumanisi eziyisiza eziyinhloko ze-HDMI RX Bheka isigaba se-Sink Interfaces ku-HDMI Intel FPGA IP User Guide ukuze uthole ulwazi olwengeziwe.
noma_pkt_addr	Okukhiphayo	6
noma_pkt_wr	Okukhiphayo	1
aux_data	Okukhiphayo	72
aux_sop	Okukhiphayo	1
aux_eop	Okukhiphayo	1
i-aux_valid	Okukhiphayo	1
aux_iphutha	Okukhiphayo	1
gcp	Okukhiphayo	6	Amasiginali webhendi eseceleni ye-HDMI RX Bheka isigaba se-Sink Interfaces ku-HDMI Intel FPGA IP User Guide ukuze uthole ulwazi olwengeziwe.
ulwazi_avi	Okukhiphayo	112
ulwazi_vsi	Okukhiphayo	61
colordepth_mgmt_sync	Okukhiphayo	2
idatha_yevidiyo	Okukhiphayo	N*48	Izimbobo zevidiyo eziwumgogodla we-HDMI RX Qaphela: N = izimpawu iwashi ngalinye Bheka ku- Sink Interfaces isigaba ku I-HDMI Intel FPGA IP User Guide ukuze uthole ulwazi olwengeziwe.
ividyo_vsync	Okukhiphayo	N
ividiyo_hsync	Okukhiphayo	N
vid_de	Okukhiphayo	N
imodi	Okukhiphayo	1	Ukulawula okuyinhloko kwe-HDMI RX kanye nezimbobo zesimo Qaphela: N = izimpawu iwashi ngalinye Bheka ku- Sink Interfaces isigaba ku I-HDMI Intel FPGA IP User Guide ukuze uthole ulwazi olwengeziwe.
ctrl	Okukhiphayo	N*6
kukhiyiwe	Okukhiphayo	3
i-vid_lock	Okukhiphayo	1
emandleni_5v	Okokufaka	1	I-HDMI RX 5V thola bese uthola i-hotplug Bheka ku Sink Interfaces isigaba ku I-HDMI Intel FPGA IP User Guide ukuze uthole ulwazi olwengeziwe.
i-hdmi_rx_hpd_n	Inout	1

hdmi_rx_i2c_sda	Inout	1	I-HDMI RX DDC ne-SCDC interface
i-hdmi_rx_i2c_scl	Inout	1

Izimpawu ze-RX EDID RAM
edid_ram_access	Okokufaka	1	I-HDMI RX EDID RAM isixhumi esibonakalayo sokufinyelela. Funa i-edid_ram_access uma ufuna ukubhala noma ukufunda ku-EDID RAM, uma kungenjalo le signali kufanele igcinwe iphansi.
edid_ram_address	Okokufaka	8
edid_ram_bhala	Okokufaka	1
i-ed_ram_read	Okokufaka	1
edid_ram_readdata	Okukhiphayo	8
edid_ram_writedata	Okokufaka	8
edid_ram_waitrequest	Okukhiphayo	1

Ithebula 43. Izimpawu ze-HDMI TX Zezinga eliphezulu

Isiginali	Isiqondiso	Ububanzi	Incazelo
Iwashi futhi Setha Kabusha Amasignali
mgmt_clk	Okokufaka	1	Okokufaka kwewashi lesistimu (100 MHz)
fr_clk (Intel Quartus Prime Pro Edition)	Okokufaka	1	Iwashi eligijima lamahhala (625 MHz) lewashi lereferensi ye-transceiver eyinhloko. Leli washi liyadingeka ekulinganisweni kwe-transceiver ngesikhathi sokuphakama kwamandla. Leli washi lingaba lanoma iyiphi imvamisa.
setha kabusha	Okokufaka	1	Okokufaka kokusetha kabusha isistimu
hdmi_clk_in	Okokufaka	1	Iwashi lereferensi ku-TX IOPLL naku-TX PLL. Ifrikhwensi yewashi iyafana nefrikhwensi yewashi ye-TMDS.
vid_clk_out	Okukhiphayo	1	Okukhipha iwashi levidiyo
ls_clk_out	Okukhiphayo	1	Xhumanisa ukuphuma kwewashi lesivinini
sys_init	Okukhiphayo	1	Ukuqaliswa kwesistimu ukuze kusethwe kabusha isistimu lapho kucishwa amandla
setha kabusha_xcvr	Okokufaka	1	Setha kabusha ku-TX transceiver
setha kabusha_pll	Okokufaka	1	Setha kabusha ku-IOPLL naku-TX PLL
reset_pll_reconfig	Okukhiphayo	1	Setha kabusha ekulungiseni kabusha kwe-PLL

I-TX Transceiver kanye ne-IOPLL Signals
tx_serial_data	Okukhiphayo	4	Idatha ye-HDMI ye-serial evela ku-TX Native PHY
gxb_tx_ready	Okukhiphayo	1	Ikhombisa ukuthi i-TX Native PHY isilungile
gxb_tx_cal_busy_out	Okukhiphayo	4	Ukulinganisa kwe-TX Native PHY isignali ematasa ku-transceiver arbiter
gxb_tx_cal_busy_in	Okokufaka	4	Isiginali yokulinganisa ematasatasa ukusuka ku-transceiver arbiter ukuya ku-TX Native PHY

I-TX Transceiver kanye ne-IOPLL Signals
iopll_locked	Okukhiphayo	1	Khomba ukuthi i-IOPLL ikhiyiwe
txpll_ikhiyiwe	Okukhiphayo	1	Khomba ukuthi i-TX PLL ikhiyiwe
gxb_reconfig_write	Okokufaka	4	I-Transceiver reconfiguration ye-Avalon memory-mapped interface kusuka ku-TX Native PHY kuya kumnqamuli we-transceiver
gxb_reconfig_read	Okokufaka	4
gxb_reconfig_address	Okokufaka	40
gxb_reconfig_writedata	Okokufaka	128
gxb_reconfig_readdata	Okukhiphayo	128
gxb_reconfig_waitrequest	Okukhiphayo	4

I-TX IOPLL kanye ne-TX PLL Izimpawu Zokumisa Kabusha
pll_reconfig_write/ tx_pll_reconfig_write	Okokufaka	1	I-TX IOPLL/TX PLL yokusetha kabusha i-Avalon yemephu yenkumbulo ye-interfaces
pll_reconfig_read/ tx_pll_reconfig_read	Okokufaka	1
pll_reconfig_address/ tx_pll_reconfig_address	Okokufaka	10
pll_reconfig_writedata/ tx_pll_reconfig_writedata	Okokufaka	32
pll_reconfig_readdata/ tx_pll_reconfig_readdata	Okukhiphayo	32
pll_reconfig_waitrequest/tx_pll_reconfig_waitrequest	Okukhiphayo	1
os	Okokufaka	2	overampi-ling factor: • 0: Awekho ama-overampling • 1: 3× ngaphezuluampling • 2: 4× ngaphezuluampling • 3: 5× ngaphezuluampling
isilinganiso	Okokufaka	24	Ikhombisa imvamisa yewashi le-TMDS lokulungiswa kwevidiyo edlulisayo.

Izimpawu ze-HDMI TX Core
ctrl	Okokufaka	6*N	Izixhumanisi zokulawula eziyinhloko ze-HDMI TX Qaphela: N = Izimpawu ngewashi ngalinye Bheka esigabeni se-Source Interfaces ku I-HDMI I-Intel FPGA IP User Guide ukuze uthole ulwazi olwengeziwe.
imodi	Okokufaka	1
TMDS_Bit_clock_Ratio	Okokufaka	1	SCIzixhumanisi zerejista ye-DC Bheka isigaba se-Source Interfaces ku-HDMI Intel FPGA IP User Guide ukuze uthole ulwazi olwengeziwe.
I-Scrambler_Vumela	Okokufaka	1
audio_de	Okokufaka	1	Izixhumanisi zomsindo eziyinhloko ze-HDMI TX Bheka ku- Source Interfaces isigaba ku I-HDMI Intel FPGA IP User Guide ukuze uthole ulwazi olwengeziwe.
thulisa_umsindo	Okokufaka	1
idatha_yomsindo	Okokufaka	256
waqhubeka...

Izimpawu ze-HDMI TX Core
audio_info_ai	Okokufaka	49
okulalelwayo_N	Okokufaka	22
okulalelwayo_CTS	Okokufaka	22
imethadatha_yomsindo	Okokufaka	166
ifomethi_yomsindo	Okokufaka	5
i2c_master_write	Okokufaka	1	I-TX I2C master Avalon-mapped interface to I2C master ngaphakathi kwe-TX core. Qaphela: Lawa masignali atholakala kuphela uma uvula Faka i-I2C ipharamitha.
i2c_master_read	Okokufaka	1
i2c_master_address	Okokufaka	4
i2c_master_writedata	Okokufaka	32
i2c_master_readdata	Okukhiphayo	32
aux_ready	Okukhiphayo	1	I-HDMI TX izixhumanisi eziyisiza eziyinhloko Bheka isigaba se-Source Interfaces ku-HDMI Intel FPGA IP User Guide ukuze uthole ulwazi olwengeziwe.
aux_data	Okokufaka	72
aux_sop	Okokufaka	1
aux_eop	Okokufaka	1
i-aux_valid	Okokufaka	1
gcp	Okokufaka	6	I-HDMI TX amasiginali webhendi eseceleni Bheka isigaba se-Source Interfaces ku-HDMI Intel FPGA IP User Guide ukuze uthole ulwazi olwengeziwe.
ulwazi_avi	Okokufaka	113
ulwazi_vsi	Okokufaka	62
idatha_yevidiyo	Okokufaka	N*48	Izimbobo zevidiyo ze-HDMI TX Qaphela: N = izimpawu ngewashi ngalinye Bheka isigaba se-Source Interfaces ku-HDMI Intel FPGA IP User Guide ukuze uthole ulwazi olwengeziwe.
ividyo_vsync	Okokufaka	N
ividiyo_hsync	Okokufaka	N
vid_de	Okokufaka	N

I2C kanye ne-Hot Plug Ithola Amasignali
nios_tx_i2c_sda_in (Intel Quartus Prime Pro Edition) Qaphela: Uma uvula i- Faka i-I2C ipharamitha, lesi siginali ibekwe kumongo we-TX futhi ngeke ibonakale kuleli zinga.	Okukhiphayo	1	I-I2C Master Avalon interface enemephu yenkumbulo
nios_tx_i2c_scl_in (Intel Quartus Prime Pro Edition) Qaphela: Uma uvula i- Faka i-I2C ipharamitha, lesi siginali ibekwe kumongo we-TX futhi ngeke ibonakale kuleli zinga.	Okukhiphayo	1
nios_tx_i2c_sda_oe (Intel Quartus Prime Pro Edition) Qaphela: Uma uvula i- Faka i-I2C ipharamitha, lesi siginali ibekwe kumongo we-TX futhi ngeke ibonakale kuleli zinga.	Okokufaka	1
waqhubeka...

I2C kanye ne-Hot Plug Ithola Amasignali
nios_tx_i2c_scl_oe (Intel Quartus Prime Pro Edition) Qaphela: Uma uvula i- Faka i-I2C ipharamitha, lesi siginali ibekwe kumongo we-TX futhi ngeke ibonakale kuleli zinga.	Okokufaka	1
nios_ti_i2c_sda_in (Intel Quartus Prime Pro Edition)	Okukhiphayo	1
nios_ti_i2c_scl_in (Intel Quartus Prime Pro Edition)	Okukhiphayo	1
nios_ti_i2c_sda_oe (Intel Quartus Prime Pro Edition)	Okokufaka	1
nios_ti_i2c_scl_oe (Intel Quartus Prime Pro Edition)	Okokufaka	1
hdmi_tx_i2c_sda	Inout	1	Izixhumanisi ze-HDMI TX DDC kanye ne-SCDC
i-hdmi_tx_i2c_scl	Inout	1
I-hdmi_ti_i2c_sda (Intel Quartus Prime Pro Edition)	Inout	1	Isixhumi esibonakalayo se-I2C se-Bitec Daughter Card Revision 11 TI181 Control
I-hdmi_tx_ti_i2c_sda (Intel Quartus Prime Standard Edition)	Inout	1
I-hdmi_ti_i2c_scl (Intel Quartus Prime Pro Edition)	Inout	1
I-hdmi_tx_ti_i2c_scl (Intel Quartus Prime Standard Edition)	Inout	1
tx_i2c_avalon_waitrequest	Okukhiphayo	1	I-Avalon memory-mapped interface ye-I2C master
tx_i2c_avalon_address (Intel Quartus Prime Standard Edition)	Okokufaka	3
tx_i2c_avalon_writedata (Intel Quartus Prime Standard Edition)	Okokufaka	8
tx_i2c_avalon_readdata (Intel Quartus Prime Standard Edition)	Okukhiphayo	8
tx_i2c_avalon_chipselect (Intel Quartus Prime Standard Edition)	Okokufaka	1
tx_i2c_avalon_write (Intel Quartus Prime Standard Edition)	Okokufaka	1
tx_i2c_irq (Intel Quartus Prime Standard Edition)	Okukhiphayo	1
tx_ti_i2c_avalon_waitrequest (Intel Quartus Prime Standard Edition)	Okukhiphayo	1
tx_ti_i2c_avalon_address (Intel Quartus Prime Standard Edition)	Okokufaka	3
tx_ti_i2c_avalon_writedata (Intel Quartus Prime Standard Edition)	Okokufaka	8
tx_ti_i2c_avalon_readdata (Intel Quartus Prime Standard Edition)	Okukhiphayo	8
waqhubeka...

I2C kanye ne-Hot Plug Ithola Amasignali
tx_ti_i2c_avalon_chipselect (Intel Quartus Prime Standard Edition)	Okokufaka	1
tx_ti_i2c_avalon_write (Intel Quartus Prime Standard Edition)	Okokufaka	1
tx_ti_i2c_irq (Intel Quartus Prime Standard Edition)	Okukhiphayo	1
i-hdmi_tx_hpd_n	Okokufaka	1	I-HDMI TX hotplug ibona izixhumi ezibonakalayo
tx_hpd_ack	Okokufaka	1
tx_hpd_req	Okukhiphayo	1

Ithebula 44. Izimpawu ze-Transceiver Arbiter

Isiginali	Isiqondiso	Ububanzi	Incazelo
clk	Okokufaka	1	Iwashi lokumisa kabusha. Leli washi kufanele labelane ngewashi elifanayo namabhulokhi okuphatha ukulungisa kabusha.
setha kabusha	Okokufaka	1	Setha kabusha isignali. Lokhu kusetha kabusha kufanele kwabelane ngokusetha kabusha okufanayo namabhulokhi okuphatha ukulungisa kabusha.
rx_rcfg_zu	Okokufaka	1	Ukumiswa kabusha kwe-RX kuvumela isignali
tx_rcfg_zu	Okokufaka	1	Ukumiswa kabusha kwe-TX kuvumela isignali
rx_rcfg_ch	Okokufaka	2	Ibonisa ukuthi yisiphi isiteshi okufanele simiswe kabusha kumongo we-RX. Lesi siginali kufanele sihlale sigomele.
tx_rcfg_ch	Okokufaka	2	Ibonisa ukuthi yisiphi isiteshi okufanele simiswe kabusha kumongo we-TX. Lesi siginali kufanele sihlale sigomele.
rx_reconfig_mgmt_write	Okokufaka	1	Ukulungisa kabusha ukuxhumana kwe-Avalon-MM kusuka ekulawuleni ukulungiselelwa kabusha kwe-RX
rx_reconfig_mgmt_read	Okokufaka	1
rx_reconfig_mgmt_address	Okokufaka	10
rx_reconfig_mgmt_writedata	Okokufaka	32
rx_reconfig_mgmt_readdata	Okukhiphayo	32
rx_reconfig_mgmt_waitrequest	Okukhiphayo	1
tx_reconfig_mgmt_write	Okokufaka	1	Ukulungisa kabusha ukuxhumana kwe-Avalon-MM kusuka ekulawuleni ukulungiselelwa kabusha kwe-TX
tx_reconfig_mgmt_read	Okokufaka	1
tx_reconfig_mgmt_address	Okokufaka	10
tx_reconfig_mgmt_writedata	Okokufaka	32
tx_reconfig_mgmt_readdata	Okukhiphayo	32
tx_reconfig_mgmt_waitrequest	Okukhiphayo	1
reconfig_write	Okukhiphayo	1	Ukulungisa kabusha i-Avalon-MM ixhuma ku-transceiver
reconfig_read	Okukhiphayo	1
waqhubeka...

Isiginali	Isiqondiso	Ububanzi	Incazelo
reconfig_address	Okukhiphayo	10
reconfig_writedata	Okukhiphayo	32
rx_reconfig_readdata	Okokufaka	32
rx_reconfig_waitrequest	Okokufaka	1
tx_reconfig_readdata	Okokufaka	1
tx_reconfig_waitrequest	Okokufaka	1
rx_cal_matasa	Okokufaka	1	Isignali yesimo sokulinganisa evela ku-transceiver ye-RX
tx_cal_matasa	Okokufaka	1	Isignali yesimo sokulinganisa evela ku-transceiver ye-TX
rx_reconfig_cal_busy	Okukhiphayo	1	Isignali yesimo sokulinganisa kusilawuli sokusetha kabusha i-RX transceiver PHY
tx_reconfig_cal_busy	Okukhiphayo	1	Isignali yesimo sokulinganisa evela kusilawuli sokusetha kabusha se-TX transceiver PHY

Ithebula 45. Izimpawu zokuxhumanisa i-RX-TX

Isiginali	Isiqondiso	Ububanzi	Incazelo
setha kabusha	Okokufaka	1	Setha kabusha ividiyo/umsindo/isilekeleli/ amabhande aseceleni e-FIFO.
hdmi_tx_ls_clk	Okokufaka	1	Iwashi lejubane lesixhumanisi se-HDMI TX
hdmi_rx_ls_clk	Okokufaka	1	Iwashi lejubane lesixhumanisi se-HDMI RX
i-hdmi_tx_vid_clk	Okokufaka	1	Iwashi levidiyo le-HDMI TX
i-hdmi_rx_vid_clk	Okokufaka	1	Iwashi levidiyo le-HDMI RX
i-hdmi_rx_locked	Okokufaka	3	Ibonisa isimo esikhiyiwe se-HDMI RX
hdmi_rx_de	Okokufaka	N	Izixhumanisi zevidiyo ze-HDMI RX Qaphela: N = izimpawu iwashi ngalinye
hdmi_rx_hsync	Okokufaka	N
hdmi_rx_vsync	Okokufaka	N
Idatha_ye-hdmi_rx	Okokufaka	I-N * 48
rx_ifomethi_yomsindo	Okokufaka	5	Izixhumanisi zomsindo ze-HDMI RX
rx_audio_metadata	Okokufaka	165
rx_audio_info_ai	Okokufaka	48
rx_audio_CTS	Okokufaka	20
rx_umsindo_N	Okokufaka	20
rx_audio_de	Okokufaka	1
rx_idatha_yomsindo	Okokufaka	256
rx_gcp	Okokufaka	6	Izixhumanisi ze-HDMI RX sideband
rx_info_avi	Okokufaka	112
rx_info_vsi	Okokufaka	61
waqhubeka...

Isiginali	Isiqondiso	Ububanzi	Incazelo
rx_aux_eop	Okokufaka	1	Izixhumanisi ezisizayo ze-HDMI RX
rx_aux_sop	Okokufaka	1
rx_aux_valid	Okokufaka	1
rx_aux_idatha	Okokufaka	72
hdmi_tx_de	Okukhiphayo	N	Izixhumanisi zevidiyo ye-HDMI TX Qaphela: N = izimpawu iwashi ngalinye
i-hdmi_tx_hsync	Okukhiphayo	N
hdmi_tx_vsync	Okukhiphayo	N
HDmi_tx_data	Okukhiphayo	I-N * 48
tx_ifomethi_yomsindo	Okukhiphayo	5	Izixhumanisi zomsindo ze-HDMI TX
tx_audio_metadata	Okukhiphayo	165
tx_audio_info_ai	Okukhiphayo	48
tx_audio_CTS	Okukhiphayo	20
tx_audio_N	Okukhiphayo	20
tx_audio_de	Okukhiphayo	1
tx_idatha_yomsindo	Okukhiphayo	256
tx_gcp	Okukhiphayo	6	Izixhumanisi ze-HDMI TX sideband
tx_info_avi	Okukhiphayo	112
tx_info_vsi	Okukhiphayo	61
tx_aux_eop	Okukhiphayo	1	Izixhumanisi ze-HDMI TX ezisizayo
tx_aux_sop	Okukhiphayo	1
tx_aux_valid	Okukhiphayo	1
tx_aux_idatha	Okukhiphayo	72
tx_aux_ready	Okukhiphayo	1

Ithebula 46. Izimpawu Zohlelo Lomklami Wenkundla

Isiginali	Isiqondiso	Ububanzi	Incazelo
cpu_clk (Intel Quartus Prime Standard Edition)	Okokufaka	1	Iwashi le-CPU
clock_bridge_0_in_clk_clk (Intel Quartus Prime Pro Edition)
cpu_clk_reset_n (Intel Quartus Prime Standard Edition)	Okokufaka	1	Ukusetha kabusha kwe-CPU
reset_bridge_0_reset_reset_n (Intel Quartus Prime Pro Edition)
tmds_bit_clock_ratio_pio_external_connectio n_export	Okokufaka	1	Isilinganiso sewashi elincane le-TMDS
isilinganiso_pio_external_connection_export	Okokufaka	24	Imvamisa yewashi ye-TMDS elindelwe
waqhubeka...

Isiginali	Isiqondiso	Ububanzi	Incazelo
measure_valid_pio_external_connection_expor t	Okokufaka	1	Ikhombisa isilinganiso se-PIO sivumelekile
i2c_master_i2c_serial_sda_in (Intel Quartus Prime Pro Edition)	Okokufaka	1	I-I2C Master interfaces
i2c_master_i2c_serial_scl_in (Intel Quartus Prime Pro Edition)	Okokufaka	1
i2c_master_i2c_serial_sda_oe (Intel Quartus Prime Pro Edition)	Okukhiphayo	1
i2c_master_i2c_serial_scl_oe (Intel Quartus Prime Pro Edition)	Okukhiphayo	1
i2c_master_ti_i2c_serial_sda_in (Intel Quartus Prime Pro Edition)	Okokufaka	1
i2c_master_ti_i2c_serial_scl_in (Intel Quartus Prime Pro Edition)	Okokufaka	1
i2c_master_ti_i2c_serial_sda_oe (Intel Quartus Prime Pro Edition)	Okukhiphayo	1
i2c_master_ti_i2c_serial_scl_oe (Intel Quartus Prime Pro Edition)	Okukhiphayo	1
oc_i2c_master_av_slave_translator_avalon_an ti_slave_0_address (Intel Quartus Prime Pro Edition)	Okukhiphayo	3	I-I2C Master Avalon enemephu yokusebenzelana enemephu yenkumbulo ye-DDC ne-SCDC
oc_i2c_master_av_slave_translator_avalon_an ti_slave_0_write (Intel Quartus Prime Pro Edition)	Okukhiphayo	1
oc_i2c_master_av_slave_translator_avalon_an ti_slave_0_readdata (Intel Quartus Prime Pro Edition)	Okokufaka	32
oc_i2c_master_av_slave_translator_avalon_an ti_slave_0_writedata (Intel Quartus Prime Pro Edition)	Okukhiphayo	32
oc_i2c_master_av_slave_translator_avalon_an ti_slave_0_waitrequest (Intel Quartus Prime Pro Edition)	Okokufaka	1
oc_i2c_master_av_slave_translator_avalon_an ti_slave_0_chipselect (Intel Quartus Prime Pro Edition)	Okukhiphayo	1
oc_i2c_master_ti_avalon_anti_slave_address (Intel Quartus Prime Standard Edition)	Okukhiphayo	3	I-I2C Master Avalon enemephu yokuxhumana enemephu yokubuyekezwa kwekhadi lendodakazi ye-Bitec 11, ukulawula kwe-T1181
oc_i2c_master_ti_avalon_anti_slave_write (Intel Quartus Prime Standard Edition)	Okukhiphayo	1
oc_i2c_master_ti_avalon_anti_slave_readdata (Intel Quartus Prime Standard Edition)	Okokufaka	32
oc_i2c_master_ti_avalon_anti_slave_writedat a (Intel Quartus Prime Standard Edition)	Okukhiphayo	32
oc_i2c_master_ti_avalon_anti_slave_waitrequ est (Intel Quartus Prime Standard Edition)	Okokufaka	1
oc_i2c_master_ti_avalon_anti_slave_chipsele ct (Intel Quartus Prime Standard Edition)	Okukhiphayo	1
waqhubeka...

Isiginali	Isiqondiso	Ububanzi	Incazelo
edid_ram_access_pio_external_connection_exp ort	Okukhiphayo	1	Izixhumanisi zokufinyelela ze-EDID RAM. Funa ukuthunyelwa kwe-edid_ram_access_pio_ external_connection_ uma ufuna ukubhala noma ukufunda ku-EDID RAM phezulu kwe-RX. Xhuma i-EDID RAM yokufinyelela isigqila se-Avalon-MM KuMklami Wenkundla kusixhumi esibonakalayo se-EDID RAM kumamojula we-RX esezingeni eliphezulu.
edid_ram_slave_translator_address	Okukhiphayo	8
edid_ram_slave_translator_write	Okukhiphayo	1
edid_ram_slave_translator_read	Okukhiphayo	1
edid_ram_slave_translator_readdata	Okokufaka	8
edid_ram_slave_translator_writedata	Okukhiphayo	8
edid_ram_slave_translator_waitrequest	Okokufaka	1
i-powerup_cal_done_export (Intel Quartus Prime Pro Edition)	Okokufaka	1	I-RX PMA Reconfiguration Avalon memory-mapped interfaces
rx_pma_cal_busy_export (Intel Quartus Prime Pro Edition)	Okokufaka	1
rx_pma_ch_export (Intel Quartus Prime Pro Edition)	Okukhiphayo	2
rx_pma_rcfg_mgmt_address (Intel Quartus Prime Pro Edition)	Okukhiphayo	12
rx_pma_rcfg_mgmt_write (Intel Quartus Prime Pro Edition)	Okukhiphayo	1
rx_pma_rcfg_mgmt_read (Intel Quartus Prime Pro Edition)	Okukhiphayo	1
rx_pma_rcfg_mgmt_readdata (Intel Quartus Prime Pro Edition)	Okokufaka	32
rx_pma_rcfg_mgmt_writedata (Intel Quartus Prime Pro Edition)	Okukhiphayo	32
rx_pma_rcfg_mgmt_waitrequest (Intel Quartus Prime Pro Edition)	Okokufaka	1
rx_pma_waitrequest_export (Intel Quartus Prime Pro Edition)	Okokufaka	1
rx_rcfg_en_export (Intel Quartus Prime Pro Edition)	Okukhiphayo	1
rx_rst_xcvr_export (Intel Quartus Prime Pro Edition)	Okukhiphayo	1
tx_pll_rcfg_mgmt_translator_avalon_anti_sla ve_waitrequest	Okokufaka	1	I-TX PLL Reconfiguration Avalon memory-mapped interfaces
tx_pll_rcfg_mgmt_translator_avalon_anti_sla ve_writedata	Okukhiphayo	32
tx_pll_rcfg_mgmt_translator_avalon_anti_sla ve_address	Okukhiphayo	10
tx_pll_rcfg_mgmt_translator_avalon_anti_sla ve_write	Okukhiphayo	1
tx_pll_rcfg_mgmt_translator_avalon_anti_sla ve_read	Okukhiphayo	1
tx_pll_rcfg_mgmt_translator_avalon_anti_sla ve_readdata	Okokufaka	32
waqhubeka...

Isiginali	Isiqondiso	Ububanzi	Incazelo
tx_pll_waitrequest_pio_external_connection_ thekelisa	Okokufaka	1	Isicelo sokulinda se-TX PLL
tx_pma_rcfg_mgmt_translator_avalon_anti_sla ve_address	Okukhiphayo	12	I-TX PMA Reconfiguration Avalon memory-mapped interfaces
tx_pma_rcfg_mgmt_translator_avalon_anti_sla ve_write	Okukhiphayo	1
tx_pma_rcfg_mgmt_translator_avalon_anti_sla ve_read	Okukhiphayo	1
tx_pma_rcfg_mgmt_translator_avalon_anti_sla ve_readdata	Okokufaka	32
tx_pma_rcfg_mgmt_translator_avalon_anti_sla ve_writedata	Okukhiphayo	32
tx_pma_rcfg_mgmt_translator_avalon_anti_sla ve_waitrequest	Okokufaka	1
tx_pma_waitrequest_pio_external_connection_ ukuthekelisa	Okokufaka	1	Isicelo sokulinda se-TX PMA
tx_pma_cal_busy_pio_external_connection_exp ort	Okokufaka	1	TX PMA Recalibration Kumatasa
tx_pma_ch_thekelisa	Okukhiphayo	2	Iziteshi ze-TX PMA
tx_rcfg_zu_pio_external_connection_export	Okukhiphayo	1	I-TX PMA Reconfiguration Vuselela
tx_iopll_rcfg_mgmt_translator_avalon_anti_s lave_writedata	Okukhiphayo	32	I-TX IOPLL Reconfiguration Avalon memory-mapped interfaces
tx_iopll_rcfg_mgmt_translator_avalon_anti_s lave_readdata	Okokufaka	32
tx_iopll_rcfg_mgmt_translator_avalon_anti_s lave_waitrequest	Okokufaka	1
tx_iopll_rcfg_mgmt_translator_avalon_anti_s lave_address	Okukhiphayo	9
tx_iopll_rcfg_mgmt_translator_avalon_anti_s lave_write	Okukhiphayo	1
tx_iopll_rcfg_mgmt_translator_avalon_anti_s lave_read	Okukhiphayo	1
tx_os_pio_external_connection_export	Okukhiphayo	2	overampi-ling factor: • 0: Awekho ama-overampling • 1: 3× ngaphezuluampling • 2: 4× ngaphezuluampling • 3: 5× ngaphezuluampling
tx_rst_pll_pio_external_connection_export	Okukhiphayo	1	Setha kabusha ku-IOPLL naku-TX PLL
tx_rst_xcvr_pio_external_connection_export	Okukhiphayo	1	Setha kabusha ku-TX Native PHY
wd_timer_resetrequest_reset	Okukhiphayo	1	Setha kabusha isibali sikhathi se-Watchdog
color_depth_pio_external_connection_export	Okokufaka	2	Ukujula kombala
tx_hpd_ack_pio_external_connection_export	Okukhiphayo	1	Okwe-TX hotplug thola ukuxhawula
tx_hpd_req_pio_external_connection_export	Okokufaka	1

3.8. Yakha amapharamitha we-RTL
Sebenzisa amapharamitha we-HDMI TX kanye ne-RX Top RTL ukuze wenze ngendlela oyifisayo i-ex yomklamoample.
Iningi lamapharamitha wokuklama ayatholakala ku-Design Exampithebhu yomhleli wepharamitha ye-HDMI Intel FPGA IP. Usengashintsha i-ex yedizayiniample izilungiselelo wena
yenziwe kusihleli sepharamitha ngamapharamitha we-RTL.

Ithebula 47. Amapharamitha aphezulu we-HDMI RX

Ipharamitha	Inani	Incazelo
SUPPORT_DEEP_COLOR	• 0: Awukho umbala ojulile • 1: Umbala ojulile	Inquma ukuthi ingabe ingqikithi ingafaka amafomethi ombala ojulile.
SUPPORT_AUXILIARY	• 0: Ayikho i-AUX • 1: AUX	Inquma ukuthi umbhalo oyisizayo wesiteshi ufakiwe yini.
SYMBOLS_PER_CLOCK	8	Isekela izimpawu eziyi-8 iwashi ngalinye kumadivayisi we-Intel Arria 10.
SUPPORT_AUDIO	• 0: Awukho umsindo • 1: Umsindo	Inquma ukuthi umgogodla ungabhala yini umsindo.
EDID_RAM_ADDR_WIDTH (Intel Quartus Prime Standard Edition)	8 (Inani elizenzakalelayo)	Isisekelo sokungena esingu-2 sikasayizi we-RAM we-EDID.
BITEC_DAUGHTER_CARD_REV	• 0: Ayiqondile noma yiliphi ikhadi lendodakazi le-Bitec HDMI • 4: Isekela ukubuyekezwa kwekhadi lendodakazi le-Bitec HDMI 4 • 6: I-Targeting Bitec HDMI ikhadi lendodakazi lendodakazi 6 •11: Ukubuyekezwa kwekhadi lendodakazi ye-Bitec HDMI 11 (okuzenzakalelayo)	Icacisa ukubuyekezwa kwekhadi lendodakazi le-Bitec HDMI elisetshenzisiwe. Uma ushintsha isibuyekezo, idizayini ingase ishintshe amashaneli e-transceiver futhi iguqule i-polarity ngokwezidingo zekhadi lendodakazi le-Bitec HDMI. Uma usetha ipharamitha ye-BITEC_DAUGHTER_CARD_REV ibe ngu-0, idizayini ayenzi izinguquko kumashaneli e-transceiver kanye ne-polarity.
POLARITY_INVERSION	• 0: Guqula i-polarity • 1: Ungaguquli i-polarity	Setha le pharamitha ku-1 ukuze uguqule inani lebhithi ngalinye ledatha yokufaka. Ukusetha le pharamitha kokuthi 1 kwabela i-4'b1111 kumbobo ye-rx_poliv ye-transceiver ye-RX.

Ithebula 48. Amapharamitha aphezulu we-HDMI TX

Ipharamitha	Inani	Incazelo
USE_FPLL	1	Isekela i-fPLL njenge-TX PLL kuphela kumadivayisi we-Intel Cyclone® 10 GX. Hlala usethe le pharamitha ku-1.
SUPPORT_DEEP_COLOR	• 0: Awukho umbala ojulile • 1: Umbala ojulile	Inquma ukuthi ingabe ingqikithi ingafaka amafomethi ombala ojulile.
SUPPORT_AUXILIARY	• 0: Ayikho i-AUX • 1: AUX	Inquma ukuthi umbhalo oyisizayo wesiteshi ufakiwe yini.
SYMBOLS_PER_CLOCK	8	Isekela izimpawu eziyi-8 iwashi ngalinye kumadivayisi we-Intel Arria 10.
waqhubeka...

Ipharamitha	Inani	Incazelo
SUPPORT_AUDIO	• 0: Awukho umsindo • 1: Umsindo	Inquma ukuthi umgogodla ungabhala yini umsindo.
BITEC_DAUGHTER_CARD_REV	• 0: Ayiqondile noma yiliphi ikhadi lendodakazi le-Bitec HDMI • 4: Isekela ukubuyekezwa kwekhadi lendodakazi le-Bitec HDMI 4 • 6: I-Targeting Bitec HDMI ikhadi lendodakazi lendodakazi 6 • 11: Ukubuyekezwa kwekhadi lendodakazi ye-Bitec HDMI 11 (okuzenzakalelayo)	Icacisa ukubuyekezwa kwekhadi lendodakazi le-Bitec HDMI elisetshenzisiwe. Uma ushintsha isibuyekezo, idizayini ingase ishintshe amashaneli e-transceiver futhi iguqule i-polarity ngokwezidingo zekhadi lendodakazi le-Bitec HDMI. Uma usetha ipharamitha ye-BITEC_DAUGHTER_CARD_REV ibe ngu-0, idizayini ayenzi izinguquko kumashaneli e-transceiver kanye ne-polarity.
POLARITY_INVERSION	• 0: Guqula i-polarity • 1: Ungaguquli i-polarity	Setha le pharamitha ku-1 ukuze uguqule inani lebhithi ngalinye ledatha yokufaka. Ukusetha le pharamitha kokuthi 1 kwabela i-4'b1111 kumbobo ye-tx_polinv ye-transceiver ye-TX.

3.9. Ukusethwa kwe-Hardware
I-HDMI Intel FPGA IP design exampi-HDMI 2.0b iyakwazi futhi yenza i-loopthrough demonstration yokusakaza kwevidiyo ye-HDMI ejwayelekile.
Ukuze uqalise ukuhlolwa kwezingxenyekazi zekhompuyutha, xhuma idivayisi enikwe amandla i-HDMI—njengekhadi lemifanekiso eline-HDMI isixhumi esibonakalayo—kubhulokhi ye-Transceiver Native PHY RX, kanye nosinki we-HDMI.
okokufaka.

1. Usinki we-HDMI uhlukanisa imbobo ibe ukusakaza kwevidiyo okuvamile futhi uyithumele kumongo wokutakula wewashi.
2. I-HDMI RX core inquma ividiyo, isilekeleli, nedatha yomsindo ezobuyiselwa emuva ngokuhambisana nomongo we-HDMI TX nge-DCFIFO.
3. Imbobo yomthombo ye-HDMI yekhadi lendodakazi ye-FMC idlulisela isithombe kusiqaphi.

Qaphela:
Uma ufuna ukusebenzisa elinye ibhodi lokuthuthukisa i-Intel FPGA, kufanele uguqule imisebenzi ezonikezwa idivayisi kanye nezabelo zamaphinikhodi. Isilungiselelo se-analog ye-transceiver sihlolelwa ikhithi yokuthuthukisa ye-Intel Arria 10 FPGA kanye nekhadi lendodakazi le-Bitec HDMI 2.0. Ungashintsha izilungiselelo zebhodi lakho.

Ithebula 49. Inkinobho Yokucindezela Esebhodini kanye Nemisebenzi ye-LED yomsebenzisi

Cindezela inkinobho/I-LED	Umsebenzi
cpu_resetn	Cindezela kanye ukuze wenze kabusha uhlelo.
umsebenzisi_pb[0]	Cindezela kanye ukuze uguqule isignali ye-HPD iye emthonjeni ojwayelekile we-HDMI.
umsebenzisi_pb[1]	• Cindezela bese ubamba ukuze uyalele umgogodla we-TX ukuthumela isignali enekhodi ye-DVI. • Khipha ukuze uthumele isignali enekhodi ye-HDMI.
umsebenzisi_pb[2]	• Cindezela bese ubamba ukuze uyalele i-TX core ukuthi iyeke ukuthumela ama-InfoFrames esuka kumasignali ebhendi eseceleni. • Khulula ukuze uqalise kabusha ukuthumela ama-InfoFrames kusuka kumasiginali ebhendi eseceleni.
USER_LED[0]	Isimo sokukhiya i-RX HDMI PLL. • 0 = Ivuliwe • 1 = Ikhiyiwe
USER_LED[1]	Isimo esilungile se-transceiver ye-RX.
waqhubeka...

Cindezela inkinobho/I-LED	Umsebenzi
	• 0 = Ayikalungi • 1 = Ilungile
USER_LED[2]	Isimo se-RX HDMI core lock. • 0 = Okungenani ishaneli eyodwa evuliwe • 1 = Wonke amashaneli ama-3 akhiyiwe
USER_LED[3]	Ama-RX ngaphezuluampisimo se-ling. • 0 = Okungadluliampled (izinga ledatha > 1,000 Mbps kudivayisi ye-Intel Arria 10) • 1 = Ama-Overampled (isilinganiso sedatha <100 Mbps kudivayisi ye-Intel Arria 10)
USER_LED[4]	Isimo sokukhiya i-TX HDMI PLL. • 0 = Ivuliwe • 1 = Ikhiyiwe
USER_LED[5]	Isimo esilungile se-transceiver. • 0 = Ayikalungi • 1 = Ilungile
USER_LED[6]	Isimo sokukhiya i-TX transceiver PLL. • 0 = Ivuliwe • 1 = Ikhiyiwe
USER_LED[7]	Ama-TX ngaphezuluampisimo se-ling. • 0 = Okungadluliampled (izinga ledatha > 1,000 Mbps kudivayisi ye-Intel Arria 10) • 1 = Ama-Overampled (isilinganiso sedatha <1,000 Mbps kudivayisi ye-Intel Arria 10)

3.10. Ukulingisa Testbench
Ibhentshi lesivivinyo sokulingisa lilingisa i-HDMI TX serial loopback ku-RX core.
Qaphela:
Le bhentshi yokulingisa ayisekelwe kumadizayini anepharamitha ethi Faka i-I2C enikwe amandla.

3. HDMI 2.0 Design Example (Ukusekela i-FRL = 0)
683156 | 2022.12.27
Umfanekiso 28. I-HDMI Intel FPGA IP Simulation Testbench Block Diagram

Ithebula 50. Izingxenye ze-Testbench

Isakhi	Incazelo
Ividiyo ye-TPG	Ijeneretha yephethini yokuhlola ividiyo (TPG) inikeza isikhuthazo sevidiyo.
Umsindo Sample Gen	Umsindo sample generator inikeza umsindo sample stimus. Ijeneretha ikhiqiza iphethini yedatha yokuhlola ekhulayo ezodluliswa ngesiteshi somsindo.
Aux Sample Gen	I-aux sample generator inikeza isilekeleli sample stimus. Ijeneretha ikhiqiza idatha engaguquki ezodluliswa isuka kumthumeli.
Hlola CRC	Lesi sihloli siqinisekisa ukuthi i-TX transceiver etholiwe imvamisa yewashi ifana yini nenani ledatha elifunekayo.
Ukuhlola Idatha Yomsindo	Ukuhlolwa kwedatha yomsindo kuqhathanisa ukuthi ingabe iphethini yedatha yokuhlola ekhulayo iyamukelwe futhi iqoshwe ngendlela efanele.
Ukuhlola Idatha ye-Aux	Ukuhlolwa kwedatha ye-aux kuqhathanisa ukuthi idatha ye-aux elindelekile yamukelwe futhi yaqoshwa kahle yini ohlangothini lomamukeli.

I-HDMI simulation testbench yenza izivivinyo zokuqinisekisa ezilandelayo:

Isici se-HDMI	Ukuqinisekisa
Idatha yevidiyo	• Ibhentshi le-test lisebenzisa i-CRC ukuhlola okokufaka nokuphumayo kwevidiyo. • Ihlola inani le-CRC ledatha edlulisiwe iqhathaniswa ne-CRC ebalwa kudatha yevidiyo etholiwe. • Ibhentshi le-test libe selihlola ngemva kokuthola amasignali angu-4 azinzile e-V-SYNC kumamukeli.
Idatha yokusiza	• I-ax sampi-generator ye-le generator ikhiqiza idatha engaguquki ukuze idluliselwe ku-transmitter. • Ohlangothini lomamukeli, ijeneretha iqhathanisa ukuthi idatha eyisisizi elindelekile yamukelwe futhi yaqoshwa ngendlela efanele yini.
Idatha yomsindo	• Umsindo sampi-le generator ikhiqiza iphethini yedatha yokuhlola ekhulayo ezodluliselwa ngesiteshi somsindo. • Ohlangothini lomamukeli, isihloli sedatha yomsindo sihlola futhi siqhathanise ukuthi iphethini yedatha yokuhlola ekhulayo yamukelwe futhi iqoshwe ngendlela efanele yini.

Ukulingisa okuyimpumelelo kugcina ngomlayezo olandelayo:
# IZIMPAWU_NGEWASHI = 2
#VIC = 4
# FRL_RATE = 0
#BPP =0
# I-AUDIO_FREQUENCY (kHz) = 48
# I-AUDIO_CHANNEL = 8
# Iphasi yokulingisa

Ithebula 51. HDMI Intel FPGA IP Design Example Izilingisi ezisekelwayo

Isifanisi	I-HDL ye-Verilog	I-VHDL
I-ModelSim – Intel FPGA Edition/ ModelSim – Intel FPGA Starter Edition	Yebo	Yebo
I-VCS/VCS MX	Yebo	Yebo
I-Riviera-PRO	Yebo	Yebo
I-Xcelium Parallel	Yebo	Cha

3.11. Ukuthuthukisa Idizayini Yakho
Ithebula 52. I-HDMI Design Example Ukuhambisana Nenguqulo Yesoftware Yangaphambilini ye-Intel Quartus Prime Pro Edition

I-Design Example Okuhlukile	Amandla Wokuthuthukela ku-Intel Quartus Prime Pro Edition 20.3
I-HDMI 2.0 Design Example (Ukusekela i-FRL = 0)	Cha

Ngokwanoma yimuphi umklamo ongahambelani exampngezansi, udinga ukwenza lokhu okulandelayo:

1. Khiqiza i-ex yedizayini entshaample enguqulweni yamanje yesofthiwe ye-Intel Quartus Prime Pro Edition usebenzisa ukulungiselelwa okufanayo komklamo wakho okhona.
2. Qhathanisa yonke i-ex yomklamoample lwemibhalo ne-ex designampikhiqizwe kusetshenziswa inguqulo yesoftware ye-Intel Quartus Prime Pro Edition yangaphambilini. Thumela izinguquko ezitholiwe.

I-HDCP Over HDMI 2.0/2.1 Design Example

I-HDCP phezu kwe-HDMI idizayini yehadiwe exampI-le ikusiza ukuthi uhlole ukusebenza kwesici se-HDCP futhi ikuvumela ukuthi usebenzise isici kumadizayini wakho we-Intel Arria 10.
Qaphela:
Isici se-HDCP asifakiwe kusofthiwe ye-Intel Quartus Prime Pro Edition. Ukuze ufinyelele isici se-HDCP, xhumana ne-Intel ku- https://www.intel.com/content/www/us/en/broadcast/products/programmable/applications/connectivity-solutions.html.

4.1. I-High-bandwidth Digital Content Protection (HDCP)
I-High-bandwidth Digital Content Protection (HDCP) iwuhlobo lokuvikelwa kwamalungelo edijithali ukuze udale uxhumano oluvikelekile phakathi komthombo nesibonisi.
I-Intel idale ubuchwepheshe bokuqala, obunikezwe ilayisense yiqembu le-Digital Content Protection LLC. I-HDCP iyindlela yokuvikela ikhophi lapho ukusakaza komsindo/ividiyo kubethelwe phakathi komthumeli nomamukeli, kuvikeleke ekukopishweni okungekho emthethweni.
Izici ze-HDCP zinamathela ku-HDCP Specification version 1.4 kanye nenguqulo ye-HDCP Specification 2.3.
I-HDCP 1.4 kanye ne-HDCP 2.3 IPs enza konke ukubala ngaphakathi kwe-hardware core logic ngaphandle kwamanani ayimfihlo (njengokhiye oyimfihlo nokhiye weseshini) afinyeleleka ngaphandle kwe-IP ebethelwe.

Ithebula 53. Imisebenzi ye-HDCP IP

I-HDCP IP	Imisebenzi
I-HDCP 1.4 IP	• Ukushintshanisa ubuqiniso - Ukubalwa kokhiye oyinhloko (Km) - Isizukulwane se-An - Ukubalwa kokhiye weseshini (Ks), M0 kanye no-R0. • Ukuqinisekisa ngokuphinda - Ukubalwa kanye nokuqinisekiswa kwe-V kanye ne-V' • Xhumanisa ubuqotho - Ukubalwa kokhiye wozimele (Ki), Mi no-Ri.
waqhubeka...

Inkampani ye-Intel Wonke Amalungelo Agodliwe. I-Intel, ilogo ye-Intel, nezinye izimpawu ze-Intel yizimpawu zokuthengisa ze-Intel Corporation noma izinkampani ezingaphansi kwayo. I-Intel iqinisekisa ukusebenza kwe-FPGA yayo kanye nemikhiqizo ye-semiconductor ekucacisweni kwamanje ngokuvumelana newaranti evamile ye-Intel, kodwa igodla ilungelo lokwenza izinguquko kunoma imiphi imikhiqizo namasevisi nganoma yisiphi isikhathi ngaphandle kwesaziso. I-Intel ayithathi mthwalo noma isikweletu esivele ngenxa yesicelo noma ukusetshenziswa kwanoma yiluphi ulwazi, umkhiqizo, noma isevisi echazwe lapha ngaphandle kwalapho okuvunyelwene ngakho ngokubhaliwe yi-Intel. Amakhasimende e-Intel ayelulekwa ukuthi athole inguqulo yakamuva yokucaciswa kwedivayisi ngaphambi kokuthembela kunoma yiluphi ulwazi olushicilelwe nangaphambi kokufaka ama-oda emikhiqizo noma amasevisi.
*Amanye amagama namabhrendi angafunwa njengempahla yabanye.

ISO
9001:2015
Ibhalisiwe

I-HDCP IP	Imisebenzi
	• Wonke amamodi e-cipher afaka i-hdcpBlockCipher, hdcpStreamCipher, hdcpRekeyCipher, ne-hdcpRngCipher • Isiginali yesimo sokubethela sangempela (i-DVI) kanye nokusayina kwesimo sokubethela okuthuthukisiwe (i-HDMI) • Ijeneretha yenombolo engahleliwe yeqiniso (TRNG) - I-Hardware esekelwe, ukuqaliswa okugcwele kwedijithali kanye nejeneretha yenombolo engahleliwe engahleliwe
I-HDCP 2.3 IP	• Ukhiye Omkhulu (km), Ukhiye Wesikhathi (ks) kanye nonce (rn, riv) ukukhiqiza - Ihambisana ne-NIST.SP800-90A ukukhiqizwa kwenombolo okungahleliwe • Ukuqinisekisa nokushintshisana okubalulekile - Ukukhiqizwa kwezinombolo ezingahleliwe ze-rtx ne-rrx ezithobela i-NIST.SP800-90A ukukhiqizwa kwenombolo okungahleliwe - Ukuqinisekiswa kwesiginesha yesitifiketi somamukeli (certrx) kusetshenziswa ukhiye womphakathi we-DCP (kpubdcp) — 3072 bits RSASSA-PKCS#1 v1.5 — I-RSAES-OAEP (PKCS#1 v2.1) ukubethela kanye nokuqanjwa kwe-Master Key (km) - Ukutholwa kwe-kd (dkey0, dkey1) kusetshenziswa imodi ye-AES-CTR - Ukubalwa kanye nokuqinisekiswa kwe-H no-H' - Ukubalwa kwe-Ekh (km) kanye ne-km (ukubhanqa) • Ukuqinisekisa ngokuphinda - Ukubalwa kanye nokuqinisekiswa kwe-V kanye ne-V' - Ukubalwa kanye nokuqinisekiswa kwe-M kanye ne-M' • Ukuvuselelwa Kwesistimu (SRM) - Ukuqinisekiswa kwesiginesha ye-SRM kusetshenziswa i-kpubdcp — 3072 bits RSASSA-PKCS#1 v1.5 • Ukushintshanisa ukhiye weSeshini • Ukukhiqizwa nokubalwa kwe-Edkey(ks) kanye ne-riv. • Ukukhishwa kwe-dkey2 kusetshenziswa imodi ye-AES-CTR • Ukuhlola Indawo - Ukubalwa kanye nokuqinisekiswa kwe-L no-L' - Isizukulwane se-nonce (rn) • Ukuphathwa kokusakaza kwedatha - Imodi ye-AES-CTR esekelwe ukukhiqizwa kokhiye wokusakaza • I-asymmetric crypto algorithms - I-RSA enobude bemodulus obungu-1024 (kpubrx) namabhithi angu-3072 (kpubdcp) - I-RSA-CRT (i-Chinese Remainder Theorem) enobude bemodulus obungamabhithi angu-512 (kprivrx) kanye nobude be-eksponenti obungamabhithi angu-512 (kprivrx) • Umsebenzi we-cryptographic osezingeni eliphansi - I-Symmetric crypto algorithms • Imodi ye-AES-CTR enobude bokhiye obungamabhithi angu-128 - I-Hash, i-MGF ne-HMAC algorithms • I-SHA256 • I-HMAC-SHA256 • MGF1-SHA256 - Ijeneretha yezinombolo ezingahleliwe (TRNG) • Ithobelana ne-NIST.SP800-90A • Izingxenyekazi zekhompuyutha, ukusetshenziswa okugcwele kwedijithali kanye nejeneretha yenombolo engahleliwe enganqunyelwe

4.1.1. I-HDCP Over HDMI Design Example Architecture
Isici se-HDCP sivikela idatha njengoba idatha idluliselwa phakathi kwamadivayisi axhunywe nge-HDMI noma ezinye izixhumanisi zedijithali ezivikelwe nge-HDCP.
Amasistimu avikelwe nge-HDCP afaka izinhlobo ezintathu zamadivayisi:

4. HDCP Over HDMI 2.0/2.1 Design Example
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• Imithombo (TX)
• Osinki (RX)
• Abaphindayo
Lo mklamo exampI-le ibonisa isistimu ye-HDCP kudivayisi ephindayo lapho yamukela khona idatha, isuse ukubethela, bese iphinda ibethela idatha, futhi ekugcineni ithumele kabusha idatha. Abaphindayo banakho kokubili okokufaka kwe-HDMI nokuphumayo. Iqinisekisa amabhafa e-FIFO ukwenza ukudlula kokusakaza kwevidiyo ye-HDMI eqondile phakathi kukasinki we-HDMI nomthombo. Ingase yenze ukucutshungulwa kwesignali, njengokuguqula amavidiyo abe yifomethi yokulungiswa okuphezulu ngokufaka amabhafa e-FIFO esikhundleni se-Video and Image Processing (VIP) Suite IP cores.

Umfanekiso 29. HDCP Over HDMI Design Example Block Diagram

Izincazelo ezilandelayo mayelana nezakhiwo ze-design exampihambisana ne-HDCP phezu kwe-HDMI design example block diagram. Lapho SEKELA FRL = 1 noma
SEKELA UKUPHATHWA KUKAkhiye we-HDCP = 1, i-ex designampI-le hierarchy ihluke kancane kuMfanekiso 29 ekhasini 95 kodwa imisebenzi eyisisekelo ye-HDCP ihlala ingu
okufanayo.

1. I-HDCP1x ne-HDCP2x ama-IP atholakala ngomhleli wepharamitha we-HDMI Intel FPGA IP. Uma ulungiselela i-HDMI IP kusihleli sepharamitha, unganika amandla futhi ufake phakathi i-HDCP1x noma i-HDCP2x noma womabili ama-IP njengengxenye yesistimu engaphansi. Ngawo womabili ama-IPs we-HDCP anikwe amandla, i-HDMI IP izilungiselela yona ku-cascade topology lapho i-HDCP2x kanye ne-HDCP1x IPs axhumeke ngokubuyela emuva.
   • I-HDCP egress interface ye-HDMI TX ithumela idatha yevidiyo yomsindo engabetheliwe.
   • Idatha engabetheliwe ibethelwa ibhulokhi ye-HDCP esebenzayo futhi ibuyiselwe ku-HDMI TX ngohlelo lwe-HDCP Ingress ukuze ludluliselwe ngesixhumanisi.
   • Isistimu engaphansi ye-CPU njengesilawuli esiyinhloko sokufakazela ubuqiniso iqinisekisa ukuthi eyodwa kuphela ye-HDCP TX IP esebenzayo noma nini futhi enye ayisebenzi.
   • Ngokufanayo, i-HDCP RX iphinda isuse ukubethela idatha etholwe ngesixhumanisi esivela ku-HDCP TX yangaphandle.
2. Udinga ukuhlela ama-IP we-HDCP ngokhiye bokukhiqiza abakhishiwe be-Digital Content Protection (DCP). Layisha okhiye abalandelayo:
   Ithebula 54. Izikhiye Zokukhiqiza ezikhishwe yi-DCP
   

   I-HDCP	I-TX / RX	Okhiye
   I-HDCP2x	TX	16 bytes: Global Constant (lc128)
   	RX	• 16 bytes (yafana ne-TX): Global Constant (lc128) • 320 bytes: RSA Private Key (kprivrx) • 522 bytes: I-RSA Public Key Certificate (certrx)
   I-HDCP1x	TX	• 5 bytes: TX Key Selection Vector (Aksv) • 280 bytes: TX Private Device Keys (Akeys)
   	RX	• 5 amabhayithi: IVector Yokukhetha Ukhiye we-RX (Bksv) • 280 bytes: RX Private Device Keys (Bkeys)

   Umklamo exampi-le isebenzisa izinkumbulo ezibalulekile njenge-double-port elula, i-RAM evunyelanisiwe yewashi elikabili. Ngosayizi omncane wokhiye njenge-HDCP2x TX, i-IP isebenzisa inkumbulo yokhiye isebenzisa amarejista ngomqondo ojwayelekile.
   Qaphela: I-Intel ayinikezi okhiye bokukhiqiza be-HDCP ne-ex yedizayiniample noma i-Intel FPGA IPs ngaphansi kwanoma yiziphi izimo. Ukusebenzisa i-HDCP IPs noma i-ex designampfuthi, kufanele ube yisamukeli se-HDCP futhi uthole okhiye bokukhiqiza ngokuqondile ku-Digital Content Protection LLC (DCP).
   Ukuze usebenzise i-design example, ungahlela inkumbulo yokhiye files ngesikhathi sokuhlanganiswa ukuze kufakwe okhiye bokukhiqiza noma ukusebenzisa amabhulokhi anengqondo ukuze ufunde ngokuphephile okhiye bokukhiqiza kusukela kudivayisi yesitoreji sangaphandle futhi ubabhale ezikhumbuzweni ezibalulekile ngesikhathi sokusebenza.

3. Ungakwazi ukuwasha imisebenzi ye-cryptographic esetshenziswe ku-HDCP2x IP nganoma iyiphi imvamisa efika ku-200 MHz. Ukuvama kwaleli washi kunquma ukuthi i-
   Ukuqinisekisa kwe-HDCP2x kuyasebenza. Ungakhetha ukwabelana ngewashi elingu-100 MHz elisetshenziselwa iphrosesa ye-Nios II kodwa ukubambezeleka kokuqinisekisa kuzophindwa kabili uma kuqhathaniswa nokusebenzisa iwashi elingu-200 MHz.
4. Amanani okufanele ananiswe phakathi kwe-HDCP TX ne-HDCP RX adluliselwa ku-HDMI DDC interface (I2 C serial interface) ye-HDCP-
   isikhombikubona esivikelekile. I-HDCP RX kufanele yethule idivayisi enengqondo ebhasini le-I2C kusixhumanisi ngasinye esisisekelayo. Isigqila se-I2C siphindwaphindwa embobeni ye-HDCP enekheli ledivayisi elingu-0x74. Ishayela imbobo yerejista ye-HDCP (i-Avalon-MM) yakho kokubili i-HDCP2x ne-HDCP1x RX IPs.
5. I-HDMI TX isebenzisa i-IC master ukufunda i-EDID ku-RX futhi idlulisele idatha ye-SCDC edingekayo ekusebenzeni kwe-HDMI 2.0 ku-RX. I-I2C master efanayo eshayelwa iphrosesa ye-Nios II iphinde isetshenziselwe ukudlulisa imilayezo ye-HDCP phakathi kwe-TX ne-RX. I-I2C master ishumekwe kusistimu engaphansi ye-CPU.
6. Iphrosesa ye-Nios II isebenza njengengcweti kuphrothokholi yokuqinisekisa futhi ishayela amarejista okulawula nesimo (i-Avalon-MM) kokubili kwe-HDCP2x ne-HDCP1x TX.
   IPs. Izishayeli zesofthiwe zisebenzisa umshini wombuso wephrothokholi wokuqinisekisa okufaka ukuqinisekiswa kwesiginesha yesitifiketi, ukushintshanisa kokhiye oyinhloko, ukuhlola kwendawo, ukushintshanisa ukhiye weseshini, ukumatanisa, ukuhlola ubuqotho besixhumanisi (HDCP1x), kanye nokuqinisekisa nabaphindayo, okufana nokusakazwa kolwazi lwe-topology kanye nokusakazwa kolwazi lokuphathwa kokusakaza. Izishayeli zesofthiwe awenzi noma yimiphi imisebenzi ye-cryptographic edingwa iphrothokholi yokuqinisekisa. Esikhundleni salokho, ihadiwe ye-HDCP IP isebenzisa yonke imisebenzi ye-cryptographic eqinisekisa ukuthi awekho amanani ayimfihlo angafinyelelwa.
   7. Embonisweni ophindaphindayo wangempela lapho ulwazi lwe-topology olusakazwayo ludingeka phezulu nomfula, iphrosesa ye-Nios II ishayela i-Repeater Message Port (Avalon-MM) yakho kokubili i-HDCP2x ne-HDCP1x RX IPs. Iphrosesa ye-Nios II isula ibhithi ye-RX REPEATER iye ku-0 uma ithola ukuthi umfula uxhumekile awukwazi i-HDCP noma uma kungekho umfula ongezansi oxhunyiwe. Ngaphandle koxhumano oluya phansi, isistimu ye-RX manje isiyisamukeli sephuzu lokugcina, esikhundleni sokuphindaphinda. Ngakolunye uhlangothi, iphrosesa ye-Nios II isetha i-RX REPEATER bit ku-1 lapho ithola ukuthi umfula ongezansi unamandla e-HDCP.

4.2. I-Nios II Processor Flow
I-flowchart yesofthiwe ye-Nios II ihlanganisa izilawuli zokuqinisekisa ze-HDCP kuhlelo lokusebenza lwe-HDMI.
Umfanekiso 30. Ishadi lokugeleza leSoftware yeProsesa ye-Nios II

1. Isofthiwe ye-Nios II iqalisa futhi isethe kabusha i-HDMI TX PLL, i-TX transceiver PHY, i-I2C master kanye nesibali sikhathi se-TI sangaphandle.
2. Isofthiwe ye-Nios II ihlola isignali yesilinganiso sezikhathi zokuvota evumelekile evela kumjikelezo wokutholwa kwesilinganiso se-RX ukuze inqume ukuthi ukulungiswa kwevidiyo kushintshile yini nokuthi ukulungiselelwa kabusha kwe-TX kuyadingeka yini. Isofthiwe iphinda ivotele isignali yokuhlonza ipulaki eshisayo ye-TX ukuze inqume ukuthi umcimbi we-TX hot-plug wenzekile yini.
3. Lapho isignali evumelekile itholwa kumjikelezo wokutholwa kwesilinganiso se-RX, isofthiwe ye-Nios II ifunda i-SCDC namanani okujula kwewashi ku-HDMI RX futhi ithola ibhendi yefrikhwensi yewashi ngokusekelwe esilinganisweni esitholiwe ukuze kunqunywe ukuthi i-HDMI TX PLL kanye ne-transceiver PHY ukulungiswa kabusha kuyadingeka. Uma ukulungiswa kabusha kwe-TX kudingekile, isofthiwe ye-Nios II iyala umphathi we-I2C ukuthi athumele inani le-SCDC ku-RX yangaphandle. Bese iyala ukulungisa kabusha i-HDMI TX PLL kanye ne-TX transceiver
   PHY, kulandelwa ukulinganisa kabusha kwedivayisi, nokusetha kabusha ukulandelana. Uma izinga lingashintshi, akukho ukumiswa kabusha kwe-TX noma ukuqinisekiswa kabusha kwe-HDCP okudingekayo.
4. Uma kwenzeke umcimbi we-TX hot-plug, isofthiwe ye-Nios II iyala inkosi ye-I2C ukuthi ithumele inani le-SCDC ku-RX yangaphandle, bese ifunda i-EDID esuka ku-RX.
   futhi ubuyekeze i-EDID RAM yangaphakathi. Isofthiwe ibe isisakaza ulwazi lwe-EDID phezulu.
5. Isofthiwe ye-Nios II iqala umsebenzi we-HDCP ngokuyala inkosi ye-I2C ukuthi ifunde i-offset 0x50 kusukela ku-RX yangaphandle ukuze ibone ukuthi umfula ongezansi uyakwazi yini i-HDCP, noma
   kungenjalo:
   • Uma inani le-HDCP2Version elibuyisiwe lingu-1, umfula ongezansi uyakwazi i-HDCP2x.
   • Uma inani elibuyisiwe lakho konke ukufundwa okungu-0x50 kungu-0, umfula ongezansi unamandla e-HDCP1x.
   • Uma inani elibuyisiwe lakho konke ukufundwa kwe-0x50 kungu-1, umfula ongezansi awukwazi amandla e-HDCP noma awusebenzi.
   • Uma ukuya phansi komfula ngaphambilini kungakwazi i-HDCP noma kungasebenzi kodwa okwamanje kunamandla e-HDCP, isofthiwe isetha i-REPEATER bit of the repeater upstream (RX) kuya ku-1 ukuze ibonise ukuthi i-RX manje isiphindaphinda.
   • Uma umfula ongezansi unakho i-HDCP kodwa okwamanje ayikwazi i-HDCP noma ingasebenzi, isofthiwe isetha i-REPEATER bit kuya ku-0 ukukhombisa ukuthi i-RX manje isiwumamukeli wephoyinti lokugcina.
6. Isofthiwe iqala iphrothokholi yokuqinisekisa ye-HDCP2x ehlanganisa ukuqinisekiswa kwesiginesha yesitifiketi se-RX, ukushintshanisa ukhiye oyinhloko, ukuhlola kwendawo, ukushintshanisa ukhiye weseshini, ukubhanqa, ukufakazela ubuqiniso nabaphindayo njengokusakazwa kolwazi lwe-topology.
7. Uma isesimweni sokuqinisekisa, isofthiwe ye-Nios II iyala umphathi we-I2C ukuthi enze inhlolovo irejista ye-RxStatus evela ku-RX yangaphandle, futhi uma isofthiwe ithola ibhithi elingu-REAUTH_REQ isethiwe, iqalisa ukufakazela ubuqiniso futhi ikhubaze ukubethela kwe-TX.
8. Uma umfula ongezansi uphindaphinda futhi i- READY bit yerejista ye-RxStatus isethelwe ku-1, lokhu ngokuvamile kubonisa ukuthi i-topology ye-downstream ishintshile. Ngakho, isofthiwe ye-Nios II iyala inkosi ye-I2C ukuthi ifunde i-ReceiverID_List kusukela ezansi nomfula futhi iqinisekise uhlu. Uma uhlu luvumelekile futhi lingekho iphutha le-topology elitholiwe, isofthiwe iqhubekela kumojula Yokulawula Ukusakaza Kokuqukethwe. Uma kungenjalo, iqala ukuqinisekiswa kabusha futhi ikhubaze ukubethela kwe-TX.
9. Isofthiwe ye-Nios II ilungiselela amanani we-ReceiverID_List kanye ne-RxInfo bese ibhalela imbobo yomlayezo we-Avalon-MM Repeater yokuphindaphinda umfudlana (RX). I-RX ibe isisakaza uhlu ku-TX yangaphandle (phezulu).
10. Ukufakazela ubuqiniso kuqediwe kuleli qophelo. Isoftware inika amandla ukubethela kwe-TX.
11. Isofthiwe iqala iphrothokholi yokuqinisekisa ye-HDCP1x ehlanganisa ukushintshanisa ukhiye kanye nokuqinisekisa ngabaphindayo.
12. Isofthiwe ye-Nios II yenza ukuhlola kobuqotho besixhumanisi ngokufunda nokuqhathanisa i-Ri' ne-Ri kusukela ku-RX yangaphandle (ezansi nomfula) kanye ne-HDCP1x TX ngokulandelanayo. Uma amanani
    akuhambisani, lokhu kubonisa ukulahleka kokuvumelanisa futhi isofthiwe iqala ukuqinisekiswa kabusha futhi ikhubaze ukubethela kwe-TX.
13. Uma umfula ongezansi uphindaphinda futhi i- READY bit yerejista ye-Bcaps isethelwe ku-1, lokhu ngokuvamile kubonisa ukuthi i-topology ye-downstream ishintshile. Ngakho-ke, isofthiwe ye-Nios II iyala inkosi ye-I2C ukuthi ifunde inani lohlu lwe-KSV kusukela ezansi nomfula futhi iqinisekise uhlu. Uma uhlu luvumelekile futhi lingekho iphutha le-topology elitholiwe, isofthiwe ilungiselela uhlu lwe-KSV kanye nevelu ye-Bstatus bese ibhalela imbobo yomlayezo we-Avalon-MM Repeater yokuphindaphinda umfula (RX). I-RX ibe isisakaza uhlu ku-TX yangaphandle (phezulu). Uma kungenjalo, iqala ukuqinisekiswa kabusha futhi ikhubaze ukubethela kwe-TX.

4.3. Design Walkthrough
Ukusetha nokusebenzisa i-HDCP nge-HDMI design example inezincezu ezinhlanutages.

1. Setha ihadiwe.
2. Khiqiza umklamo.
3. Hlela inkumbulo yokhiye we-HDCP files ukufaka okhiye bakho bokukhiqiza be-HDCP.
   a. Gcina okhiye abangenalutho bokukhiqiza be-HDCP ku-FPGA (Ukuphathwa Kokhiye Wokusekela we-HDCP = 0)
   b. Gcina okhiye bokukhiqiza be-HDCP ababethelwe kumemori yefuleshi yangaphandle noma i-EEPROM (Ukulawula Ukhiye Wokusekela we-HDCP = 1)
4. Hlanganisa umklamo.
5. View Imiphumela.

4.3.1. Setha i-Hardware
Eyokuqala stagi-e yomboniso ukusetha ihadiwe.
Uma SUPPORT FRL = 0, landela lezi zinyathelo ukuze usethe ihadiwe ukuze ubonise:

1. Xhuma ikhadi lendodakazi le-Bitec HDMI 2.0 FMC (inguqulo 11) kukhithi yokuthuthukisa ye-Arria 10 GX ethekwini le-FMC B.
2. Xhuma ikhithi yokuthuthukisa i-Arria 10 GX ku-PC yakho usebenzisa ikhebula le-USB.
3. Xhuma ikhebula le-HDMI elisuka kusixhumi se-HDMI RX ekhadini lendodakazi le-Bitec HDMI 2.0 FMC kudivayisi ye-HDCP enikwe amandla i-HDCP, njengekhadi lesithombe elikhipha i-HDMI.
4. Xhuma enye ikhebula ye-HDMI kusukela kusixhumi se-HDMI TX ekhadini lendodakazi le-Bitec HDMI 2.0 FMC kudivayisi ye-HDCP enikwe amandla i-HDCP, njengomabonakude onokufaka kwe-HDMI.

Uma SUPPORT FRL = 1, landela lezi zinyathelo ukuze usethe i-hardware ye ukuboniswa:

1. Xhuma ikhadi lendodakazi le-Bitec HDMI 2.1 FMC (Isibuyekezo 9) kukhithi yokuthuthukisa ye-Arria 10 GX ethekwini le-FMC B.
2. Xhuma ikhithi yokuthuthukisa i-Arria 10 GX ku-PC yakho usebenzisa ikhebula le-USB.
3. Xhuma izintambo ze-HDMI 2.1 Zesigaba 3 kusukela kusixhumi se-HDMI RX ekhadini lendodakazi le-Bitec HDMI 2.1 FMC emthonjeni onikwe amandla we-HDCP we-HDMI 2.1, njenge-Quantum Data 980 48G Generator.
4. Xhuma ezinye izintambo ze-HDMI 2.1 zeSigaba 3 kusukela kusixhumi se-HDMI TX ekhadini lendodakazi le-Bitec HDMI 2.1 FMC kusinki enikwe amandla i-HDCP ye-HDMI 2.1, njengokuthi
   I-Quantum Data 980 48G Analyzer.

4.3.2. Khiqiza Idizayini
Ngemuva kokusetha i-hardware, udinga ukukhiqiza umklamo.
Ngaphambi kokuthi uqale, qinisekisa ukufaka isici se-HDCP kusofthiwe ye-Intel Quartus Prime Pro Edition.

1. Chofoza Amathuluzi ➤ Ikhathalogi ye-IP, bese ukhetha i-Intel Arria 10 njengomndeni wedivayisi okuqondiswe kuyo.
   Qaphela: I-HDCP design example isekela kuphela i-Intel Arria 10 kanye namadivayisi we-Intel Stratix® 10.
2. Kukhathalogi ye-IP, thola bese uchofoza kabili i-HDMI Intel FPGA IP. Iwindi elisha lokwehluka kwe-IP liyavela.
3. Cacisa igama lezinga eliphezulu lokuhluka kwakho kwe-IP yangokwezifiso. Umhleli wepharamitha ugcina izilungiselelo zokuhlukahluka kwe-IP ku-a file okuthiwa .qsys noma .ip.
4. Chofoza okuthi KULUNGILE. Umhleli wepharamitha uyavela.
5. Kuthebhu ye-IP, lungiselela imingcele oyifunayo yakho kokubili i-TX ne-RX.
6. Vula ipharamitha Yosekelo lwe-HDCP 1.4 noma i-HDCP 2.3 ukuze ukhiqize i-ex yedizayini ye-HDCPample.
7. Vula ipharamitha Yokulawula Ukhiye Wokusekela i-HDCP uma ufuna ukugcina ukhiye wokukhiqiza we-HDCP ngefomethi ebethelwe kumemori yefuleshi yangaphandle noma i-EEPROM. Uma kungenjalo, vala ipharamitha Yokusekela Ukhiye Wokusekela I-HDCP ukuze ugcine ukhiye wokukhiqiza we-HDCP ngefomethi engenalutho ku-FPGA.
8. Ku-Design Exampkuthebhu, khetha i-Arria 10 HDMI RX-TX Retransmit.
9. Khetha i-Synthesis ukuze ukhiqize i-ex ye-hardware designample.
10. Okokukhiqiza File Fometha, khetha i-Verilog noma i-VHDL.
11. Ngekhithi Yokuthuthukisa Eqondiwe, khetha Ikhithi Yokuthuthukisa i-Arria 10 GX FPGA. Uma ukhetha ikhithi yokuthuthukisa, idivayisi eqondiwe (ekhethwe esinyathelweni sesi-4) iyashintsha ukuze ifane nedivayisi ekukhithi yokuthuthukisa. Nge-Arria 10 GX FPGA Development Kit, idivayisi ezenzakalelayo yi-10AX115S2F45I1SG.
12. Chofoza okuthi Khiqiza Isibample Design ukukhiqiza iphrojekthi files kanye nohlelo lwesofthiwe ye-Executable and Linking Format (ELF). file.

4.3.3. Faka okhiye bokukhiqiza be-HDCP
4.3.3.1. Gcina okhiye bokukhiqiza be-HDCP ku-FPGA (Ukhiye Wokusekela we-HDCP Ukuphatha = 0)
Ngemva kokukhiqiza idizayini, hlela inkumbulo yokhiye we-HDCP files ukufaka okhiye bakho bokukhiqiza.
Ukuze ufake okhiye bokukhiqiza, landela lezi zinyathelo.

1. Thola inkumbulo yokhiye elandelayo files kwe /rtl/hdcp/ umkhombandlela:
   • hdcp2x_tx_kmem.v
   • hdcp2x_rx_kmem.v
   • hdcp1x_tx_kmem.v
   • hdcp1x_rx_kmem.v
2. Vula ifayela le-hdcp2x_rx_kmem.v file futhi thola ukhiye wefeksi ochazwe ngaphambilini u-R1 Womamukeli Wesitifiketi Sikahulumeni kanye ne-RX Private Key kanye ne-Global Constant njengoba kuboniswe ku-ex.ampngaphansi.
   Umfanekiso 31. Uhlu Lwezintambo Lwefaksi Ukhiye R1 Womamukeli Wesitifiketi Sikahulumeni
   Umfanekiso 32. I-Wire Array ye-Facsimile Key R1 ye-RX Private Key kanye ne-Global Constant
   
3. Thola isimeli sokhiye bokukhiqiza bese ubuyisela okhiye bakho bokukhiqiza ohlwini lwazo olulandelanayo ngefomethi enkulu ye-endian.
   Umfanekiso 33. Uchungechunge Lwezintambo Lokhiye Bokukhiqiza be-HDCP (Isimeli)
   
4. Phinda Isinyathelo sesi-3 ngayo yonke enye inkumbulo yokhiye files. Uma usuqedile ukufaka okhiye bakho bokukhiqiza kuyo yonke imemori yokhiye files, qinisekisa ukuthi ipharamitha ye-USE_FACSIMILE isethwe ukuze ithi 0 ku-ex designampizinga eliphezulu file (a10_hdmi2_demo.v)

4.3.3.1.1. Imephu yokhiye we-HDCP kusuka kukhiye we-DCP Files
Izigaba ezilandelayo zichaza ukwenziwa kwemephu kokhiye bokukhiqiza be-HDCP abagcinwe kukhiye we-DCP files ohlwini lwezintambo ze-HDCP kmem files.
4.3.3.1.2. hdcp1x_tx_kmem.v kanye ne-hdcp1x_rx_kmem.v files
Okwe-hdcp1x_tx_kmem.v kanye ne-hdcp1x_rx_kmem.v files

• Laba ababili files babelana ngefomethi efanayo.
• Ukuze uhlonze ukhiye olungile we-HDCP1 TX DCP file nge-hdcp1x_tx_kmem.v, qiniseka ukuthi amabhayithi angu-4 okuqala file kukhona “0x01, 0x00, 0x00, 0x00”.
• Ukuze uhlonze ukhiye olungile we-HDCP1 RX DCP file nge-hdcp1x_rx_kmem.v, qiniseka ukuthi amabhayithi angu-4 okuqala file kukhona “0x02, 0x00, 0x00, 0x00”.
• Okhiye kukhiye we-DCP files akufomethi encane-endian. Ukuze usebenzise ku-km files, kuzomele uwaguqule abe yi-big-endian.

Umfanekiso 34. Imephu ye-Byte kusuka kukhiye we-HDCP1 TX DCP file ku-hdcp1x_tx_kmem.v

Qaphela:
Inombolo yebhayithi iboniswa ngefomethi engezansi:

• Usayizi wokhiye ngamabhayithi * inombolo yokhiye + inombolo yebhayithi kumugqa wamanje + ukususa okungashintshi + usayizi womugqa ngamabhayithi * inombolo yomugqa.
• 308*n ikhombisa ukuthi isethi ngayinye yokhiye inamabhayithi angu-308.
• U-7*y ukhombisa ukuthi umugqa ngamunye unamabhayithi ayi-7.

Umfanekiso 35. Ukhiye we-HDCP1 TX DCP file ukugcwalisa amanani odoti

Umfanekiso 36. Izintambo zocingo ze-hdcp1x_tx_kmem.v
Example ye-hdcp1x_tx_kmem.v nokuthi izintambo zocingo lwayo zenza kanjani imephu eya kwakudalaampukhiye we-HDCP1 TX DCP file kuMfanekiso 35 ekhasini 105.

4.3.3.1.3. hdcp2x_rx_kmem.v file
Okwe-hdcp2x_rx_kmem.v file

• Ukuze uhlonze ukhiye olungile we-HDCP2 RX DCP file nge-hdcp2x_rx_kmem.v, qiniseka ukuthi amabhayithi angu-4 okuqala file kukhona “0x00, 0x00, 0x00, 0x02”.
• Okhiye kukhiye we-DCP files akufomethi encane-endian.

Umfanekiso 37. Imephu ye-Byte kusuka kukhiye we-HDCP2 RX DCP file ku-hdcp2x_rx_kmem.v
Umfanekiso ongezansi ubonisa imephu ye-byte ngqo kusuka kukhiye we-HDCP2 RX DCP file ku-hdcp2x_rx_kmem.v.

Qaphela:
Inombolo yebhayithi iboniswa ngefomethi engezansi:

• Usayizi wokhiye ngamabhayithi * inombolo yokhiye + inombolo yebhayithi kumugqa wamanje + ukususa okungashintshi + usayizi womugqa ngamabhayithi * inombolo yomugqa.
• 862*n ikhombisa ukuthi isethi ngayinye yokhiye inamabhayithi angu-862.
• 16*y ukhombisa ukuthi umugqa ngamunye unamabhayithi ayi-16. Kukhona okuhlukile ku-cert_rx_prod lapho i-ROW 32 inamabhayithi angu-10 kuphela.

Umfanekiso 38. Ukhiye we-HDCP2 RX DCP file ukugcwalisa amanani odoti

Umfanekiso 39. Izintambo zocingo ze-hdcp2x_rx_kmem.v
Lesi sibalo sibonisa izintambo zezintambo ze-hdcp2x_rx_kmem.v (cert_rx_prod, kprivrx_qinv_prod, kanye ne-lc128_prod) imephu kuya ku-exampukhiye we-HDCP2 RX DCP file in
Umdwebo 38 ekhasini 108.

4.3.3.1.4. hdcp2x_tx_kmem.v file
Okwe-hdcp2x_tx_kmem.v file:

• Ukuze uhlonze ukhiye olungile we-HDCP2 TX DCP file nge-hdcp2x_tx_kmem.v, qiniseka ukuthi amabhayithi angu-4 okuqala file kukhona “0x00, 0x00, 0x00, 0x01”.
• Okhiye kukhiye we-DCP files akufomethi encane-endian.
• Kungenjalo, ungasebenzisa i-lc128_prod esuka ku-hdcp2x_rx_kmem.v ngokuqondile ku-hdcp2x_tx_kmem.v. Okhiye babelana ngamavelu afanayo.

Umfanekiso 40. Izintambo eziningi ze-hdcp2x_tx_kmem.v
Lesi sibalo sibonisa imephu ye-byte ngqo kusuka kukhiye we-HDCP2 TX DCP file ku-hdcp2x_tx_kmem.v.

4.3.3.2. Gcina okhiye bokukhiqiza be-HDCP ababethelwe kumemori ye-flash yangaphandle noma I-EEPROM (Ukusekela Ukuphathwa Kokhiye we-HDCP = 1)
Umfanekiso 41. Izinga Eliphezulu Ngaphezuluview yokuphathwa kokhiye we-HDCP

Lapho ipharamitha Yokulawula Ukhiye Wokusekela i-HDCP ivuliwe, ubamba ukulawula ukubethela kokhiye wokukhiqiza we-HDCP ngokusebenzisa insiza yesofthiwe yokubethela engukhiye (KEYENC) kanye nedizayini yokhiye yomhleli ehlinzekwa yi-Intel. Kufanele unikeze ngokhiye bokukhiqiza be-HDCP kanye nokhiye wokuvikela we-HDCP wamabhithi angu-128. Ukhiye wokuvikela we-HDCP
ibhala ngemfihlo ukhiye wokukhiqiza we-HDCP futhi igcine ukhiye kumemori yefuleshi yangaphandle (isibample, EEPROM) ekhadini lendodakazi ye-HDMI.
Vula ipharamitha Yokulawula Ukhiye Wokusekela we-HDCP kanye nesici sokhiye sokususa ukubethela (KEYDEC) siyatholakala kuma-HDCP IP cores. Ukuvikelwa okufanayo kwe-HDCP
ukhiye kufanele usetshenziswe ku-KEYDEC ukuze kutholwe okhiye bokukhiqiza be-HDCP ngesikhathi sokuqalisa sokucubungula izinjini. I-KEYENC ne-KEYDEC zisekela i-Atmel AT24CS32 32-Kbit serial EEPROM, i-Atmel AT24C16A 16-Kbit serial EEPROM namadivayisi ahambisanayo e-I2C EEPROM anosayizi we-rom okungenani ongu-16-Kbit.

Qaphela:

1. Ngekhadi lendodakazi ye-HDMI 2.0 FMC Revision 11, qiniseka ukuthi i-EEPROM ekhadini lendodakazi ithi Atmel AT24CS32. Kukhona osayizi ababili abahlukene be-EEPROM abasetshenziswe ku-Bitec HDMI 2.0 FMC ikhadi lendodakazi Revision 11.
2. Uma ngaphambilini ubusebenzise i-KEYENC ukuze ubethele okhiye bokukhiqiza be-HDCP futhi wavula Ukuphathwa Kokhiye Wokusekela i-HDCP enguqulweni engu-21.2 noma yangaphambilini, udinga ukubethela kabusha okhiye bokukhiqiza be-HDCP usebenzisa insiza yesofthiwe ye-KEYENC futhi ukhiqize kabusha ama-HDCP IPs kusukela kunguqulo 21.3
   kuya phambili.

4.3.3.2.1. I-Intel KEYENC
I-KEYENC insiza yesofthiwe yomugqa womyalo i-Intel eyisebenzisayo ukuze ibethele okhiye bokukhiqiza be-HDCP ngokhiye wokuvikela we-HDCP wamabhithi angu-128 owunikezayo. Imiphumela ye-KEYENC ebethelwe okhiye bokukhiqiza be-HDCP ku-hex noma kubhini noma unhlokweni file ifomethi. I-KEYENC iphinde ikhiqize i-mif file iqukethe ukhiye wakho wokuvikela we-HDCP wamabhithi angu-128 onikeziwe. KEYDEC
idinga i-mif file.

Isidingo Sesistimu:

1. umshini we-x86 64-bit one-Windows 10 OS
2. Iphakheji ebonakalayo ye-C++ Esabalaliswa kabusha ye-Visual Studio 2019(x64)

Qaphela:
Kufanele ufake i-Microsoft Visual C++ ye-VS 2019. Ungahlola ukuthi i-Visual C++ esakwazi ukusabalalisa kabusha ifakiwe ku-Windows ➤ Iphaneli Yokulawula ➤ Izinhlelo Nezici. Uma i-Microsoft Visual C++ ifakiwe, ungabona i-Visual C++ xxxx
Ingasabalaliswa kabusha (x64). Uma kungenjalo, ungalanda futhi ufake i-Visual C++
Ingasabalaliswa kabusha kwa-Microsoft webindawo. Bheka ulwazi oluhlobene ukuze uthole isixhumanisi sokulanda.

Ithebula 55. Izinketho ze-KEYENC Command Line

Izinketho Zomugqa Womyalo	Ingxabano/Incazelo
-k	<HDCP protection key file> Umbhalo file equkethe kuphela ukhiye wokuvikela we-HDCP wamabhithi angu-128 ku-hexadecimal. Example: f0f1f2f3f4f5f6f7f8f9fafbfcfdfeff
-hdcp1tx	<HDCP 1.4 TX production keys file> Okhiye bokukhiqiza be-HDCP 1.4 transmitter file kusuka ku-DCP (.bin file)
-hdcp1rx	<HDCP 1.4 RX production keys file> Okhiye bokukhiqiza abamukeli be-HDCP 1.4 file kusuka ku-DCP (.bin file)
-hdcp2tx	<HDCP 2.3 TX production keys file> Okhiye bokukhiqiza be-HDCP 2.3 transmitter file kusuka ku-DCP (.bin file)
-hdcp2rx	<HDCP 2.3 RX production keys file> Okhiye bokukhiqiza abamukeli be-HDCP 2.3 file kusuka ku-DCP (.bin file)
-hdcp1txkeys	Cacisa ububanzi bokhiye bokufakwayo okukhethiwe (.bin) files -hdcp1txkeys|hdcp1rxkeys|hdcp2rxkeys nm lapho n = isiqalo sokhiye (1 noma >1) m = isiphetho sikakhiye (n noma >n) Example: Khetha okhiye abangu-1 kuye ku-1000 ku-HDCP 1.4 TX ngayinye, HDCP 1.4 RX ne-HCDP 2.3 okhiye bokukhiqiza be-RX file. “-hdcp1txkeys 1-1000 -hdcp1rxkeys 1-1000 -hdcp2rxkeys 1-1000”
-hdcp1rxkeys
-hdcp2rxkeys
waqhubeka...

Izinketho Zomugqa Womyalo	Ingxabano/Incazelo
	Qaphela: 1. Uma ungasebenzisi noma yibaphi okhiye bokukhiqiza be-HDCP file, ngeke udinge ububanzi bokhiye be-HDCP. Uma ungasebenzisi i-agumenti kulayini womyalo, ububanzi bokhiye obumisiwe ngu-0. 2. Ungakwazi futhi ukukhetha inkomba ehlukile yokhiye bokhiye bokukhiqiza be-HDCP file. Nokho, inani lokhiye kufanele lifane nezinketho ezikhethiwe. Example: Khetha okhiye abayi-100 abahlukene Khetha okhiye bokuqala abangu-100 kusukela kokhiye bokukhiqiza be-HDCP 1.4 TX file “-hdcp1txkeys 1-100” Khetha okhiye abangu-300 ukuya ku-400 ngokhiye bokukhiqiza be-HDCP 1.4 RX file "-hdcp1rxkeys 300-400" Khetha okhiye abangu-600 ukuya ku-700 ngokhiye bokukhiqiza be-HDCP 2.3 RX file "-hdcp2rxkeys 600-700"
-o	Okukhiphayo file ifomethi . Okuzenzakalelayo yi-hex file. Khiqiza okhiye bokukhiqiza be-HDCP ababethelwe kukhombambili file ifomethi: -o bin Khiqiza okhiye bokukhiqiza be-HDCP ababethelwe ku-hex file ifomethi: -o hex Khiqiza okhiye bokukhiqiza be-HDCP ababethelwe kunhlokweni file ifomethi: -oh
-hlola-okhiye	Inombolo yokuphrinta yokhiye abatholakalayo kokokufaka files. Isbample:
	keyenc.exe -hdcp1tx file> -hdcp1rx <HDCP 1.4 RX production keys file> -hdcp2tx file> -hdcp2rx file> -hlola-okhiye
	Qaphela: sebenzisa ipharamitha -check-keys ekugcineni komugqa womyalo njengoba kushiwo ngenhla example.
-inguqulo	Phrinta inombolo yenguqulo ye-KEYENC

Ungakhetha ngokukhetha okhiye bokukhiqiza be-HDCP 1.4 kanye/noma be-HDCP 2.3 ukuze ubabethele. Okwesiboneloample, ukusebenzisa kuphela okhiye bokukhiqiza be-HDCP 2.3 RX ukuze ubethele, sebenzisa kuphela -hdcp2rx
<HDCP 2.3 RX production keys file> -hdcp2rxkeys kumapharamitha womugqa womyalo.
Ithebula 56. Umhlahlandlela Womlayezo Wephutha Elivamile le-KEYENC

Umlayezo Wephutha	Isiqondiso
IPHUTHA: Ukhiye wokuvikela we-HDCP file engekho	Ipharamitha yomugqa womyalo engekho -k file>
IPHUTHA: ukhiye kufanele ube amadijithi angu-32 hex (isb. f0f1f2f3f4f5f6f7f8f9fafbfcfdfeff)	Ukhiye wokuvikela we-HDCP file kufanele iqukathe kuphela ukhiye wokuvikela we-HDCP ngamadijithi angu-32 hexadecimal.
IPHUTHA: Sicela ucacise ububanzi bokhiye	Ububanzi bokhiye abucacisiwe kokufakwayo okhiye bokukhiqiza be-HDCP file.
IPHUTHA: Ibanga lokhiye elingavumelekile	Ububanzi bokhiye obucaciswe ku- -hdcp1txkeys noma -hdcp1rxkeys noma -hdcp2rxkeys alilungile.
IPHUTHA: ayikwazi ukudalaFileigama>	Hlola imvume yefolda evela ku-keyenc.exe esebenzayo.
IPHUTHA: -hdcp1txkeys okokufaka akuvumelekile	Ifomethi yohlu lokhiye wokufaka yokhiye bokukhiqiza be-HDCP 1.4 TX ayivumelekile. Ifomethi elungile ithi “-hdcp1txkeys nm” lapho n >= 1, m >= n
IPHUTHA: -hdcp1rxkeys okokufaka akuvumelekile	Ifomethi yohlu lokhiye wokufaka yokhiye bokukhiqiza be-HDCP 1.4 RX ayivumelekile. Ifomethi elungile ithi “-hdcp1rxkeys nm” lapho n >= 1, m >= n
IPHUTHA: -hdcp2rxkeys okokufaka akuvumelekile	Ifomethi yohlu lokhiye wokufaka yokhiye bokukhiqiza be-HDCP 2.3 RX ayivumelekile. Ifomethi elungile ithi “-hdcp2rxkeys nm” lapho n >= 1, m >= n
waqhubeka...

Umlayezo Wephutha	Isiqondiso
IPHUTHA: Akuvumelekile file <fileigama>	Okhiye bokukhiqiza be-HDCP abangavumelekile file.
IPHUTHA: file uhlobo olulahlekile lwe- -o inketho	Ipharamitha yomugqa womyalo ayikho yokuthi -o .
IPHUTHA: akuvumelekile fileigama -fileigama>	<fileIgama> alivumelekile, sicela usebenzise elivumelekile fileigama elingenazo izinhlamvu ezikhethekile.

Bethela Ukhiye Owodwa we-EEPROM Eyodwa
Qalisa umugqa womyalo olandelayo kusuka kumyalo womyalo we-Windows ukuze ubethele ukhiye owodwa we-HDCP 1.4 TX, HDCP 1.4 RX, HDCP 2.3 TX kanye ne-HDCP 2.3 RX ngokukhiphayo file ifomethi kanhlokweni file nge-EEPROM eyodwa:
keyenc.exe -k file> -hdcp1tx file> -hdcp1rx file> -hdcp2tx file> -hdcp2rx file> -hdcp1txkeys 1-1 -hdcp1rxkeys 1-1 -hdcp2rxkeys 1-1 -oh

Bethela okhiye abangu-N kuma-N EEPROM
Qalisa umugqa womyalo olandelayo kusuka kumyalo womyalo we-Windows ukuze ubethele okhiye abangu-N (kusukela kukhiye 1) we-HDCP 1.4 TX, HDCP 1.4 RX, HDCP 2.3 TX kanye ne-HDCP 2.3 RX ngokukhiphayo file ifomethi ye-hex file kuma-N EEPROM:
keyenc.exe -k file> -hdcp1tx file> -hdcp1rx file> -hdcp2tx file> -hdcp2rx file> -hdcp1txkeys 1 -hdcp1rxkeys 1- -hdcp2rxkeys 1- -o i-hex lapho okuthi N >= 1 futhi kufanele ifane nazo zonke izinketho.

Ulwazi Oluhlobene
I-Microsoft Visual C++ ye-Visual Studio 2019
Ihlinzeka ngephakheji ye-Microsoft Visual C++ x86 esabalaliswa kabusha (vc_redist.x86.exe) ukuze ilandwe. Uma isixhumanisi sishintsha, i-Intel incoma ukuthi useshe okuthi “Visual C++ esakwazi ukusabalalisa kabusha” enjinini yokusesha ye-Microsoft.

4.3.3.2.2. Umhleli Obalulekile
Ukuze uhlele okhiye bokukhiqiza be-HDCP ababethelwe ku-EEPROM, landela lezi zinyathelo:

1. Kopisha idizayini yokhiye wohlelo files kusuka endleleni elandelayo eya kunkomba yakho yokusebenza: /hdcp2x/hw_demo/key_programmer/
2. Kopisha unhlokweni wesofthiwe file (hdcp_key .h) ekhiqizwe ensizeni yesofthiwe ye-KEYENC (isigaba Bethela Ukhiye Owodwa we-EEPROM Eyodwa ekhasini 113 ) kuya ku-software/key_programmer_src/ lwemibhalo futhi uyiqambe kabusha ngokuthi hdcp_key.h.
3. Gijimani ./runall.tcl. Lesi script senza imiyalo elandelayo:
   • Khiqiza ikhathalogi ye-IP files
   • Khiqiza isistimu yoMklami Wenkundla
   • Dala iphrojekthi ye-Intel Quartus Prime
   • Dala indawo yokusebenza yesofthiwe futhi wakhe isofthiwe
   • Yenza iqoqo eliphelele
4. Landa i-Software Object File (.sof) ku-FPGA ukuze kuhlelwe okhiye bokukhiqiza be-HDCP ababethelwe ku-EEPROM.

Khiqiza i-Stratix 10 HDMI RX-TX Retransmit design example nge-Support HDCP 2.3 kanye namapharamitha wokusekela we-HDCP 1.4 avuliwe, bese ulandela isinyathelo esilandelayo ukuze ufake ukhiye wokuvikela we-HDCP.

• Kopisha i-mif file (hdcp_kmem.mif) ekhiqizwe ensizeni yesoftware ye-KEYENC (isigaba Bethela Ukhiye Owodwa we-EEPROM Eyodwa ekhasini 113) kuya ku- /quartus/hdcp/ umkhombandlela.

4.3.4. Hlanganisa Umklamo
Ngemva kokuthi ufake owakho okhiye bokukhiqiza be-HDCP ku-FPGA noma ukuhlela okhiye bokukhiqiza be-HDCP ababethelwe ku-EEPROM, manje usungakwazi ukuhlanganisa idizayini.

1. Yethula isofthiwe ye-Intel Quartus Prime Pro Edition futhi uvule /quartus/a10_hdmi2_demo.qpf.
2. Chofoza Ukucubungula ➤ Qala Ukuhlanganisa.

4.3.5. View Imiphumela
Ekupheleni komboniso, uzokwazi view imiphumela kusinki yangaphandle ye-HDCPenabled HDMI.
Kuya view imiphumela yomboniso, landela lezi zinyathelo:

1. Nika amandla ibhodi le-Intel FPGA.
2. Shintsha uhla lwemibhalo lube /ikwata/.
3. Thayipha umyalo olandelayo ku-Nios II Command Shell ukuze ulande i-Software Object File (.sof) ku-FPGA. nios2-configure-sof output_files/ .sof
4. Nika amandla umthombo wangaphandle we-HDCP onikwe amandla i-HDCP kanye usinki (uma ungenzanga kanjalo). Usinki wangaphandle we-HDMI ubonisa okukhiphayo komthombo wakho wangaphandle we-HDMI.

4.3.5.1. I-Push Button kanye nemisebenzi ye-LED
Sebenzisa izinkinobho zokucindezela kanye nemisebenzi ye-LED ebhodini ukuze ulawule ukuboniswa kwakho.

Ithebula 57. Inkinobho Yokusunduza kanye Nezinkomba ze-LED (SUPPORT FRL = 0)

Cindezela inkinobho/I-LED	Imisebenzi
cpu_resetn	Cindezela kanye ukuze wenze kabusha uhlelo.
umsebenzisi_pb[0]	Cindezela kanye ukuze uguqule isignali ye-HPD iye emthonjeni ojwayelekile we-HDMI.
umsebenzisi_pb[1]	• Cindezela bese ubamba ukuze uyalele i-TX core ukuthumela isignali enekhodi ye-DVI. • Khipha ukuze uthumele isignali enekhodi ye-HDMI. • Qiniseka ukuthi ividiyo engenayo ingaphakathi kwesikhala sombala esingu-8 bpc RGB.
umsebenzisi_pb[2]	• Cindezela bese ubamba ukuze uyalele i-TX core ukuthi iyeke ukuthumela ama-InfoFrames esuka kumasignali ebhendi eseceleni. • Khulula ukuze uqalise kabusha ukuthumela ama-InfoFrames kusuka kumasiginali ebhendi eseceleni.
oholwa ngabasebenzisi[0]	Isimo sokukhiya i-RX HDMI PLL. • 0: Ivuliwe • 1: Ikhiyiwe
oholwa ngabasebenzisi[1]	Isimo se-RX HDMI core lock • 0: Okungenani isiteshi esingu-1 sivuliwe • 1: Zonke iziteshi ezi-3 zikhiyiwe
oholwa ngabasebenzisi[2]	Isimo sokuqanjwa kwe-RX HDCP1x IP. • 0: Ayisebenzi • 1: Iyasebenza
oholwa ngabasebenzisi[3]	Isimo sokuqanjwa kwe-RX HDCP2x IP. • 0: Ayisebenzi • 1: Iyasebenza
oholwa ngabasebenzisi[4]	Isimo sokukhiya i-TX HDMI PLL. • 0: Ivuliwe • 1: Ikhiyiwe
oholwa ngabasebenzisi[5]	Isimo sokukhiya i-TX transceiver PLL. • 0: Ivuliwe • 1: Ikhiyiwe
oholwa ngabasebenzisi[6]	Isimo sokubethela se-TX HDCP1x IP. • 0: Ayisebenzi • 1: Iyasebenza
oholwa ngabasebenzisi[7]	Isimo sokubethela se-TX HDCP2x IP. • 0: Ayisebenzi • 1: Iyasebenza

Ithebula 58. Inkinobho Yokusunduza kanye Nezinkomba ze-LED (SUPPORT FRL = 1)

Cindezela inkinobho/I-LED	Imisebenzi
cpu_resetn	Cindezela kanye ukuze wenze kabusha uhlelo.
umsebenzisi_dipsw	Iswishi ye-DIP echazwe umsebenzisi ukuze uguqule imodi yokudlula. • VALIWE (isikhundla esimisiwe) = Ukudlula I-HDMI RX ku-FPGA ithola i-EDID kusinki wangaphandle futhi iyethule emthonjeni ongaphandle exhunywe kuwo. • IVULIWE = Ungalawula isilinganiso esiphezulu se-RX se-FRL kutheminali ye-Nios II. Umyalo ulungisa i-RX EDID ngokukhohlisa inani eliphezulu lezinga le-FRL. Bukela ku Isebenzisa Idizayini Ngamazinga Ahlukene e-FRL ekhasini 33 ukuze uthole ulwazi olwengeziwe mayelana nokusetha amazinga e-FRL ahlukene.
waqhubeka...

Cindezela inkinobho/I-LED	Imisebenzi
umsebenzisi_pb[0]	Cindezela kanye ukuze uguqule isignali ye-HPD iye emthonjeni ojwayelekile we-HDMI.
umsebenzisi_pb[1]	Igodliwe.
umsebenzisi_pb[2]	Cindezela kanye ukuze ufunde amarejista e-SCDC kusinki exhunywe ku-TX yekhadi lendodakazi le-Bitec HDMI 2.1 FMC. Qaphela: Ukuze unike amandla ukufunda, kufanele usethe i-DEBUG_MODE ibe ngu-1 kusofthiwe.
user_led_g[0]	Isimo sokukhiya iwashi le-RX FRL PLL. • 0: Ivuliwe • 1: Ikhiyiwe
user_led_g[1]	Isimo sokukhiya ividiyo ye-RX HDMI. • 0: Ivuliwe • 1: Ikhiyiwe
user_led_g[2]	Isimo sokuqanjwa kwe-RX HDCP1x IP. • 0: Ayisebenzi • 1: Iyasebenza
user_led_g[3]	Isimo sokuqanjwa kwe-RX HDCP2x IP. • 0: Ayisebenzi • 1: Iyasebenza
user_led_g[4]	Isimo sokukhiya iwashi le-TX FRL PLL. • 0: Ivuliwe • 1: Ikhiyiwe
user_led_g[5]	Isimo sokukhiya ividiyo ye-TX HDMI. • 0 = Ivuliwe • 1 = Ikhiyiwe
user_led_g[6]	Isimo sokubethela se-TX HDCP1x IP. • 0: Ayisebenzi • 1: Iyasebenza
user_led_g[7]	Isimo sokubethela se-TX HDCP2x IP. • 0: Ayisebenzi • 1: Iyasebenza

4.4. Ukuvikelwa Kokhiye Wokubethela Ushumekwe Kumklamo we-FPGA
Imiklamo eminingi ye-FPGA isebenzisa ukubethela, futhi kuvame ukuba nesidingo sokushumeka okhiye abayimfihlo ku-FPGA bitstream. Emindenini emisha yedivayisi, njenge-Intel Stratix 10 ne-Intel Agilex, kukhona ibhulokhi Yesiphathi Sedivayisi Evikelekile esingahlinzeka ngokuvikelekile futhi silawule labo khiye abayimfihlo. Lapho lezi zici zingekho khona, ungakwazi ukuvikela okuqukethwe kwe-bitstream ye-FPGA, okuhlanganisa noma yibaphi okhiye abashumekiwe abayimfihlo bomsebenzisi, ngokubhala ngemfihlo.
Okhiye bomsebenzisi kufanele bagcinwe bevikelekile ngaphakathi kwendawo yakho yokuklama, futhi ngokufanelekile wengeze ekwakhiweni usebenzisa inqubo evikelekile ezenzakalelayo. Izinyathelo ezilandelayo zibonisa ukuthi ungayisebenzisa kanjani inqubo enjalo ngamathuluzi we-Intel Quartus Prime.

1. Thuthukisa futhi ulungiselele i-HDL ku-Intel Quartus Prime endaweni engavikelekile.
2. Dlulisela idizayini endaweni evikelekile futhi usebenzise inqubo ezenzakalelayo ukuze ubuyekeze ukhiye oyimfihlo. Imemori eku-chip ishumeka inani lokhiye. Uma ukhiye ubuyekezwa, ukuqaliswa kwememori file (.mif) ingashintsha futhi ukugeleza kwesihlanganisi esithi “quartus_cdb –update_mif” kungashintsha ukhiye wokuvikela we-HDCP ngaphandle kokuhlanganisa kabusha. Lesi sinyathelo siyashesha kakhulu ukusebenza futhi sigcina isikhathi sokuqala.
3. I-Intel Quartus Prime bitstream bese ibhala ngemfihlo ngokhiye we-FPGA ngaphambi kokudlulisa i-bitstream ebethelwe ibuyele endaweni engavikelekile ukuze ihlolwe okokugcina futhi isetshenziswe.

Kunconywa ukukhubaza konke ukufinyelela kokususa iphutha okungabuyisa ukhiye oyimfihlo ku-FPGA. Ungakhubaza amandla okususa iphutha ngokuphelele ngokukhubaza i-JTAG port, noma khubaza ngokukhetha bese uphindeview ukuthi azikho izici zokususa iphutha ezifana nomhleli wememori yangaphakathi nohlelo noma i-Signal Tap engabuyisa ukhiye. Bheka i-AN 556: Ukusebenzisa Izici Zokuvikela Zokuklama kuma-Intel FPGA ukuze uthole ulwazi olwengeziwe ngokusebenzisa izici zokuphepha ze-FPGA okuhlanganisa nezinyathelo ezithile zokubethela i-FPGA bitstream futhi ulungiselele izinketho zokuphepha ezifana nokukhubaza i-J.TAG ukufinyelela.

Qaphela:
Ungacabangela isinyathelo esengeziwe sokufiphaza noma ukubethela ngomunye ukhiye wokhiye oyimfihlo kusitoreji se-MIF.
Ulwazi Oluhlobene
I-AN 556: Ukusebenzisa Izici Zokuvikela Zokuklama kuma-Intel FPGAs

4.5. Ukucatshangelwa Kokuphepha
Uma usebenzisa isici se-HDCP, khumbula ukucatshangelwa kokuvikeleka okulandelayo.

• Lapho uklama isistimu ephindayo, kufanele uvimbele ividiyo eyamukelwe ukuthi ingangeni ku-TX IP ngaphansi kwezimo ezilandelayo:
  — Uma ividiyo etholiwe ibethelwe nge-HDCP (okungukuthi isimo sokubethela hdcp1_enabled noma i-hdcp2_enabled kusuka ku-RX IP kuyagonyelwa) futhi ividiyo edlulisiwe ayibethelwanga nge-HDCP (okungukuthi ukubethela isimo hdcp1_enabled noma i-hdcp2_enabled ku-TX IP akuqinisekiswanga).
  — Uma ividiyo etholiwe iyi-HDCP TYPE 1 (okungukuthi streamid_type evela ku-RX IP kuyagonyelwa) futhi ividiyo edlulisiwe ibethelwe nge-HDCP 1.4 (okungukuthi ukubethela isimo se-hdcp1_enabled kusuka ku-TX IP kuyagonyelwa)
• Kufanele ugcine ubumfihlo nobuqotho bokhiye bakho bokukhiqiza be-HDCP, kanye nanoma ibaphi okhiye bokubethela komsebenzisi.
• I-Intel incoma kakhulu ukuthi uthuthukise noma imaphi amaphrojekthi we-Intel Quartus Prime nomthombo wokuklama files aqukethe okhiye bokubethela endaweni ephephile yokubala ukuvikela okhiye.
• I-Intel incoma kakhulu ukuthi usebenzise izici zokuphepha zedizayini kuma-FPGA ukuze uvikele idizayini, okuhlanganisa noma yibaphi okhiye bokubethela abashunyekiwe, ekukopishelweni okungagunyaziwe, ubunjiniyela bokuhlehla, kanye t.ampukwenza iphutha.

Ulwazi Oluhlobene
I-AN 556: Ukusebenzisa Izici Zokuvikela Zokuklama kuma-Intel FPGAs

4.6. Izinkombandlela zokususa iphutha
Lesi sigaba sichaza isignali yesimo se-HDCP ewusizo namapharamitha esofthiwe angasetshenziselwa ukulungisa iphutha. Futhi iqukethe imibuzo evame ukubuzwa (FAQ) mayelana nokusebenzisa i-ex yedizayiniample.

4.6.1. Izimpawu zesimo se-HDCP
Kunezimpawu ezimbalwa eziwusizo ukuhlonza isimo sokusebenza se-HDCP IP cores. Lezi zimpawu ziyatholakala ku-ex designampizinga eliphezulu futhi liboshwe kuma-LED angaphakathi:

Igama Lesignali	Umsebenzi
hdcp1_enabled_rx	I-RX HDCP1x Isimo Sokuqanjwa Kwe-IP 0: Ayisebenzi 1: Kuyasebenza
hdcp2_enabled_rx	I-RX HDCP2x Isimo Sokuqanjwa Kwe-IP 0: Ayisebenzi 1: Kuyasebenza
hdcp1_enabled_tx	TX HDCP1x IP Ukubethela Isimo 0: Ayisebenzi 1: Kuyasebenza
hdcp2_enabled_tx	TX HDCP2x IP Ukubethela Isimo 0: Ayisebenzi 1: Kuyasebenza

Bheka kuThebula 57 ekhasini 115 kanye neThebula 58 ekhasini 115 ngokubekwa kwazo kwe-LED.
Isimo sokusebenza salezi zimpawu sibonisa ukuthi i-HDCP IP igunyaziwe futhi yamukela/ithumela ukusakaza kwevidiyo ebethelwe. Ngokuqondisa ngakunye, i-HDCP1x noma i-HDCP2x kuphela
amasiginali wesimo sokubethela/ukususa ukubethela ayasebenza. Okwesiboneloample, uma ngabe i-hdcp1_enabled_rx noma i-hdcp2_enabled_rx isebenza, i-HDCP ohlangothini lwe-RX inikwe amandla futhi isusa ukubethela ukusakaza kwevidiyo ebethelwe emthonjeni wevidiyo ongaphandle.

4.6.2. Ukulungisa i-HDCP Software Parameters
Ukuze wenze kube lula inqubo yokulungisa iphutha le-HDCP, ungakwazi ukulungisa amapharamitha kokuthi hdcp.c.
Ithebula elingezansi lifingqa uhlu lwamapharamitha alungisekayo kanye nemisebenzi yawo.

Ipharamitha	Umsebenzi
SUPPORT_HDCP1X	Nika amandla i-HDCP 1.4 ohlangothini lwe-TX
SUPPORT_HDCP2X	Nika amandla i-HDCP 2.3 ohlangothini lwe-TX
DEBUG_MODE_HDCP	Nika amandla imilayezo yokususa iphutha ku-TX HDCP
REPEATER_MODE	Nika amandla imodi yokuphinda ye-HDCP design example

Ukuze ulungise amapharamitha, shintsha amanani abe amanani ofisayo kokuthi hdcp.c. Ngaphambi kokuqala ukuhlanganisa, yenza ushintsho olulandelayo ku-built_sw_hdcp.sh:

1. Thola umugqa olandelayo bese uwuphawula ukuze uvimbele isofthiwe eguquliwe file ithathelwa indawo ngeyokuqala files kusuka endleleni yokufaka ye-Intel Quartus Prime Software.
   
2.  Qalisa okuthi “./build_sw_hdcp.sh” ukuze uhlanganise isofthiwe ebuyekeziwe.
3. I-.elf ekhiqiziwe file ingafakwa ekwakhiweni ngezindlela ezimbili:
   a. Qalisa “nios2-landa -g file igama>". Setha kabusha isistimu ngemva kokuqedwa kwenqubo yokulanda ukuze uqinisekise ukusebenza okufanele.
   b. Qalisa okuthi “quartus_cdb –-update_mif” ukuze ubuyekeze ukuqaliswa kwenkumbulo files. Qalisa i-assembler ukuze ukhiqize i-.sof entsha file okuhlanganisa isofthiwe ebuyekeziwe.

4.6.3. Imibuzo Evame Ukubuzwa (FAQ)
Ithebula 59. Izimpawu Zokwehluleka Neziqondiso

Inombolo	Ukwehluleka Uphawu	Isiqondiso
1.	I-RX ithola ividiyo ebethelwe, kodwa i-TX ithumela ividiyo emile enombala oluhlaza okwesibhakabhaka noma omnyama.	Lokhu kungenxa yokungaphumeleli kokuqinisekisa kwe-TX ngosinki wangaphandle. Isiphindaphinda esinekhono le-HDCP akumele sidlulise ividiyo ngefomethi engabetheliwe uma ividiyo engenayo evela phezulu ibethelwe. Ukuze kuzuzwe lokhu, ividiyo emile enombala oluhlaza okwesibhakabhaka noma omnyama ingena esikhundleni sevidiyo ephumayo lapho isignali yesimo sokubethela ye-TX HDCP ingasebenzi kuyilapho isignali yesimo sokususwa kwekhodi ye-RX HDCP isebenza. Ukuze uthole imihlahlandlela eqondile, bheka ku Ukucatshangelwa Kokuphepha ekhasini 117. Nokho, lokhu kuziphatha kungase kuvimbe inqubo yokulungisa iphutha lapho kunika amandla idizayini ye-HDCP. Ngezansi indlela yokukhubaza ukuvinjwa kwevidiyo ku-ex yokuklamaample: 1. Thola uxhumano lwembobo olulandelayo ezingeni eliphezulu le-ex yedizayiniample. Le mbobo ingeyemojuli ye-hdmi_tx_top. 2. Lungisa uxhumano lwembobo kulayini olandelayo:
2.	Isignali yesimo sokubethela ye-TX HDCP iyasebenza kodwa isithombe seqhwa siboniswa kusinki ongezansi.	Lokhu kungenxa yokuthi usinki ongezansi awukukhiphi ukubethela ividiyo ephumayo ebethelwe ngendlela efanele. Qiniseka ukuthi unikeza i-global constant (LC128) ku-TX HDCP IP. Inani kufanele libe inani lokukhiqiza futhi lilungile.
3.	Isignali yesimo sokubethela ye-TX HDCP ayizinzile noma ihlezi ingasebenzi.	Lokhu kungenxa yokungaphumeleli kokuqinisekisa kwe-TX ngosinki ongezansi. Ukwenza kube lula inqubo yokulungisa iphutha, ungavumela ifayela le- DEBUG_MODE_HDCP ipharamitha ku-hdcp.c. Bukela ku Ukulungisa Imingcele Yesofthiwe ye-HDCP ekhasini 118 leziqondiso. I-3a-3c elandelayo ingaba yimbangela engenzeka yokuqinisekisa kwe-TX okungaphumeleli.
3a.	Ilogi yokususa iphutha lesofthiwe iqhubeka nokuphrinta lo mlayezo “i-HDCP 1.4 ayisekelwe wumfula ongezansi (Rx)”.	Umlayezo ubonisa ukuthi usinki ongezansi awukusekeli kokubili i-HDCP 2.3 ne-HDCP 1.4. Qiniseka ukuthi usinki ongezansi usekela i-HDCP 2.3 noma i-HDCP 1.4.
3b.	Ukuqinisekisa kwe-TX kwehluleka phakathi.	Lokhu kungenxa yanoma iyiphi ingxenye yokuqinisekisa kwe-TX njengokuqinisekiswa kwesiginesha, ukuhlola indawo njll kungahluleka. Qiniseka ukuthi usinki waphansi womfula usebenzisa ukhiye wokukhiqiza kodwa hhayi ukhiye wefeksi.
3c.	Ilogi yokususa iphutha lesoftware iqhubeka nokuphrinta “Ukuqinisekisa kabusha	Lo mlayezo ukhombisa ukuthi usinki ongezansi ucele ukugunyazwa kabusha ngoba ividiyo eyamukelwe ayizange isuswe ukubethela ngendlela efanele. Qiniseka ukuthi unikeza i-global constant (LC128) ku-TX HDCP IP. Inani kufanele libe inani lokukhiqiza futhi inani lilungile.
waqhubeka...

Inombolo	Ukwehluleka Uphawu	Isiqondiso
	iyadingeka” ngemva kokuqedwa kokuqinisekisa kwe-HDCP.
4.	Isignali yesimo sokususwa kwekhodi ye-RX HDCP ayisebenzi nakuba umthombo okhuphuka nomfula unike amandla i-HDCP.	Lokhu kubonisa ukuthi i-RX HDCP IP ayikasifinyeleli isimo esiqinisekisiwe. Ngokuzenzakalelayo, i REPEATER_MODE ipharamitha inikwe amandla ku-ex designample. Uma i REPEATER_MODE ivuliwe, qiniseka ukuthi i-TX HDCP IP igunyaziwe. Lapho i- REPEATER_MODE ipharamitha inikwe amandla, i-RX HDCP IP izama ukufakazela ubuqiniso njengesiphindaphinda uma i-TX ixhunywe kusinki okwazi i-HDCP. Ukuqinisekisa kuma phakathi ngenkathi kulinde i-TX HDCP IP ukuthi iqedele ukufakazela ubuqiniso ngosinki ongezansi bese idlulisela i-RECEIVERID_LIST ku-RX HDCP IP. Isikhathi sokuvala njengoba kuchazwe ku-HDCP Specification imizuzwana emi-2. Uma i-TX HDCP IP ingakwazi ukuqedela ukufakazela ubuqiniso kulesi sikhathi, umthombo okhuphukayo uphatha ukuqinisekiswa njengokwehluleka futhi uqala ukufakazela ubuqiniso njengoba kucaciswe Ekucacisweni kwe-HDCP.
		Qaphela: • Bukela ku Ukulungisa Imingcele Yesofthiwe ye-HDCP ekhasini 118 lendlela yokukhubaza i REPEATER_MODE ipharamitha yenhloso yokulungisa iphutha. Ngemva kokukhubaza i- REPEATER_MODE ipharamitha, i-RX HDCP IP ihlale izama ukuqinisekiswa njengesamukeli sephoyinti lokugcina. I-TX HDCP IP ayifuni inqubo yokuqinisekisa.
		• Uma i REPEATER_MODE ipharamitha ayinikiwe amandla, qiniseka ukuthi ukhiye we-HDCP onikezwe i-HDCP IP uyinani lokukhiqiza futhi inani lilungile.
5.	Isignali yesimo sokususwa kwekhodi ye-RX HDCP ayizinzile.	Lokhu kusho ukuthi i-RX HDCP IP icele ukugunyazwa kabusha ngemva nje kokuba isimo esiqinisekisiwe sesifinyelelwe. Lokhu kungenxa yokuthi ividiyo engenayo ebethelwe ayisuswanga ukubethela ngendlela efanele yi-RX HDCP IP. Qiniseka ukuthi i-global constant (LC128) ehlinzekwa ku-RX HDCP IP core iyivelu yokukhiqiza futhi inani lilungile.

I-HDMI Intel Arria 10 FPGA IP Design Example Izingobo zomlando zomhlahlandlela womsebenzisi

Ukuze uthole izinguqulo zakamuva nezidlule zalo mhlahlandlela womsebenzisi, bheka ku-HDMI Intel® Arria 10 FPGA IP Design Ex.ample Umhlahlandlela Womsebenzisi. Uma i-IP noma inguqulo yesofthiwe ingekho ohlwini, inkomba yomsebenzisi ye-IP yangaphambilini noma inguqulo yesofthiwe iyasebenza.
Izinguqulo ze-IP ziyefana nezinguqulo zesofthiwe ye-Intel Quartus Prime Design Suite kufika ku-v19.1. Kusuka ku-Intel Quartus Prime Design Suite software version 19.2 noma kamuva, IP
ama-cores anohlelo olusha lwenguqulo ye-IP.

Umlando Wokubuyekeza we-HDMI Intel Arria 10 FPGA IP Design Example Umhlahlandlela Womsebenzisi

Inguqulo Yedokhumenti	Inguqulo ye-Intel Quartus Prime	Inguqulo ye-IP	Izinguquko
2022.12.27	22.4	19.7.1	Kwengezwe ipharamitha entsha yokukhetha ukubuyekezwa kwekhadi lendodakazi ye-HDMI engxenyeni ye-Hardware ne-Software Requirements ye-design ex.ample ye-HDMI 2.0 (imodi engeyona ye-FRL).
2022.07.29	22.2	19.7.0	• Isaziso sokukhishwa kwengxenye ye-Cygwin enguqulweni ye-Windows* ye-Nios II EDS kanye nemfuneko yokufaka i-WSL yabasebenzisi be-Windows*. • Kubuyekezwe inguqulo yekhadi lendodakazi kusukela ekubuyekezweni 4 kuya ku-9 lapho kusebenza khona kuwo wonke umbhalo.
2021.11.12	21.3	19.6.1	• Kubuyekezwe okhiye bokukhiqiza be-HDCP ababethelwe kwesigatshana seSitolo kumemori yefuleshi yangaphandle noma i-EEPROM (Ukusekela Ukuphathwa Kokhiye we-HDCP = 1) ukuze kuchazwe insiza entsha yesofthiwe yokubethela yokhiye (KEYENC). • Ususe izibalo ezilandelayo: — Uhlu lwedatha yeFacsimile Key R1 ye-RX Private Key - Uhlu lwedatha Yezikhiye Zokukhiqiza ze-HDCP (Isimeli) - Uhlu lwedatha ye-HDCP Protection Key (ukhiye ochazwe ngaphambilini) — Ukhiye wokuvikela we-HDCP uqaliswe ku-hdcp2x_tx_kmem.mif - Ukhiye wokuvikela we-HDCP uqaliswe ku-hdcp1x_rx_kmem.mif — Ukhiye wokuvikela we-HDCP uqaliswe ku-hdcp1x_tx_kmem.mif • Kuhanjiswe isigatshana sokumepha ukhiye we-HDCP ukusuka kukhiye we-DCP Files ukusuka Kumihlahlandlela Yokususa iphutha kuya Kugcina okhiye bokukhiqiza be-HDCP abangenalutho ku-FPGA (Ukusekela Ukuphathwa Kokhiye we-HDCP = 0).
2021.09.15	21.1	19.6.0	Ireferensi esusiwe ku-ncsim
2021.05.12	21.1	19.6.0	• Kwengezwe Lapho ISEKELA FRL = 1 noma SEKELA UKUPHATHWA KUKAkhiye we-HDCP = 1 encazelweni yomfanekiso 29 HDCP Over HDMI Design Example Block Diagram. • Kwengezwe izinyathelo kumemori yokhiye we-HDCP files ku-Design Walkthrough. • Kwengezwe Uma USEKELA FRL = 0 esigabeni Setha i-ardware. • Kwengezwe isinyathelo ukuze uvule ipharamitha Yokulawula Ukhiye Yokusekela i-HDCP kokuthi Khiqiza Idizayini. • Kwengezwe okhiye bokukhiqiza be-HDCP ababethelwe besiqephu esisha seSitolo kumemori yefuleshi yangaphandle noma i-EEPROM (Ukusekela Ukuphathwa Kokhiye we-HDCP = 1).
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Inguqulo Yedokhumenti	Inguqulo ye-Intel Quartus Prime	Inguqulo ye-IP	Izinguquko
			• Inkinobho Yokusunduza Yethebula Eqanjwe Kabusha kanye Nezinkomba ze-LED Zokusunduza Inkinobho kanye Nezinkomba ze-LED (SUPPORT FRL = 0). • Kwengezwe Inkinobho Yokusunduza Yethebula kanye Nezinkomba ze-LED (SUPPORT FRL = 1). • Kwengezwe isahluko esisha Ukuvikelwa Kokhiye Wokubethela Oshumekwe Kumklamo we-FPGA. • Kwengezwe isahluko esisha Izinkombandlela zokususa iphutha nezigatshana ze-HDCP Status Signals, Ukulungisa Ipharamitha Yesofthiwe ye-HDCP kanye Nemibuzo Evame Ukubuzwa.
2021.04.01	21.1	19.6.0	• Izingxenye Zezibalo Ezibuyekeziwe Ezidingekayo Kumklamo we-RX-Only noma we-TX-Only. • Ithebula Elibuyekeziwe Elikhiqizwe i-RTL Files. • Izingxenye eziphezulu ze-HDMI RX ezibuyekeziwe. • Isigaba Esikhishiwe Inqubo Yokuqeqesha Isixhumanisi Esiphezulu se-HDMI RX. • Kubuyekezwe izinyathelo Zokuqalisa Idizayini Ngamazinga Ahlukene e-FRL. • Umfanekiso Obuyekeziwe we-HDMI 2.1 Example Clock Scheme. • Izimpawu Zohlelo Lokuvala Ithebula Olubuyekeziwe. • Umfanekiso Obuyekeziwe we-HDMI RX-TX Block Diagram ukuze wengeze uxhumano kusuka ku-Transceiver Arbiter kuya ku-TX top.
2020.09.28	20.3	19.5.0	• Kukhishwe inothi ethi i-HDMI 2.1 design exampI-le kumodi ye-FRL isekela kuphela amadivayisi webanga lesivinini -1 ku-HDMI Intel FPGA IP Design Example Umhlahlandlela Wokuqala Osheshayo wamadivayisi we-Intel Arria 10 kanye ne-HDMI 2.1 Design Example (Support FRL = 1) izigaba. Idizayini isekela wonke amamaki esivinini. • Kukhishwe ulwazi lwe-ls_clk kuwo wonke ama-design we-HDMI 2.1 example izigaba ezihlobene. Isizinda se-ls_clk asisasetshenziswa ku-design example. • Kubuyekezwe imidwebo yebhulokhi ye-HDMI 2.1 design example kumodi ye-FRL ku-HDMI 2.1 Design Example (Ukusekela i-FRL = 1), Ukudala i-RX- Kuphela noma i-TX-Only Designs Design Components, kanye nezigaba ze-Clocking Scheme. • Kubuyekezwe izinkomba futhi kwakhiwe files uhlu ezigabeni zeSakhiwo Semibhalo. • Kukhishwe amasignali angafanele, futhi yengeza noma yahlela incazelo ye-HDMI 2.1 design ex elandelayoampamasignali esigabeni Sezimpawu Zokuxhumana: - sys_init — txpll_frl_locked — tx_os - amasiginali we-txphy_rcfg* — tx_reconfig_done - txcore_tbcr — pio_in0_external_connection_export • Kwengezwe amapharamitha alandelayo esigabeni se-Design RTL Parameters: — EDID_RAM_ADDR_WIDTH — BITEC_DAUGHTER_CARD_REV - SEBENZISA i-FPLL — POLARITY_INVERSION
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Inguqulo Yedokhumenti	Inguqulo ye-Intel Quartus Prime	Inguqulo ye-IP	Izinguquko
			• Kubuyekezwe imidwebo yebhulokhi ye-HDMI 2.0 design example yesoftware ye-Intel Quartus Prime Pro Edition ku-HDMI 2.0 Design Example (Ukusekela i-FRL = 0), Ukudala i-RX-Only noma i-TX-Only Designs Izingxenye Zedizayini, kanye nezigaba ze-Clocking Scheme. • Kubuyekezwe iwashi futhi kusethe kabusha amagama esignali esigabeni se-Dynamic Range ne-Mastering (HDR) InfoFrame Insert and Filtering. • Kukhishwe amasignali angafanele, futhi yengeza noma yahlela incazelo ye-HDMI 2.0 design ex elandelayoampamasignali esigabeni Sezimpawu Zokuxhumana: - clk_fpga_b3_p - REFCLK_FMCB_P — fmcb_la_tx_p_11 - fmcb_la_rx_n_9e - fr_click — setha kabusha_xcvr_powerup - amasiginali we-nios_tx_i2c* - amasiginali we-hdmi_ti_i2c* — tx_i2c_avalon* amasiginali — clock_bridge_0_in_clk_clk — reset_bridge_0_reset_reset_n — i2c_master* amasignali - amasiginali we-nios_tx_i2c* — measure_valid_pio_external_connectio n_export — oc_i2c_av_slave_translator_avalon_an ti_slave_0* amasiginali — thumela_i-cal_done_export — rx_pma_cal_busy_export — rx_pma_ch_export — rx_pma_rcfg_mgmt* amasiginali • Kwengezwe inothi lokuthi ibhentshi lokulingisa le-testbench alisekelwe kumiklamo ene- Faka i-I2C ipharamitha inikwe amandla futhi yabuyekeza umlayezo wokulingisa esigabeni seSimulation Testbench. • Kubuyekezwe ingxenye ethi Thuthukisa Idizayini Yakho.
2020.04.13	20.1	19.4.0	• Kwengezwe inothi yokuthi i-HDMI 2.1 design exampI-le kumodi ye-FRL isekela kuphela amadivayisi webanga lesivinini -1 ku-HDMI Intel FPGA IP Design Example Umhlahlandlela Wokuqala Okusheshayo Wamadivayisi we-Intel Arria 10 Nencazelo Eningiliziwe ye-HDMI 2.1 Design Example (Support FRL = 1) izigaba. • Kuhanjiswe I-HDCP Nge-HDMI Isibample lesigaba se-Intel Arria 10 Devices esivela ku-HDMI Intel FPGA IP User Guide. • Kuhlelwe isigaba Sokulingisa Idizayini ukuze sifake ama-audio sampI-le generator, i-sideband data generator, kanye ne-auxiliary data generator futhi yabuyekeza umlayezo wokulingisa oyimpumelelo. • Kukhishwe inothi ukuthi ukulingiswa okushiwo kutholakalela kuphela Sekela i-FRL inothi lemiklamo ekhubazekile. Ukulingisa manje sekuyatholakala Sekela i-FRL imiklamo enikwe amandla futhi. • Kubuyekezwe incazelo yesici Encazelweni Enemininingwane ye-HDMI 2.1 Design Example (Ukusekela i-FRL Kunikwe amandla) isigaba.
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Inguqulo Yedokhumenti	Inguqulo ye-Intel Quartus Prime	Inguqulo ye-IP	Izinguquko
			• Uhlele umdwebo webhulokhi ku-HDMI 2.1 RX-TX Design Block Diagram, Design Components, kanye Nokudala i-RX-Only noma i-TX-Only Designs izigaba ze-HDMI 2.1 design example. Kwengezwe izingxenye ezintsha kanye nezingxenye ezikhishiwe ezingasasebenzi. • Kuhlelwe umyalo weskripthi esikhulu.c esigabeni sokudala i-RX-Only noma i-TX-Only Designs. • Kubuyekezwe izigaba zeSakhiwo Semibhalo ukuze kwengezwe amafolda amasha kanye files kukho kokubili i-HDMI 2.0 ne-HDMI 2.1 umklamo exampLes. • Kubuyekezwe isigaba se-Hardware kanye Nezimfuneko Zesofthiwe ye-HDMI 2.1 design example. • Kubuyekezwe idayagramu yebhulokhi kanye nezincazelo zesignali ku-Dynamic Range ne-Mastering (i-HDR) isigaba Sokufaka kanye Nokuhlunga kwe-InfoFrame ye-HDMI 2.1 ex design.ample. • Kwengezwe isigaba esisha, Ukusebenzisa Idizayini Ngamazinga Ahlukene e-FRL, ku-HDMI 2.1 design exampLes. • Kubuyekezwe idayagramu yebhulokhi kanye nezincazelo zesignali esigabeni se-Clocking Scheme ye-HDMI 2.1 design example. • Incazelo eyengeziwe mayelana neswishi ye-DIP yomsebenzisi esigabeni sokusethwa kwezingxenyekazi zekhompyutha ye-HDMI 2.1 example. • Kubuyekezwe isigaba Semikhawulo Yedizayini ye-HDMI 2.1 design example. • Kubuyekezwe ingxenye ethi Thuthukisa Idizayini Yakho. • Kubuyekezwe izigaba zeSimulation Testbench zazo zombili i-HDMI 2.0 kanye ne-HDMI 2.1 ex yedizayiniampLes.
2020.01.16	19.4	19.3.0	• Kubuyekezwe i-HDMI Intel FPGA IP Design Example Umhlahlandlela Wokuqala Okusheshayo wesigaba samadivayisi we-Intel Arria 10 ngolwazi mayelana ne-HDMI 2.1 ex design example ngemodi ye-FRL. • Kwengezwe isahluko esisha, Incazelo Eningiliziwe ye-HDMI 2.1 Design Example (Ukusekela i-FRL Kunikwe amandla) equkethe lonke ulwazi olufanele mayelana nomklamo osanda kufakwa example. • Iqanjwe kabusha i-HDMI Intel FPGA IP Design Example Incazelo Eningiliziwe Encazelweni Enemininingwane ye-HDMI 2.0 Design Example ukuze kube nokucaca okungcono.
2019.10.31	18.1	18.1	• Kwengezwe kukhiqiziwe files kufolda ethi tx_control_src: ti_i2c.c kanye no-ti_i2c.h. • Ukwesekwa okwengeziwe kokubuyekezwa kwekhadi lendodakazi le-FMC 11 ku-Hardware Nezimfuneko Zesofthiwe kanye Nokuhlanganiswa Nokuhlola Izigaba Zokuklama. • Kukhishwe isigaba Somkhawulo Wokuklama. Umkhawulo ophathelene nokwephulwa kwesikhathi kumkhawulo omkhulu we-skew uxazululwe enguqulweni 18.1 ye-HDMI Intel FPGA IP. • Kwengezwe ipharamitha entsha ye-RTL, BITEC_DAUGHTER_CARD_REV, ukuze ukwazi ukukhetha ukubuyekezwa kwekhadi lendodakazi le-Bitec HDMI.
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Inguqulo Yedokhumenti	Inguqulo ye-Intel Quartus Prime	Inguqulo ye-IP	Izinguquko
			• Kubuyekezwe incazelo yezimpawu ze-fmcb_dp_m2c_p kanye ne-fmcb_dp_c2m_p ukuze kufakwe ulwazi mayelana nezibuyekezo zekhadi lendodakazi le-FMC 11, 6, kanye no-4. • Kwengezwe amasiginali amasha alandelayo okubuyekezwa kwekhadi lendodakazi le-Bitec 11: — hdmi_tx_ti_i2c_sda — hdmi_tx_ti_i2c_scl — oc_i2c_master_ti_avalon_anti_slave_a ikheli — oc_i2c_master_ti_avalon_anti_slave_w rite — oc_i2c_master_ti_avalon_anti_slave_r eaddata — oc_i2c_master_ti_avalon_anti_slave_w ritedata — oc_i2c_master_ti_avalon_anti_slave_w aitrequest • Kwengezwe isigaba mayelana Nokuthuthukisa Idizayini Yakho.
2017.11.06	17.1	17.1	• Iqanjwe kabusha i-HDMI IP core yaba yi-HDMI Intel FPGA IP njengokusho kwe-Intel kabusha. • Kushintshwe igama elithi Qsys laba Umklami Wenkundla. • Ulwazi olungeziwe mayelana ne-Dynamic Range kanye ne-Mastering InfoFrame (i-HDR) nezici zokuhlunga. • Kubuyekezwe ukwakheka kohla lwemibhalo: - Kwengezwe amafolda eskripthi nesoftware kanye files. - Kubuyekezwe okuvamile kanye ne-hdr files. - Kukhishwe i-atx files. - Ihlukaniswe files ye-Intel Quartus Prime Standard Edition ne-Intel Quartus Prime Pro Edition. • Kubuyekezwe ingxenye ethi Ukukhiqiza Ukuklama ukuze kwengeze idivayisi esetshenziswa njenge-10AX115S2F4I1SG. • Kuhlelwe izinga ledatha ye-transceiver engu-50-100 MHz TMDS iwashi ukuya ku-2550-5000 Mbps. • Kubuyekezwe imininingwane yesixhumanisi se-RX-TX ongayikhulula inkinobho yomsebenzisi_pb[2] ukuze ukhubaze ukuhlunga kwangaphandle. • Kubuyekezwe umdwebo wokugeleza kwesofthiwe ye-Nios II obandakanya izilawuli ze-I2C master kanye nomthombo we-HDMI. • Ulwazi olungeziwe mayelana ne I-Design Example Imingcele ye-GUI. • Kwengezwe imingcele ye-HDMI RX kanye ne-TX Top. • Kwengezwe lawa masignali e-HDMI RX kanye ne-TX aphezulu: - mgmt_clk - setha kabusha — i2c_clk — hdmi_clk_in - Kukhishwe lezi zimpawu ze-HDMI RX kanye ne-TX eziphezulu: • inguqulo • i2c_clk
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Inguqulo Yedokhumenti	Inguqulo ye-Intel Quartus Prime	Inguqulo ye-IP	Izinguquko
			• Kwengezwe inothi lokuthi isilungiselelo se-analog ye-transceiver sihlolelwa i-Intel Arria 10 FPGA Development Kit kanye nekhadi lendodakazi le-Bitec HDMI 2.0. Ungashintsha ukulungiselelwa kwe-analog ebhodini lakho. • Kwengezwe isixhumanisi sokusebenza ukuze kugwenywe i-jitter ye-PLL cascading noma imizila yewashi engazinikele yewashi lesithenjwa le-Intel Arria 10 PLL. • Kwengezwe inothi ukuthi awukwazi ukusebenzisa i-transceiver RX pin njenge-CDR refclk ye-HDMI RX noma njenge-TX PLL refclk ye-HDMI TX. • Kwengezwe inothi elimayelana nendlela yokwengeza umkhawulo we-set_max_skew kumadizayini asebenzisa i-TX PMA ne-PCS bonding.
2017.05.08	17.0	17.0	• Iqanjwe kabusha njenge-Intel. • Inombolo yengxenye eshintshiwe. • Kubuyekezwe ukwakheka kohla lwemibhalo: - Kwengezwe i-hdr files. - Kushintshwe qsys_vip_passthrough.qsys ukuze nios.qsys. — Kwengezwe fileyakhelwe i-Intel Quartus Prime Pro Edition. • Ulwazi olubuyekeziwe lokuthi ibhulokhi ye-RX-TX Link iphinde yenze ukuhlunga kwangaphandle ku-High Dynamic Range (HDR) Infoframe evela kudatha ye-HDMI RX eyisiza futhi ifaka i-ex.ample-HDR Infoframe kudatha eyisiza ye-HDMI TX nge-Avalon ST multiplexer. • Kwengezwe inothi lencazelo ye-Transceiver Native PHY yokuthi ukuze uhlangabezane nemfuneko ye-HDMI TX inter-channel skew, udinga ukusetha inketho yemodi yebhondi yesiteshi se-TX kusihleli sepharamitha ye-Arria 10 Transceiver Native PHY ukuze Ukuhlanganiswa kwe-PMA ne-PCS. • Incazelo ebuyekeziwe ye-os namasignali wokulinganisa. • Kulungiswe ama-oversampisici se-ling sesilinganiso sedatha ye-transceiver ehlukile ebangeni ngalinye lefrikhwensi yewashi le-TMDS ukuze kusekelwe isikimu sewashi eliqondile le-TX FPLL. • Kushintshwe i-TX IOPLL yaba isikimu sewashi se-TX FPLL yaba isikimu esiqondile se-TX FPLL. • Kwengezwe amasiginali wokumisa kabusha we-TX PMA. • Kuhlelwe ama-over angu-USER_LED[7]ampisimo se-ling. U-1 ukhombisa ama-overampled (isilinganiso sedatha <1,000 Mbps kudivayisi ye-Arria 10). • Idizayini ye-HDMI ebuyekeziwe Example Ithebula le-Simulator Asekelwe. I-VHDL ayisekelwe ku-NCSim. • Kwengezwe isixhumanisi enguqulweni efakwe kungobo yomlando ye-Arria 10 HDMI IP Core Design Example Umhlahlandlela Womsebenzisi.
2016.10.31	16.1	16.1	Ukukhishwa kokuqala.

Inkampani ye-Intel Wonke Amalungelo Agodliwe. I-Intel, ilogo ye-Intel, nezinye izimpawu ze-Intel yizimpawu zokuthengisa ze-Intel Corporation noma izinkampani ezingaphansi kwayo. I-Intel iqinisekisa ukusebenza kwe-FPGA yayo kanye nemikhiqizo yesemiconductor ekucacisweni kwamanje ngokuvumelana newaranti evamile ye-Intel, kodwa igodla ilungelo lokwenza izinguquko kunoma imiphi imikhiqizo namasevisi nganoma yisiphi isikhathi ngaphandle kwesaziso. I-Intel ayithathi mthwalo noma isikweletu esivele ngenxa yesicelo noma ukusetshenziswa kwanoma yiluphi ulwazi, umkhiqizo, noma isevisi echazwe lapha ngaphandle kwalapho okuvunyelwene ngakho ngokubhaliwe yi-Intel. Amakhasimende e-Intel ayelulekwa ukuthi athole inguqulo yakamuva yokucaciswa kwedivayisi ngaphambi kokuthembela kunoma yiluphi ulwazi olushicilelwe nangaphambi kokufaka ama-oda emikhiqizo noma amasevisi. *Amanye amagama namabhrendi angafunwa njengempahla yabanye.

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Inguqulo: 2022.12.27

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Intel HDMI Arria 10 FPGA IP Design Example [pdf] Umhlahlandlela Womsebenzisi I-HDMI Arria 10 FPGA IP Design Example, HDMI Arria, 10 FPGA IP Design Example, Design Example

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