I-GPIO Intel® FPGA IP Umhlahlandlela Womsebenzisi

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I-Intel® Arria® 10 kanye ne-Intel® Cyclone® 10 GX Amadivayisi

Ibuyekezelwe i-Intel® Quartus® Prime Design Suite: 21.2
Inguqulo ye-IP: 20.0.0

I-Online Version                                                               I-ID: 683136
Thumela Impendulo             ug-altera_gpio            Inguqulo: 2021.07.15

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I-GPIO Intel® FPGA IP core isekela inhloso evamile izici ze-I/O (GPIO) nezingxenye. Ungasebenzisa ama-GPIO ezinhlelweni ezijwayelekile ezingaqondile kuma-transceivers, i-memory interface, noma i-LVDS.

I-GPIO IP core itholakala kumadivayisi we-Intel Arria® 10 kanye ne-Intel Cyclone® 10 GX kuphela. Uma uthutha imiklamo kusukela kumadivayisi we-Stratix® V, Arria V, noma i-Cyclone V, kufanele uthuthe ama-IP cores ALTDDIO_IN, ALTDDIO_OUT, ALTDDIO_BIDIR, noma ALTIOBUF.

Ulwazi Oluhlobene

• I-IP Migration Flow ye-Arria V, Cyclone V, kanye ne-Stratix V Amadivayisi ekhasini 22
• Intel Stratix 10 I/O Imihlahlandlela Yokuqalisa
  Ihlinzeka ngomhlahlandlela womsebenzisi oyinhloko we-GPIOIP wamadivayisi we-Intel Stratix 10.
• Isingeniso se-Intel FPGA IP Cores
  Ihlinzeka ngolwazi olujwayelekile mayelana nawo wonke ama-Intel FPGA IP cores, okuhlanganisa ukwenza ipharamitha, ukukhiqiza, ukuthuthukisa, kanye nokulingisa ama-IP cores.
• Ukudala Inguqulo Ezimele Ye-IP kanye Nezikripthi Zokulingisa ze-Qsys
  Dala imibhalo yokulingisa engadingi ukubuyekezwa mathupha kwesofthiwe noma ukuthuthukiswa kwenguqulo ye-IP.
• Izindlela Ezinhle Zokuphatha Iphrojekthi
  Imihlahlandlela yokuphatha kahle nokuphatheka kwephrojekthi yakho ne-IP files.
• I-GPIO Intel FPGA IP Umhlahlandlela Womsebenzisi Izingobo zomlando ekhasini 24
  Ihlinzeka ngohlu lwemihlahlandlela yomsebenzisi yezinguqulo zangaphambilini ze-GPIO IP core.
• I-Double Data Rate I/O (ALTDDIO_IN, ALTDDIO_OUT, kanye ne-ALTDDIO_BIDIR) IP Cores User Guide
• I/O Buffer (ALTIOBUF) IP Core User Guide

Ulwazi Lokukhishwa lwe-GPIO Intel FPGA IP

Izinguqulo ze-Intel FPGA IP zifana nezinguqulo zesofthiwe ye-Intel Quartus® Prime Design Suite kuze kube yi-v19.1. Iqala ku-Intel Quartus Prime Design Suite software version 19.2, i-Intel FPGA IP inohlelo olusha lwenguqulo.

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Inkampani ye-Intel Wonke Amalungelo Agodliwe. I-Intel, ilogo ye-Intel, nezinye izimpawu ze-Intel yizimpawu zokuthengisa ze-Intel Corporation noma izinkampani ezingaphansi kwayo. I-Intel iqinisekisa ukusebenza kwe-FPGA yayo kanye nemikhiqizo yesemiconductor ekucacisweni kwamanje ngokuvumelana newaranti evamile ye-Intel, kodwa igodla ilungelo lokwenza izinguquko kunoma imiphi imikhiqizo namasevisi nganoma yisiphi isikhathi ngaphandle kwesaziso. I-Intel ayithathi mthwalo noma isikweletu esivele ngenxa yesicelo noma ukusetshenziswa kwanoma yiluphi ulwazi, umkhiqizo, noma isevisi echazwe lapha ngaphandle kwalapho okuvunyelwene ngakho ngokubhaliwe yi-Intel. Amakhasimende e-Intel ayelulekwa ukuthi athole inguqulo yakamuva yokucaciswa kwedivayisi ngaphambi kokuthembela kunoma yiluphi ulwazi olushicilelwe nangaphambi kokufaka ama-oda emikhiqizo noma amasevisi. *Amanye amagama namabhrendi angafunwa njengempahla yabanye.

I-ISO 9001:2015 Ibhalisiwe

Inombolo ye-Intel FPGA IP (XYZ) ingashintsha ngenguqulo ngayinye yesofthiwe ye-Intel Quartus Prime. Ushintsho ku:

• U-X ukhombisa ukubuyekezwa okukhulu kwe-IP. Uma ubuyekeza isofthiwe ye-Intel Quartus Prime, kufanele uvuselele i-IP.
• U-Y ukhombisa ukuthi i-IP ihlanganisa izici ezintsha. Khiqiza kabusha i-IP yakho ukuze ufake lezi zici ezintsha.
• U-Z ukhombisa ukuthi i-IP ihlanganisa izinguquko ezincane. Khiqiza kabusha i-IP yakho ukuze ufake lezi zinguquko.

Ithebula 1. I-GPIO Intel FPGA IP Ulwazi Lwamanje Lokukhishwa

Into	Incazelo
Inguqulo ye-IP	20.0.0
Inguqulo ye-Intel Quartus Prime	21.2
Usuku lokukhulula	2021.06.23

Izici ze-GPIO Intel FPGA IP

I-GPIO IP core ihlanganisa izici zokusekela i-I/O block yedivayisi. Ungasebenzisa isihleli sepharamitha ye-Intel Quartus Prime ukuze ulungiselele umongo we-GPIO IP.

I-GPIO IP core inikeza lezi zingxenye:

• Okokufaka/okuphumayo kwedatha okuphindwe kabili (DDIO)—ingxenye yedijithali ephinda kabili noma ehhafu izinga ledatha yesiteshi sokuxhumana.
• Amaketanga okulibaziseka—lungiselela amaketanga okulibaziseka ukuze enze ukubambezeleka okuthile futhi usize ekuvaleni isikhathi se-I/O.
• Amabhafa we-I/O—xhuma amaphedi ku-FPGA.

I-GPIO Intel FPGA IP Data Izindlela

Umfanekiso 1. Izinga eliphezulu View ye-GPIO ene-Single-Ending

Ithebula 2. I-GPIO IP Core Data Path Modes

Umzila Wedatha	Bhalisa Imodi
	Ukudlula	Irejista elula	I-DDR I/O
			Izinga Eligcwele	I-Half-Rate
Okokufaka	Idatha isuka entweni yokubambezeleka iye kweyinhloko, yeqe wonke ama-I/Os (DDIO) wedatha ephindwe kabili.	I-DDIO enesilinganiso esigcwele isebenza njengerejista elula, yeqa ama-DDIO aphakathi nendawo. I-Fitter ikhetha ukupakisha irejista ku-I/O noma isebenzise irejista emnyombweni, kuye ngendawo kanye nesikhathi sokuhwebelana.	I-DDIO enesilinganiso esigcwele isebenza njenge-DDIO evamile, yeqa ama-DDIO esilinganiso esiyingxenye.	I-DDIO enesilinganiso esigcwele isebenza njenge-DDIO evamile. Ama-DDIO esilinganiso esiyingxenye aguqula idatha enesilinganiso esigcwele ibe idatha enesilinganiso esiyingxenye.
Okukhiphayo	Idatha isuka kumongo iqonde kusici sokulibaziseka, yeqe wonke ama-DDIO.	I-DDIO enesilinganiso esigcwele isebenza njengerejista elula, yeqa ama-DDIO aphakathi nendawo. I-Fitter ikhetha ukupakisha irejista ku-I/O noma isebenzise irejista emnyombweni, kuye ngendawo kanye nesikhathi sokuhwebelana.	I-DDIO enesilinganiso esigcwele isebenza njenge-DDIO evamile, yeqa ama-DDIO esilinganiso esiyingxenye.	I-DDIO enesilinganiso esigcwele isebenza njenge-DDIO evamile. Ama-DDIO esilinganiso esiyingxenye aguqula idatha enesilinganiso esigcwele ibe idatha enesilinganiso esiyingxenye.
I-Bidirectional	Ibhafa yokukhiphayo ishayela kokubili iphinikhodi yokukhipha kanye nebhafa yokufaka.	I-DDIO enesilinganiso esigcwele isebenza njengerejista elula. Ibhafa yokukhiphayo ishayela kokubili iphinikhodi yokukhipha kanye nebhafa yokufaka.	I-DDIO enesilinganiso esigcwele isebenza njenge-DDIO evamile. Ibhafa yokukhiphayo ishayela kokubili iphinikhodi yokukhipha kanye nebhafa yokufaka. Ibhafa yokufaka ishayela isethi yama-flip-flop amathathu.	I-DDIO enesilinganiso esigcwele isebenza njenge-DDIO evamile. Ama-DDIO esilinganiso esiyingxenye aguqula idatha enesilinganiso esigcwele ibe isilinganiso esiyingxenye. Ibhafa yokukhiphayo ishayela kokubili iphinikhodi yokukhipha kanye nebhafa yokufaka. Ibhafa yokufaka ishayela isethi yama-flip-flop amathathu.

Uma usebenzisa amasignali acacile futhi asethiwe asynchronous, wonke ama-DDIO abelana ngala masiginali afanayo.

Ama-DDIO alinganisa uhhafu nawesilinganiso esigcwele axhumeka emawashini ahlukene. Uma usebenzisa ama-DDIO esilinganiso esimaphakathi kanye nesilinganiso esigcwele, iwashi lesilinganiso esigcwele kufanele lisebenze ngokuphindwe kabili kunesilinganiso sesilinganiso esinguhhafu. Ungasebenzisa ubudlelwano bezigaba ezahlukene ukuze uhlangabezane nezidingo zesikhathi.

Ulwazi Oluhlobene
Ibhasi Lokufaka Nokuphumayo Ibhithi Eliphezulu Naphansi ekhasini 12

Indlela Yokufaka

Iphedi ithumela idatha ku-bafa yokokufaka, futhi isigcinalwazi sokufakwayo siphakela isici sokulibaziseka. Ngemva kokuthi idatha iye ekuphumeni kwesici sokulibaziseka, i-bypass multiplexers ehlelekayo ikhetha izici nezindlela ezizosetshenziswa.Indlela yokufaka ngayinye iqukethe amasekhondi amabili.tagama-DDIOs, anenani eligcwele nelihhafu.

Umfanekiso 2. Owenziwe Lula View Yendlela Yokufaka Ye-GPIO Enesiphetho Esizodwa

1. Iphedi ithola idatha.
2. I-DDIO IN (1) ithwebula idatha emaphethelweni akhuphukayo naphansi e-ck_fr futhi ithumele idatha, amasiginali (A) kanye no-(B) kusibalo esilandelayo se-waveform, ngenani ledatha elilodwa.
3. I-DDIO IN (2) kanye ne-DDIO IN (3) zinciphisa isilinganiso sedatha ngohhafu.
4. dout[3:0] presents the data as a half-rate bus.

Umfanekiso 3. Indlela Yokufaka I-Waveform kumodi ye-DDIO enokuguqulwa kwe-Half-Rate

Kulesi sibalo, idatha isuka ewashini lesilinganiso esigcwele ngenani ledatha eliphindwe kabili iye kuwashi elinesilinganiso esiyingxenye ngenani ledatha elilodwa. Izinga ledatha lihlukaniswa ngezine futhi usayizi webhasi ukhuphuka ngesilinganiso esifanayo. Konke okuphumayo nge-GPIO IP core kuhlala kungashintshile.

Ubudlelwano bangempela besikhathi phakathi kwamasignali ahlukene bungase buhluke kuye ngedizayini ethile, ukubambezeleka, nezigaba ozikhethayo zamawashi anesilinganiso esigcwele nesilinganiso esiyingxenye.

Qaphela: I-GPIO IP core ayikusekeli ukulinganisa okuguquguqukayo kwamaphinikhodi aqondiswa kabili. Ngezinhlelo zokusebenza ezidinga ukuguqulwa okuguquguqukayo kwamaphinikhodi aqondiswe kabili, bheka ulwazi oluhlobene.

Ulwazi Oluhlobene

• I-PHY Lite ye-Parallel Interfaces Intel FPGA IP Core User Guide: Intel Stratix 10, Intel Arria 10, kanye ne-Intel Cyclone 10 GX Devices
  Ihlinzeka ngolwazi olwengeziwe lwezinhlelo zokusebenza ezidinga i-OCT eguquguqukayo yamaphinikhodi amabili.
• Okukhiphayo Nokukhiphayo Vumela Izindlela ekhasini lesi-7

Okukhiphayo Nokuphumayo Nika amandla Izindlela

I-elementi yokulibaziseka okukhiphayo ithumela idatha kuphedi ngebhafa yokukhiphayo.

Indlela ngayinye yokuphumayo iqukethe ama-s amabilitagama-DDIOs, anesilinganiso esiyingxenye kanye nenani eligcwele.

Umfanekiso 4. Owenziwe lula View yoMgudu Wokukhiphayo we-GPIO enesiphelo esisodwa

Umfanekiso 5. I-Output Path Waveform kumodi ye-DDIO enokuguqulwa kwe-Half-Rate

Umfanekiso 6. Owenziwe Lula View Yokuphuma Ivumela Indlela

Umehluko phakathi kwendlela yokuphumayo nendlela yokuvula amandla (OE) ukuthi indlela ye-OE ayiqukethe i-DDIO enezinga eligcwele. Ukuze kusekelwe ukuqaliswa kokubhaliswa okugcwele kumzila we-OE, irejista elula isebenza njenge-DDIO enenani eligcwele. Ngesizathu esifanayo, i-DDIO eyodwa kuphela yezinga elinguhhafu ekhona.

Umzila we-OE usebenza ngezindlela ezintathu eziyisisekelo ezilandelayo:

• I-Bypass—umongo uthumela idatha ngokuqondile entweni yokubambezeleka, yeqe wonke ama-DDIO.
• Irejista Epakishiwe—idlula i-DDIO yezinga elinguhhafu.
• Okukhiphayo kwe-SDR ngenani elinguhhafu—ama-DDIO esilinganiso esiyingxenye aguqula idatha isuke esilinganisweni esigcwele iye esilinganisweni esiyingxenye.

Qaphela: I-GPIO IP core ayikusekeli ukulinganisa okuguquguqukayo kwamaphinikhodi aqondiswa kabili. Ngezinhlelo zokusebenza ezidinga ukuguqulwa okuguquguqukayo kwamaphinikhodi aqondiswe kabili, bheka ulwazi oluhlobene.

Ulwazi Oluhlobene

• I-PHY Lite ye-Parallel Interfaces Intel FPGA IP Core User Guide: Intel Stratix 10, Intel Arria 10, kanye ne-Intel Cyclone 10 GX Devices
  Ihlinzeka ngolwazi olwengeziwe lwezinhlelo zokusebenza ezidinga i-OCT eguquguqukayo yamaphinikhodi amabili.
• Indlela Yokufaka ekhasini lesi-5

I-GPIO Intel FPGA IP Interface Signals

Kuye ngezilungiselelo zepharamitha ozicacisayo, amasiginali ahlukile wokusebenzelana ayatholakala kumongo we-GPIO IP.

Umfanekiso 7. I-GPIO IP Core Interfaces

Umfanekiso 8. Izimpawu ze-GPIO Interface

Ithebula 3. Amasignali e-Pad Interface

Isixhumi esibonakalayo sephedi ukuxhumana ngokomzimba kusuka kumongo we-GPIO IP kuya kuphedi. Lesi sixhumanisi singaba okokufaka, okukhiphayo noma isixhumi esibonakalayo se-bidirectional, kuye ngokucushwa okuyinhloko kwe-IP. Kuleli thebula, SIZE ububanzi bedatha obucaciswe kusihleli sepharamitha eyinhloko ye-IP.

Igama Lesignali	Isiqondiso	Incazelo
pad_in[SIZE-1:0]	Okokufaka	Isignali yokokufaka evela kuphedi.
pad_in_b[SIZE-1:0]	Okokufaka	I-node enegethivu yesiginali yokufaka ehlukile ukusuka kuphedi. Le port iyatholakala uma uvula Sebenzisa ibhafa ehlukile inketho.
khipha[SIZE-1:0]	Okukhiphayo	Isignali yokuphuma kuphedi.
pad_out_b[SIZE-1:0]	Okukhiphayo	I-node engalungile yesiginali yokuphumayo ehlukile kuphedi. Le port iyatholakala uma uvula Sebenzisa ibhafa ehlukile inketho.
pad_io[SIZE-1:0]	I-Bidirectional	Ukuxhumana kwesignali kabili nephedi.
pad_io_b[SIZE-1:0]	I-Bidirectional	I-node engeyinhle yokuxhumana kwesignali ye-bidirectional ehlukile nephedi. Le port iyatholakala uma uvula Sebenzisa ibhafa ehlukile inketho.

Ithebula 4. Amasignali e-Data Interface

I-interface yedatha iwukuxhumanisa okokufaka noma okukhiphayo kusuka kumongo we-GPIO IP kuya kumongo we-FPGA. Kuleli thebula, SIZE ububanzi bedatha obucaciswe kusihleli sepharamitha eyinhloko ye-IP.

Igama Lesignali	Isiqondiso	Incazelo
din[DATA_SIZE-1:0]	Okokufaka	Okokufaka kwedatha okuvela kumongo we-FPGA kokuphumayo noma kumodi yokuqondiswa kabili. DATA_SIZE incike kumodi yokubhalisa: I-Bypass noma irejista elula—DATA_SIZE = SIZE I-DDIO engenangqondo yesilinganiso esimaphakathi—DATA_SIZE = 2 × SIZE I-DDIO enengqondo yesilinganiso esiyingxenye—DATA_SIZE = 4 × SIZE
dout[DATA_SIZE-1:0]	Okukhiphayo	Ukukhishwa kwedatha kumongo we-FPGA kumodi yokufaka noma yokukhomba kabili, DATA_SIZE incike kumodi yokubhalisa: I-Bypass noma irejista elula—DATA_SIZE = SIZE I-DDIO engenangqondo yesilinganiso esimaphakathi—DATA_SIZE = 2 × SIZE I-DDIO enengqondo yesilinganiso esiyingxenye—DATA_SIZE = 4 × SIZE
i-oe[OE_SIZE-1:0]	Okokufaka	Okokufaka kwe-OE okuvela kumongo we-FPGA kumodi yokukhipha nge Nika amandla imbobo yokuphumayo ivuliwe, noma imodi ye-bidirectional. I-OE iphezulu esebenzayo. Lapho uthumela idatha, setha lesi siginali ibe 1. Lapho uthola idatha, sethela le siginali ibe ngu-0. OE_SIZE incike kwimodi yokubhalisa: I-Bypass noma irejista elula—DATA_SIZE = SIZE I-DDIO engenawo umqondo wokulinganisela uhhafu—DATA_SIZE = SIZE I-DDIO enengqondo yesilinganiso esiyingxenye—DATA_SIZE = 2 × SIZE

Ithebula 5. Amasignali e-interface yewashi

I-interface yewashi iyisixhumi esibonakalayo sewashi okokufaka. Iqukethe amasignali ahlukene, kuye ngokucushwa. I-GPIO IP core ingaba neziro, eyodwa, ezimbili, noma ezine zewashi okokufaka. Izimbobo zewashi zivela ngendlela ehlukile ekucushweni okuhlukene ukuze kubonakale umsebenzi wangempela owenziwa isignali yewashi.

Igama Lesignali	Isiqondiso	Incazelo
ck	Okokufaka	Ezindleleni zokufaka nezokuphumayo, leli washi liphakela irejista epakishiwe noma i-DDIO uma ucisha I-Half Rate logic ipharamitha. Kumodi ye-bidirectional, leli washi liyiwashi eliyingqayizivele lezindlela zokufaka nokukhiphayo uma ucisha iwashi. Hlukanisa amawashi okokufaka/okukhiphayo ipharamitha.
ck_fr	Okokufaka	Ezindleleni zokufaka nezokuphumayo, lawa mawashi ondla ama-DDIO anesilinganiso esigcwele nesikahafu uma uvule I-Half Rate logic ipharamitha. Kumodi ye-bidirectional, izindlela zokufaka nezokukhiphayo zisebenzisa lawashi uma ucisha i Hlukanisa amawashi okokufaka/okukhiphayo ipharamitha.
ck_hr
ck_in	Okokufaka	Kumodi yokuqondisa kabili, lawa mawashi ondla irejista epakishiwe noma i-DDIO kundlela yokufaka neyokukhiphayo uma ucacise zombili lezi zilungiselelo: Vala i- I-Half Rate logic ipharamitha. Vula i- Hlukanisa amawashi okokufaka/okukhiphayo ipharamitha.
ck_ngaphandle
ck_fr_in	Okokufaka	Kumodi ye-bidirectional, lawa mawashi ondla i-DDIOS enesilinganiso esigcwele nesilinganiso esiyingxenye emigwaqweni yokokufaka neyokukhiphayo uma ucacise zombili lezi zilungiselelo. Vula i- I-Half Rate logic ipharamitha. Vula i- Hlukanisa amawashi okokufaka/okukhiphayo ipharamitha. Okwesiboneloample, ck_fr_out iphakela i-DDIO enezinga eligcwele endleleni yokuphuma.
ck_fr_out
ck_hr_in
ck_hr_out
cke	Okokufaka	Iwashi livula amandla.

Ithebula 6. Amasignali eNhlangano Yokunqamula

Isixhumi esibonakalayo sokunqanyulwa sixhuma i-GPIO IP core kumabhafa e-I/O.

Igama Lesignali	Isiqondiso	Incazelo
seriesterminationcontrol	Okokufaka	Okokufaka kusuka kubhulokhi yokulawula ukunqanyulwa (OCT) kuya kumabhafa. Isetha inani le-impedance lochungechunge lwe-buffer.
parallelterminationcontrol	Okokufaka	Okokufaka kusuka kubhulokhi yokulawula ukunqanyulwa (OCT) kuya kumabhafa. Isetha inani le-buffer parallel impedance.

Ithebula 7. Setha Kabusha Izimpawu Zokuhlangana

Isixhumi esibonakalayo sokusetha kabusha sixhuma i-GPIO IP core kuma-DDIO.

Igama Lesignali	Isiqondiso	Incazelo
sclr	Okokufaka	Okokufaka okucacile okuvumelanayo. Ayitholakali uma unika amandla isethi.
aclr	Okokufaka	Okokufaka okucacile okungahambisani. Ukuphakama okusebenzayo. Ayitholakali uma unika amandla i-asethi.
impahla	Okokufaka	Okokufaka kwesethi engavumelanisi. Ukusebenza okuphezulu. Ayitholakali uma unika amandla i-aclr.
isethi	Okokufaka	Okokufaka kwesethi yokuvumelanisa. Ayitholakali uma unika amandla i-sclr.

Ulwazi Oluhlobene
Ibhasi Lokufaka Nokuphumayo Ibhithi Eliphezulu Naphansi ekhasini 12

Amasignali Abiwe

• Okokufaka, okukhiphayo, kanye nezindlela ze-OE zabelana ngamasignali afanayo acacile futhi asethiwe.
• Okukhiphayo kanye nendlela ye-OE yabelana ngamasignali wewashi afanayo.

I-Data Bit-Order ye-Data Interface

Umfanekiso 9. Data Bit-Order Convention

Lesi sibalo sibonisa ukuhlangana kwe-bit-oda yezimpawu zedatha ye-din, doout kanye ne-oe.

• Uma inani likasayizi webhasi ledatha lingu-SIZE, i-LSB isendaweni ekwesokudla kakhulu.
• Uma inani likasayizi webhasi ledatha lingu-2 × SIZE, ibhasi lenziwe ngamagama amabili okuthi SIZE .
• Uma inani likasayizi webhasi ledatha elingu-4 × SIZE, ibhasi lenziwe ngamagama amane ka-SIZE.
• I-LSB isendaweni elungile kakhulu yegama ngalinye.
• Igama elingakwesokudla kakhulu licacisa igama lokuqala eliphumayo kumabhasi aphumayo kanye negama lokuqala elingena kumabhasi okufakwayo.

Ulwazi Oluhlobene
Indlela Yokufaka ekhasini lesi-5

Okokufaka nokukhipha Ibhasi Eliphezulu Naphansi

Amabhithi aphezulu naphansi kumasiginali okufakwayo noma okukhiphayo afakiwe kumabhasi e-din ne-dout input kanye nokuphumayo.

Ibhasi Lokufaka

Ebhasini le-din, uma i-datain_h ne-datain_l kungamabhithi aphakeme naphansi, ububanzi buyi-datain_width:

• datain_h = din[(2 × datain_width – 1):datain_width]
• datain_l = din[(datain_width – 1):0]

Okwesiboneloample, for din[7:0] = 8'b11001010:

• idathain_h = 4'b1100
• idathain_l = 4'b1010

Ibhasi Lokukhipha

Ebhasini le-dout, uma i-dataout_h ne-dataout_l kungamabhithi aphezulu naphansi, ububanzi ngabunye buyi-dataout_width:

• idathaout_h = dout[(2 × dataout_width – 1):dataout_width]
• idathaout_l = dout[(dataout_width – 1):0]

Okwesiboneloample, for dout[7:0] = 8'b11001010:

• idathaout_h = 4'b1100
• idathaout_l = 4'b1010

Izimpawu Zesixhumi Esibonakalayo Sedatha Namawashi Ahambisanayo

Ithebula 8. Amasignali e-Data Interface kanye namawashi ahambisanayo

Igama Lesignali	Ukucushwa kwepharamitha			Iwashi
	Bhalisa Imodi	Isilinganiso esiyingxenye	Amawashi ahlukene
din	Irejista elula I-DDIO	Valiwe	Valiwe	ck
	I-DDIO	On	Valiwe	ck_hr
	Irejista elula I-DDIO	Valiwe	On	ck_in
	I-DDIO	On	On	ck_hr_in
dout oe	Irejista elula I-DDIO	Valiwe	Valiwe	ck
	I-DDIO	On	Valiwe	ck_hr
	Irejista elula I-DDIO	Valiwe	On	ck_ngaphandle
	I-DDIO	On	On	ck_hr_out
sclr isethi Zonke izimpawu zephedi	Irejista elula I-DDIO	Valiwe	Valiwe	ck
	I-DDIO	On	Valiwe	ck_fr
	Irejista elula I-DDIO	Valiwe	On	Indlela yokokufaka: ck_in Indlela yokuphuma: ck_out
	I-DDIO	On	On	Indlela yokokufaka: ck_fr_in Indlela yokuphuma: ck_fr_out

Ukuqinisekisa Ukusetshenziswa Kwensiza kanye Nokusebenza Kwedizayini

Ungabheka imibiko yokuhlanganisa ye-Intel Quartus Prime ukuze uthole imininingwane mayelana nokusetshenziswa kwensiza nokusebenza komklamo wakho.

1. Kumenyu, chofoza Iyacubungula ➤ Qala Ukuhlanganisa ukwenza ukuhlanganiswa okuphelele.
2. Ngemva kokuhlanganisa umklamo, chofoza Kuyacutshungulwa ➤ Umbiko Wokuhlanganiswa.
3. Ukusebenzisa i- Okuqukethwe, zulazulela ku Fitter ➤ Isigaba Sensiza.
   a. Kuya view ulwazi lokusetshenziswa kwensiza, khetha Isifinyezo Sokusetshenziswa Kwensiza.
   b. Ku view imininingwane yokusetshenziswa kwensiza, khetha Ukusetshenziswa Kwezinsiza Ibhizinisi.

Izilungiselelo zepharamitha ye-GPIO Intel FPGA IP

Ungasetha izilungiselelo zepharamitha ye-GPIO IP core kusofthiwe ye-Intel Quartus Prime. Kunamaqembu amathathu wezinketho: Okujwayelekile, Ibhafa, futhi Amarejista.

Ithebula 9. I-GPIO IP Core Parameters - Okujwayelekile

Ipharamitha	Isimo	Amanani Avunyelwe	Incazelo
Idatha Direction	—	Okokufaka Okukhiphayo  I-Bidir	Icacisa isiqondiso sedatha ye-GPIO.
Ububanzi bedatha	—	1 ku128	Icacisa ububanzi bedatha.
Sebenzisa amagama embobo esezingeni eliphezulu	—	On Valiwe	Sebenzisa amagama embobo afanayo njengakumadivayisi we-Stratix V, i-Arria V, ne-Cyclone V. OkwesiboneloampI-le, i-dout iba idathaout_h ne-dataout_l, futhi i-din iba i-datain_h ne-datain_l. Qaphela: Ukuziphatha kwalezi zimbobo kuhlukile kunakumadivayisi we-Stratix V, i-Arria V, ne-Cyclone V. Ukuze uthole umhlahlandlela wokuthutha, bheka ulwazi oluhlobene.

Ithebula 10. I-GPIO IP Core Parameters - Buffer

Ipharamitha	Isimo	Amanani Avunyelwe	Incazelo
Sebenzisa ibhafa ehlukile	—	On  Valiwe	Uma ivuliwe, inika amandla amabhafa e-I/O ahlukile.
Sebenzisa isikhumbuzi sebhafa ehlukile	Data Direction = Okukhiphayo Sebenzisa isihlukanisi sebhafa = Vuliwe	On  Valiwe	Uma ivuliwe kumodi yokuphumayo, inika amandla amabhafa okukhiphayo okungelona iqiniso. Le nketho ivulwa ngokuzenzakalelayo kumodi ye-bidirectional uma uvula Sebenzisa ibhafa ehlukile.
Sebenzisa ukujikeleza kwamabhasi	Ukuqondisa Kwedatha = Okokufaka noma i-Bidir Sebenzisa isihlukanisi sebhafa = Valiwe	On  Valiwe	Uma ivuliwe, isifunda sokubamba ibhasi singabamba isignali kancane kuphinikhodi ye-I/O esimweni sayo sokushayela lapho isimo sebhafa esiphumayo sizoba ngu-1 noma 0 kodwa hhayi ukuthikamezeka okuphezulu.
Sebenzisa okukhiphayo okuvulekile	Ukuqondisa Kwedatha = Okukhiphayo noma I-Bidir Sebenzisa isihlukanisi sebhafa = Valiwe	On  Valiwe	Uma kuvuliwe, okukhiphayo okuvulekile kuvumela idivayisi ukuthi inikeze amasiginali okulawula izinga lesistimu njengokuphazamisa nokubhala amandla amasignali angagonyelwa amadivayisi amaningi kusistimu yakho.
Nika amandla imbobo yokuphumayo	Data Direction = Okukhiphayo	On  Valiwe	Uma ivuliwe, inika amandla okokufaka komsebenzisi embobeni ye-OE. Le nketho ivulwa ngokuzenzakalelayo kumodi ye-bidirectional.
Nika amandla izimbobo zokuqedwa kochungechunge / zokuhambisana	—	On  Valiwe	Uma ivuliwe, inika amandla i-seriesterminationcontrol kanye nezimbobo zokulawula i-paralleltermination zebhafa yokuphumayo.

Ithebula 11. I-GPIO IP Core Parameters - Amarejista

Ipharamitha	Isimo	Amanani Avunyelwe	Incazelo
Imodi yokubhalisa	—	Lutho  Irejista elula  I-DDIO	Icacisa imodi yokubhalisa ye-GPIO IP core: Lutho-icacisa uxhumano lwezintambo olulula ukusuka/kuya kusigcinalwazi. Irejista elula—icacisa ukuthi i-DDIO isetshenziswa njengerejista elula kumodi yedatha yezinga elilodwa (SDR). I-Fitter ingase ipakishe le rejista ku-I/O. I-DDIO- icacisa ukuthi i-IP core isebenzisa i-DDIO.
Nika amandla imbobo ecacile / esethiwe evumelanisiwe	Imodi yokubhalisa = DDIO	Lutho  Kucace  Setha kusengaphambili	Icacisa indlela yokufaka imbobo yokusetha kabusha evumelanisiwe. Lutho-Ikhubaza imbobo yokusetha kabusha ehambisanayo. Kucace-Inika amandla imbobo ye-SCLR yokusula okuvumelanayo. Setha kusengaphambili-Inika amandla imbobo ye-SSET yokusetha ngaphambilini okuvumelanayo.
Nika amandla imbobo ecacile / esethiwe engavumelanisiwe	Imodi yokubhalisa = DDIO	Lutho  Kucace  Setha kusengaphambili	Icacisa indlela yokufaka imbobo yokusetha kabusha engavumelanisiwe. Lutho-Ikhubaza imbobo yokusetha kabusha esynchronous. Kucace-Inika amandla imbobo ye-ACLR ukuze kucace okuhambisanayo. Setha kusengaphambili-Inika amandla imbobo ye-ASET yokusetha kabusha okungavumelaniyo. Izimpawu ze-ACLR ne-ASET ziphezulu.
Nika amandla izimbobo zewashi	Imodi yokubhalisa = DDIO	On  Valiwe	On-Idalula imbobo yewashi (i-CKE) ukuze ikuvumele ukuthi ulawule lapho idatha ivalwa noma ivaliwe. Lesi siginali ivimbela idatha ekudlulisweni ngaphandle kokulawula kwakho. Valiwe-Imbobo yokuvula iwashi ayivezwa futhi idatha idlula njalo kurejista ngokuzenzakalelayo.
I-Half Rate logic	Imodi yokubhalisa = DDIO	On  Valiwe	Uma ivuliwe, inika amandla i-DDIO yesilinganiso esimaphakathi.
Hlukanisa amawashi okokufaka / okukhiphayo	Isiqondiso Sedatha = I-Bidir  Imodi yokubhalisa = Irejista elula noma i-DDIO	On  Valiwe	Uma ivuliwe, inika amandla amawashi ahlukene (CK_IN kanye ne-CK_OUT) emigwaqweni yokokufaka neyokukhiphayo kumodi ye-bidirectional.

Ulwazi Oluhlobene

• Ibhasi Lokufaka Nokuphumayo Ibhithi Eliphezulu Naphansi ekhasini 12
• Isiqondiso: Shintshanisa i-datain_h kanye nezimbobo ze-datain_l ku-IP Ethuthiwe ekhasini 23

Bhalisa Ukupakisha

I-GPIO IP core ikuvumela ukuthi upakishe irejista endaweni ezungezile ukuze ulondoloze indawo nokusetshenziswa kwezinsiza.

Ungakwazi ukumisa i-DDIO enesilinganiso esigcwele endleleni yokufaka nokuphumayo njenge-flip flop. Ukuze wenze njalo, engeza imisebenzi ezokwenziwa ye-qsf esohlwini lwaleli thebula.

Ithebula 12. Bhalisa Ukupakisha Izabelo ze-QSF

Indlela	Isabelo se-QSF
Ukupakisha irejista yokufaka	Isabelo_sesabelo_se-QSF sethiwe_igama_igama FAST_INPUT_REGISTER ON -kuya
Ukupakisha irejista yokuphuma	set_instance_assignment -igama FAST_OUTPUT_REGISTER ON -to
Okukhiphayo vumela ukupakishwa kwerejista	set_instance_assignment -igama FAST_OUTPUT_ENABLE_REGISTER ON -to

Qaphela: Lezi zabelo aziqinisekisi ukupakishwa kwerejista. Nokho, le misebenzi ezokwenziwa ivumela i-Fitter ukuthi ithole ukubekwa okusemthethweni. Uma kungenjalo, i-Fitter igcina i-flip flop kumongo.

I-GPIO Intel FPGA IP Isikhathi

Ukusebenza kwe-GPIO IP core kuncike emikhawulweni ye-I/O nezigaba zewashi. Ukuze uqinisekise isikhathi sokucushwa kwakho kwe-GPIO, i-Intel incoma ukuthi usebenzise i-Timing Analyzer.

Ulwazi Oluhlobene
I-Intel Quartus Prime Timing Analyzer

Izingxenye Zesikhathi

Izingxenye zesikhathi eziyinhloko ze-GPIO IP zihlanganisa izindlela ezintathu.

• Izindlela zokusebenzelana ze-I/O—kusuka ku-FPGA kuya emishinini yokwamukela yangaphandle kanye nakumadivaysi okudlulisela angaphandle kuya ku-FPGA.
• Izindlela zokusebenzelana eziyinhloko zedatha newashi—kusuka ku-I/O kuye kumnyombo futhi kusukela kumnyombo kuya ku-I/O.
• Izindlela zokudlulisa—kusuka kuhhafu wesilinganiso ukuya ku-DDIO yesilinganiso esigcwele, futhi ukusuka ku-DDIO enenani eligcwele ukuya kwehhafu.

Qaphela: I-Timing Analyzer iphatha indlela engaphakathi kwamabhulokhi e-DDIO_IN kanye ne-DDIO_OUT njengamabhokisi amnyama.

Umfanekiso 10. Izingxenye Zesikhathi Sendlela Yokufaka

Umfanekiso 11. Izingxenye Zesikhathi Sendlela Yokuphuma

Umfanekiso 12. Okukhiphayo Nika amandla Izingxenye Zesikhathi Sendlela

Ibambezela Izinto

Isofthiwe ye-Intel Quartus Prime ayibeki ngokuzenzakalelayo izici zokulibaziseka ukuze ikhulise ukuntenga ekuhlaziyeni isikhathi se-I/O. Ukuze uvale isikhathi noma ukhulise ukuntenga, setha izinto zokulibaziseka mathupha kuzilungiselelo ze-Intel Quartus Prime file (.qsf).

Ithebula 13. Izingxenye Zokubambezeleka .qsf Izabelo

Cacisa le misebenzi ezokwenziwa ku-.qsf ukuze ufinyelele izici zokulibaziseka.

Isici sokubambezeleka	.qsf Umsebenzi ozokwenziwa
Isici Sokubambezeleka Kokufaka	set_instance_assignment to -igama INPUT_DELAY_CHAIN ​​<0..63>
Isici Sokubambezeleka Kokukhiphayo	set_instance_assignment to -igama elithi OUTPUT_DELAY_CHAIN ​​<0..15>
Okukhiphayo Nika amandla Isici Sokubambezeleka	set_instance_assignment to -igama OE_DELAY_CHAIN ​​<0..15>

Ukuhlaziya Isikhathi

Isofthiwe ye-Intel Quartus Prime ayikhiqizi ngokuzenzakalelayo izithiyo zesikhathi ze-SDC zomongo we-GPIO IP. Kufanele uzifakele mathupha izithiyo zesikhathi.

Landela imihlahlandlela yesikhathi kanye nesibampukuqinisekisa ukuthi i-Timing Analyzer ihlaziya isikhathi se-I/O ngendlela efanele.

• Ukuze wenze ukuhlaziya isikhathi esifanele sezindlela zokusebenzelana kwe-I/O, cacisa imingcele yeleveli yesistimu yamaphini wedatha ngokumelene nephinikhodi yewashi lesistimu ku-.sdc file.
• Ukuze wenze ukuhlaziya isikhathi esifanele sezindlela zokusebenzelana eziyinhloko, chaza lezi zilungiselelo zewashi ku-.sdc file:
  — Iwashi eliya kumarejista asemqoka
  — Khipha iwashi kurejista ye-I/O ukuze uthole irejista elula kanye nezindlela ze-DDIO

Ulwazi Oluhlobene
I-AN 433: Ukucindezela Nokuhlaziya Izixhumi-zokuxhumana Ezivumelanayo Zomthombo
Ichaza amasu okukhawulela nokuhlaziya ukuxhumana okuvunyelanisiwe komthombo.

Irejista Yokufaka Yesilinganiso Sedatha Eyodwa

Umfanekiso 13. Irejista Yokufaka Yesilinganiso Sedatha Eyodwa

Ithebula 14. Irejista Yokufaka Yesilinganiso Sedatha Eyodwa .sdc Umyalo ExampLes

Umyalo	Yala u-Example	Incazelo
dala_iwashi	create_clock -name sdr_in_clk -period "100 MHz" sdr_in_clk	Idala izilungiselelo zewashi lewashi lokufaka.
setha_ukulibaziseka_kokufaka	set_input_delay -clock sdr_in_clk 0.15 sdr_in_data	Iyala Isihlaziyi Sesikhathi ukuthi sihlaziye isikhathi sokokufaka kwe-I/O ngokubambezeleka kokufaka okungu-0.15 ns.

Irejista Yokufaka Yezinga Eligcwele noma Isilinganiso Sohhafu se-DDIO

Uhlangothi lokokufaka lwerejista ye-DDIO enesilinganiso esigcwele nesilinganiso esiyingxenye luyafana. Ungakwazi ukubopha kahle isistimu ngokusebenzisa iwashi elibonakalayo ukuze wenze imodeli yesidlulisi esiphuma ku-chip siye ku-FPGA.

Umfanekiso 14. Irejista yokufaka ye-DDIO enenani eligcwele noma elihhafu

Ithebula 15. Irejista Yokufaka Yezinga Eligcwele noma Isilinganiso Esiwuhhafu se-DDIO .sdc Command ExampLes

Umyalo	Yala u-Example	Incazelo
dala_iwashi	create_clock -name virtual_clock Isikhathi "200 MHz" create_clock -name ddio_in_clk -inkathi “200 MHz” ddio_in_clk	Dala ukulungiselelwa kwewashi lewashi eliwumbukwane kanye newashi le-DDIO.
setha_ukulibaziseka_kokufaka	set_input_delay -clock virtual_clock 0.25 ddio_in_data set_input_delay -add_delay -iwashi_iwa -washi virtual_clock 0.25 ddio_in_data	Yala i-Timing Analyzer ukuthi ihlaziye umphetho wewashi ophozithivu kanye nonqenqema lwewashi olunegethivu lokudlulisa. Qaphela i- -add_delay kumyalo wesibili we-set_input_delay.
misa_indlela_yamanga	misa_indlela_yamanga -wa_kusuka virtual_clock -rise_to ddio_in_clk set_false_path -phakama_kusuka virtual_clock -fall_to ddio_in_clk	Yalela Isihlaziyi Sesikhathi ukuthi singanaki umkhawulo wewashi ophozithivu onqenqemeni olunegethivu lwerejista ecushiwe, kanye nonqenqema lwewashi olunegethivu ukuya kurejista ecushiwe yonqenqema oluphozithivu. Qaphela: Ifrikhwensi ye-ck_hr kufanele ibe uhhafu wefrikhwensi ye-ck_fr. Uma i-I/O PLL ishayela amawashi, ungacabangela ukusebenzisa umyalo we-derive_pll_clocks .sdc.

Irejista Yokukhipha Isilinganiso Sedatha Eyodwa

Umfanekiso 15. Irejista Yokukhipha Isilinganiso Sedatha Eyodwa

Ithebula 16. Irejista Yokukhishwa Kwesilinganiso Sedatha Eyodwa .sdc Umyalo ExampLes

Umyalo	Yala u-Example	Incazelo
create_clock and create_generated_clock	create_clock -name sdr_out_clk -inkathi "100 MHz" sdr_out_clk create_generated_clock -source sdr_out_clk -name sdr_out_outclk sdr_out_outclk	Khiqiza iwashi eliwumthombo kanye newashi lokukhiphayo ozolidlulisela.
setha_ukulibaziseka_kokukhipha	set_output_delay -clock sdr_out_clk 0.45 sdr_out_data	Iyala i-Timing Analyzer ukuthi ihlaziye idatha yokukhiphayo ukuze idluliselwe ngewashi elikhiphayo ukuze lidluliselwe.

Irejista Yokuphuma Kwezinga Eligcwele noma Isilinganiso Sohhafu se-DDIO

Uhlangothi lokuphumayo lwerejista yezinga eligcwele kanye nesilinganiso esiyingxenye ye-DDIO luyefana.

Ithebula 17. Irejista yokuphuma kwe-DDIO .sdc Umyalo ExampLes

Umyalo	Yala u-Example	Incazelo
create_clock and create_generated_clock	create_clock -name ddio_out_fr_clk -inkathi “200 MHz” ddio_out_fr_clk create_generated_clock -source ddio_out_fr_clk -igama ddio_out_fr_outclk ddio_out_fr_outclk	Khiqiza amawashi ku-DDIO kanye newashi ozolidlulisela.
setha_ukulibaziseka_kokukhipha	set_output_delay -iwashi ddio_out_fr_outclk 0.55 ddio_out_fr_data set_output_delay -add_dey -iwashi_lokuwa -iwashi ddio_out_fr_outclk 0.55 ddio_out_fr_data	Yala i-Timing Analyzer ukuthi ihlaziye idatha evumayo nengalungile iqhathanisa newashi lokukhiphayo.
misa_indlela_yamanga	set_false_path -phakama_kusuka ddio_out_fr_clk -fall_to ddio_out_fr_outclk misa_indlela_yamanga -wa_kusuka ddio_out_fr_clk -rise_to ddio_out_fr_outclk	Yala i-Timing Analyzer ukuthi indibe unqenqema olukhuphukayo lwewashi lomthombo ngokumelene nonqenqema oluwayo lwewashi eliphumayo, kanye nonqenqema oluwayo lwewashi lomthombo ngokumelene nomkhawulo okhuphukayo wewashi eliphumayo.

Izinkombandlela Zokuvalwa Kwesikhathi

Kurejista yokufaka ye-GPIO, ukudluliselwa kwe-I/O okokufaka kungenzeka kuhluleke isikhathi sokubamba uma ungasethi uchungechunge lokulibaziseka okokufaka. Lokhu kwehluleka kubangelwa ukubambezeleka kwewashi kukhulu kunokulibaziseka kwedatha.

Ukuze uhlangabezane nesikhathi sokubamba, engeza ukubambezeleka kumzila wedatha yokufaka usebenzisa uchungechunge lokulibaziseka okokufaka. Ngokuvamile, uchungechunge lokulibaziseka okokufaka lubalelwa ku-60 ps ngesinyathelo ngasinye ebangeni elingu-1 lesivinini. Ukuze uthole ukulungiselelwa kochungechunge lokubambezeleka kokufaka okulinganiselwe ukuze kudlule isikhathi, hlukanisa ukubamba okunegethivu ngo-60 ps.

Nokho, uma i-I/O PLL ishayela amawashi erejista yokufaka ye-GPIO (irejista elula noma imodi ye-DDIO), ungasetha imodi yesinxephezelo ukuze ithole imodi yokuvumelanisa. I-Fitter izozama ukulungisa i-I/O PLL ukuze ikwazi ukusethwa kangcono futhi ibambe kancane ukuze kuhlaziywe isikhathi se-I/O.

Okokukhiphayo nokukhiphayo kunika amandla amarejista we-GPIO, ungangeza ukubambezeleka kudatha yokuphuma newashi usebenzisa okukhiphayo nokukhiphayo kunika amandla amaketanga okulibaziseka.

• Uma ubona ukwephulwa kwesikhathi sokusetha, ungakwazi ukwandisa ukulungiselelwa kochungechunge lokulibaziseka kwewashi.
• Uma ubona ukwephulwa kwesikhathi sokubamba, ungakwazi ukwandisa ukulungiselelwa kochungechunge lokulibaziseka kwedatha.

I-GPIO Intel FPGA IP Design ExampLes

I-GPIO IP core ingakhiqiza i-design exampokufana nokucushwa kwakho kwe-IP kusihleli sepharamitha. Ungasebenzisa lawa ma-ex designampkancane njengezinkomba zokuqinisekisa i-IP core kanye nokuziphatha okulindelekile ekulingiseni.

Ungakwazi ukukhiqiza i-ex designampokuncane kusuka kusihleli sepharamitha eyinhloko ye-GPIO IP. Ngemva kokusetha amapharamitha owafunayo, chofoza Khiqiza Isibample Design. I-IP core ikhiqiza i-ex yedizayiniampumthombo files ohlwini lwemibhalo olucacisayo.

Umfanekiso 16. Umthombo Files ku-Generated Design Example Directory

Qaphela: I-.qsys files ezokusetshenziswa kwangaphakathi phakathi nomklamo example generation kuphela. Awukwazi ukuhlela lezi .qsys files.

I-GPIO IP Core Synthesizable Intel Quartus Prime Design Example

Idizayini ye-synthesizeble exampI-le iwuhlelo lwe-Platform Designer olulungele ukuhlanganisa ongalufaka kuphrojekthi ye-Intel Quartus Prime.

Ukukhiqiza nokusebenzisa i-Design Example

Ukukhiqiza i-Intel Quartus Prime design example kusuka emthonjeni files, sebenzisa umyalo olandelayo ku-design example directory:

quartus_sh -t make_qii_design.tcl

Ukuze ucacise idivayisi efanele ongayisebenzisa, sebenzisa umyalo olandelayo:

quartus_sh -t make_qii_design.tcl [igama_ledivayisi]

Umbhalo we-TCL udala uhla lwemibhalo lwe-qii oluqukethe iphrojekthi ye-ed_synth.qpf file. Ungakwazi ukuvula futhi uhlanganise le phrojekthi ku-Intel Quartus Prime software.

I-GPIO IP Core Simulation Design Example

Idizayini yokulingisa isibampI-le isebenzisa izilungiselelo zakho zepharamitha eyinhloko ye-GPIO IP ukwakha isibonelo se-IP esixhunywe kumshayeli wokulingisa. Umshayeli ukhiqiza ithrafikhi engahleliwe futhi uhlola ngaphakathi ukuba semthethweni kwedatha ephumayo.

Ukusebenzisa i-design example, ungaqalisa ukulingisa usebenzisa umyalo owodwa, kuye ngesifanisi osisebenzisayo. Ukulingisa kukhombisa ukuthi ungasebenzisa kanjani i-GPIO IP core.

Ukukhiqiza nokusebenzisa i-Design Example

Ukukhiqiza umklamo wokulingisa isibample kusuka emthonjeni files yesifanisi se-Verilog, sebenzisa umyalo olandelayo ku-ex designample directory:

quartus_sh -t make_sim_design.tcl

Ukukhiqiza umklamo wokulingisa isibample kusuka emthonjeni files yesifanisi se-VHDL, sebenzisa umyalo olandelayo ku-ex designample directory:

quartus_sh -t make_sim_design.tcl VHDL

Umbhalo we-TCL udala uhla lwemibhalo lwe-sim oluqukethe iziqondiso ezingaphansi—eyodwa kuthuluzi ngalinye lokulingisa elisekelwayo. Ungathola imibhalo yethuluzi ngalinye lokulingisa kunkhombandlela ehambisanayo.

I-IP Migration Flow ye-Arria V, Cyclone V, ne-Stratix V Amadivayisi

Ukugeleza kokuthutha kwe-IP kukuvumela ukuthi uthuthele i-ALTDDIO_IN, ALTDDIO_OUT, ALTDDIO_BIDIR, ne-ALTIOBUF IP cores yamadivayisi we-Arria V, Cyclone V, kanye ne-Stratix V uye ku-GPIO IP core ye-Intel Arria 10 kanye namadivayisi we-Intel Cyclone 10 GX.

Lokhu kugeleza kokuthutha kwe-IP kulungiselela i-GPIO IP core ukuze ifane nezilungiselelo ze-ALTDDIO_IN, ALTDDIO_OUT, ALTDDIO_BIDIR, kanye ne-ALTIOBUF IP cores, okukuvumela ukuthi ukhiqize kabusha i-IP core.

Qaphela: Amanye ama-IP cores asekela ukugeleza kokuthutha kwe-IP ngamamodi athile kuphela. Uma i-IP core yakho ikumodi engasekelwe, ungase udinge ukusebenzisa i-IP Parameter Editor ye-GPIO IP core futhi ulungiselele i-IP core mathupha.

Ithutha i-ALTDDIO_IN, ALTDDIO_OUT, ALTDDIO_BIDIR Yakho, kanye ne-ALTIOBUF IP Cores

Ukuze uthuthele i-ALTDDIO_IN, ALTDDIO_OUT, ALTDDIO_BIDIR, ne-ALTIOBUF IP cores yakho iye ku-GPIO Intel FPGA IP IP core, landela lezi zinyathelo:

1. Vula i-ALTDDIO_IN, ALTDDIO_OUT, ALTDDIO_BIDIR, noma i-ALTIOBUF IP core yakho kusihleli sepharamitha ye-IP.
2. Kwe Umndeni wedivayisi okhethiwe okwamanje, khetha I-Intel Arria 10 or I-Intel Cyclone i-10 GX.
3. Chofoza Qeda ukuvula i-GPIO IP Parameter Editor.
   Isihleli sepharamitha ye-IP silungiselela izilungiselelo eziyinhloko ze-GPIO IP ezifana nezilungiselelo eziyinhloko ze-ALTDDIO_IN, ALTDDIO_OUT, ALTDDIO_BIDIR, noma ze-ALTIOBUF.
4. Uma kukhona amasethingi angahambisani phakathi kwakho kokubili, khetha izilungiselelo ezintsha ezisekelwayo.
5. Chofoza Qeda ukukhiqiza kabusha i-IP core.
6. Miselela i-ALTDDIO_IN, ALTDDIO_OUT, ALTDDIO_BIDIR, noma i-ALTIOBUF IP core instantiation yakho ku-RTL ufake i-GPIO IP core.

Qaphela: Amagama embobo eyinhloko ye-GPIO IP angase angafani ne-ALTDDIO_IN, ALTDDIO_OUT, ALTDDIO_BIDIR, noma amagama embobo ye-ALTIOBUF IP. Ngakho-ke, ukumane uguqule igama eliwumgogodla we-IP kulesi senzo kungase kunganele.

Ulwazi Oluhlobene
Ibhasi Lokufaka Nokuphumayo Ibhithi Eliphezulu Naphansi ekhasini 12

Isiqondiso: Shintshanisa i-datain_h kanye nezimbobo ze-datain_l ku-IP Ethuthiwe

Uma uthutha i-GPIO IP yakho usuka kumadivayisi adlule uye ku-GPIO IP core, ungavula Sebenzisa amagama embobo esezingeni eliphezulu inketho kumhleli wepharamitha eyinhloko ye-GPIO IP. Kodwa-ke, ukuziphatha kwalawa machweba kumongo we-GPIO IP kuhlukile kunakuma-IP cores asetshenziselwa amadivayisi we-Stratix V, i-Arria V, ne-Cyclone V.

I-GPIO IP core ishayela lezi zimbobo kumarejista okukhiphayo kula maphethelo wewashi:

• datain_h—emaphethelweni akhuphukayo ewashi eliphuma ngaphandle
• datain_l—emaphethelweni awelayo ewashi

Uma uthuthe i-GPIO IP yakho kusukela kumadivayisi we-Stratix V, i-Arria V, ne-Cyclone V, shintshanisa i-datain_h nezimbobo ze-datain_l lapho uqinisekisa i-IP ekhiqizwe yi-GPIO IP core.

Ulwazi Oluhlobene
Ibhasi Lokufaka Nokuphumayo Ibhithi Eliphezulu Naphansi ekhasini 12

I-GPIO Intel FPGA IP Umhlahlandlela Wokusetshenziswa Kwezingobo Zomlando

Izinguqulo ze-IP ziyefana nezinguqulo zesofthiwe ye-Intel Quartus Prime Design Suite kufika ku-v19.1. Kusukela ku-Intel Quartus Prime Design Suite software version 19.2 noma kamuva, ama-IP cores anohlelo olusha lwenguqulo ye-IP.

Uma inguqulo ye-IP eyinhloko ingekho ohlwini, umhlahlandlela womsebenzisi wenguqulo yangaphambilini ye-IP iyasebenza.

Inguqulo ye-IP Core	Umhlahlandlela Womsebenzisi
20.0.0	I-GPIO Intel FPGA IP Umhlahlandlela Womsebenzisi: Intel Arria 10 kanye ne-Intel Cyclone 10 GX Amadivayisi
19.3.0	I-GPIO Intel FPGA IP Umhlahlandlela Womsebenzisi: Intel Arria 10 kanye ne-Intel Cyclone 10 GX Amadivayisi
19.3.0	I-GPIO Intel FPGA IP Umhlahlandlela Womsebenzisi: Intel Arria 10 kanye ne-Intel Cyclone 10 GX Amadivayisi
18.1	I-GPIO Intel FPGA IP Umhlahlandlela Womsebenzisi: Intel Arria 10 kanye ne-Intel Cyclone 10 GX Amadivayisi
18.0	I-GPIO Intel FPGA IP Umhlahlandlela Womsebenzisi: Intel Arria 10 kanye ne-Intel Cyclone 10 GX Amadivayisi
17.1	Intel FPGA GPIO IP Core User Guide
17.0	I-Altera GPIO IP Core User Guide
16.1	I-Altera GPIO IP Core User Guide
16.0	I-Altera GPIO IP Core User Guide
14.1	Umhlahlandlela Womsebenzisi we-Altera GPIO Megafunction
13.1	Umhlahlandlela Womsebenzisi we-Altera GPIO Megafunction

Umlando Wokubuyekezwa Kombhalo we-GPIO Intel FPGA IP Umhlahlandlela Womsebenzisi: Intel Arria 10 kanye ne-Intel Cyclone 10 GX Amadivayisi

Inguqulo Yedokhumenti	Inguqulo ye-Intel Quartus Prime	Inguqulo ye-IP	Izinguquko
2021.07.15	21.2	20.0.0	Kubuyekezwe umdwebo obonisa okwenziwe lula view kwendlela yokufaka ye-GPIO enesiphetho esisodwa ukuze ubuyekeze i-dout[0] ukuze i-dout[3] kanye ne-dout[3] ukuze i-dout[0].
2021.03.29	21.1	20.0.0	Kubuyekezwe inombolo yenguqulo ye-GPIO yaba ngu-20.0.0.
2021.03.12	20.4	19.3.0	Kubuyekezwe umhlahlandlela wokuthutha we-IP ukuze ucacise ukuthi i-GPIO IP ishayela i-datain_h onqenqemeni olukhuphukayo kanye ne-datain_l onqenqemeni oluwayo.
2019.10.01	19.3	19.3.0	Kulungiswe iphutha lokuthayipha kumakhodi we-.qsf ozokwenziwa esihlokweni esimayelana nezinto zokulibaziseka.
2019.03.04	18.1	18.1	Ezihlokweni ezimayelana nendlela yokufaka, futhi okukhiphayo nokuphumayo kunika amandla izindlela: Kulungiswe amanothi ezihlokweni ukuze kucaciswe ukuthi i-GPIO Intel FPGA IP ayikusekeli ukulinganisa okuguquguqukayo kwamaphini wokuqondiswa kabili. Kwengezwe izixhumanisi ku-PHY Lite ye-Parallel Interfaces Intel FPGA IP Core User Guide: Intel Stratix 10, Intel Arria 10, kanye ne-Intel Cyclone 10 GX Devices ukuze uthole ulwazi olwengeziwe mayelana nezinhlelo zokusebenza ezidinga ukulinganiswa okuguquguqukayo kwamaphinikhodi amabili.
2018.08.28	18.0	18.0	Iphinde yaqanjwa kabusha idokhumenti esuka ku-Intel FPGA GPIO IP Core User Guide kuya ku-GPIO Intel FPGA IP User Guide: Intel Arria 10 kanye ne-Intel Cyclone 10 GX Devices. Kwengezwe isixhumanisi kumhlahlandlela womsebenzisi we-Intel Stratix 10 GPIO IP.  Iqanjwe kabusha i-IP isuka ku-“Intel FPGA GPIO” yaba “GPIO Intel FPGA IP”.  Izimo ezilungisiwe ze-“clk_fr” kanye ne-“clk_hr” kuya ku-“ck_fr” nokuthi “ck_hr”.  Kubuyekezwe indlela yokufaka ye-GPIO IP kanye nemidwebo yezindlela zokuphuma ukuze kuboniswe amagama angempela esignali ye-IP.

Usuku	Inguqulo	Izinguquko
Novemba 2017	2017.11.06	Usekelo olungeziwe lwamadivayisi e-Intel Cyclone 10 GX. Kubuyekezwe amagama esignali ezibalo ukuze afane namagama esignali kumongo we-GPIO IP. Kwengezwe i-waveform yendlela yokuphumayo. Iqanjwe kabusha ngokuthi “Altera GPIO IP core” yaba “Intel FPGA GPIO IP core”. Iqanjwe kabusha ngokuthi “Altera IOPLL IP core” yaba “Intel FPGA IOPLL IP core”. Iqanjwe kabusha ngokuthi “I-TimeQuest Timing Analyzer” yaba “Isihlaziyi Sesikhathi”. Iqanjwe kabusha ngokuthi “Qsys” yaba “Umklami Wenkundla”. Kucaciswe ukuthi amasiginali we-ASET ne-ACLR ayasebenza phezulu.
Meyi 2017	2017.05.08	Kubuyekezwe ithebula lohlu lwamapharamitha ebhafa ye-GPIO ukuze ucacise izimo ze Sebenzisa ukujikeleza kwamabhasi inketho yepharamitha. Iqanjwe kabusha njenge-Intel.
Okthoba 2016	2016.10.31	Kubuyekezwe i-waveform yendlela yokufaka. Kwengezwe isihloko esichaza amabhithi aphezulu naphansi kumabhasi e-din nama-dout.
Agasti 2016	2016.08.05	Amanothi angeziwe mayelana nokusekelwa kwe-OCT okuguquguqukayo kumongo we-GPIO IP. Kubuyekezwe isihloko esimayelana nezilungiselelo zepharamitha ukuze kuthuthukiswe ukunemba nokucaca. Buyekeza isigaba esimayelana nokukhiqiza i-ex yedizayiniample. Kwengezwe isihloko somhlahlandlela mayelana nokuziphatha kwezimbobo zefa lapho uthuthela ku-GPIO IP core kusukela kumadivayisi we-Stratix V, i-Arria V, ne-Cyclone V. Bhala kabusha futhi uhlele kabusha idokhumenti ukuze kuthuthukiswe ukucaca kanye nokwenza kube lula ukubhekisela kuyo. Izikhathi ezishintshile ze-Quartus II zaba yi-Quartus Prime.
Agasti 2014	2014.08.18	Kwengezwe ulwazi lwesikhathi. Ulwazi olungeziwe lokupakisha irejista. Kwengeziwe Sebenzisa amagama embobo esezingeni eliphezulu ipharamitha. Lena ipharamitha entsha. Ulwazi olungeziwe lokupakisha irejista. Kushintshwe igama elithi megafunction kwafakwa i-IP core.
Novemba 2013	2013.11.29	Ukukhishwa kokuqala.

Thumela Impendulo

I-GPIO Intel FPGA IP Umhlahlandlela Womsebenzisi: Intel Arria 10 kanye ne-Intel Cyclone 10 GX Amadivayisi

Amadokhumenti / Izinsiza

Intel GPIO Intel FPGA IP [pdf] Umhlahlandlela Womsebenzisi GPIO Intel FPGA IP, GPIO, Intel FPGA IP, FPGA IP

Izithenjwa

• Imaniwali yosebenzisayo