Ukucushwa kwesilawuli se-Microsemi IGLOO2 HPMS DDR

Isingeniso

I-IGLOO2 HPMS inesilawuli se-DDR esishumekiwe (HPMS DDR). Lesi silawuli se-DDR senzelwe ukulawula imemori ye-DDR engaphandle kwe-chip. Isilawuli se-HPMS DDR singafinyelelwa ku-HPMS (kusetshenziswa i-HPDMA) kanye nasendwangu ye-FPGA.
Uma usebenzisa I-System Builder ukwakha ibhulokhi yesistimu ehlanganisa i-HPMS DDR, I-System Builder ikulungisela isilawuli se-HPMS DDR ngokusekelwe kokufakiwe nokukhetha kwakho.
Akukho ukucushwa okuhlukile kwe-HPMS DDR okudingwa umsebenzisi. Ukuze uthole imininingwane, sicela ubheke I-IGLOO2 System Builder User's Guide.
Umakhi Wesistimu

Umakhi Wesistimu

Ku-em Builder ukuze ulungiselele i-HPMS DDR ngokuzenzakalelayo.

1.  Kuthebhu Yezici Zedivayisi Yomakhi Wesistimu, hlola Imemori Ye-DDR Yangaphandle ye-HPMS (HPMS DDR).
2. Kuthebhu Yezinkumbulo, khetha Uhlobo Lwenkumbulo ye-DDR:
   • I-DDR2
   •  I-DDR3
   • I-LPDDR
3. Khetha Ububanzi Benkumbulo ye-DDR: 8, 16 noma 32
4. Hlola i-ECC uma ufuna ukuba ne-ECC ye-DDR.
5. Faka isikhathi sokusetha imemori ye-DDR. Lesi yisikhathi lapho inkumbulo ye-DDR idinga ukuqalisa.
6. Chofoza Ukulungiselelwa Kwerejista Yokungenisa ukuze ungenise amanani okubhalisa e-FDDR embhalweni okhona file equkethe amanani erejista. Bheka Ithebula 1 ukuze uthole ukumiswa kwerejista file i-syntax.
   I-Libero igcina ngokuzenzakalelayo le datha yokumisa ku-eNVM. Lapho i-FPGA isethwe kabusha, le datha yokumisa izokopishelwa ngokuzenzakalelayo ku-HPMS DDR.

Umfanekiso 1 • Umakhi Wesistimu ne-HPMS DDR

Ithebula 1 • Ukumiswa Kwerejista File I-syntax

• ddrc_dyn_soft_reset_CR 0x00 ;
• ddrc_dyn_refresh_1_CR 0x27DE ;
• ddrc_dyn_refresh_2_CR 0x30F ;
• ddrc_dyn_powerdown_CR 0x02 ;
• ddrc_dyn_debug_CR 0x00 ;
• ddrc_ecc_data_mask_CR 0x0000 ;
• ddrc_addr_map_col_1_CR 0x3333 ;

Ukucushwa kwesilawuli se-HPMS DDR

Uma usebenzisa Isilawuli se-HPMS DDR ukuze ufinyelele Imemori ye-DDR yangaphandle, Isilawuli se-DDR kufanele siqaliswe ngesikhathi sokusebenza. Lokhu kwenziwa ngokubhala idatha yokumisa kumarejista okucushwa kwesilawuli se-DDR. Ku-IGLOO2, i-eNVM igcina idatha yokumisa irejista futhi ngemva kokusetha kabusha kwe-FPGA, idatha yokumisa ikopishwa isuka ku-eNVM iye kumarejista anikezelwe we-HPMS DDR ukuze aqalise.

Amarejista okulawula e-HPMS DDR
Isilawuli se-HPMS DDR sinesethi yamarejista adinga ukulungiswa ngesikhathi sokusebenza. Amanani okumisa alawa marejista amele amapharamitha ahlukene, njengemodi ye-DDR, ububanzi be-PHY, imodi yokuqhuma, ne-ECC. Ukuze uthole imininingwane ephelele mayelana namarejista okucushwa kwesilawuli se-DDR sicela ubheke ku-Microsemi IGLOO2 User's Guide.
Ukucushwa Kwerejista ye-HPMS MDDR

Ukuze ucacise amanani e-DDR Register:

1. Sebenzisa umhleli wombhalo ngaphandle kwe-Libero SoC, lungiselela umbhalo file equkethe amagama namanani eRejista, njengakuMdwebo 1-1.
2. Kusuka kuthebhu Yenkumbulo Yomakhi Wesistimu, chofoza Ukucushwa Kwerejista Ngenisa.
3. Zulazulela endaweni yombhalo Wokucushwa Kokubhalisa file oyilungisile esinyathelweni soku-1 bese ukhetha i file ukungenisa.

Umfanekiso 1-1 • Bhalisa Idatha Yokumisa - Ifomethi Yombhalo

Ukuqaliswa kwe-HPMS DDR
Idatha Yokucushwa Kwerejista oyingenisayo ye-HPMS DDR ilayishwa ku-eNVM futhi ikopishelwe kumarejista okumisa e-HPMS DDR lapho i-FPGA isethwe kabusha. Asikho isenzo somsebenzisi esidingekayo ukuze uqalise i-HPMS DDR ngesikhathi sokusebenza. Lokhu kuqalisa okuzenzakalelayo nakho kumodelwe ngokulinganisa.

Incazelo Yembobo

I-DDR PHY Interface
Lezi zimbobo zivezwa ezingeni eliphezulu lebhulokhi ekhiqizwe ye-System Builder. Ukuze uthole imininingwane, bheka I-IGLOO2 System Builder User Guide. Xhuma lezi zimbobo kumemori yakho ye-DDR.

Ithebula 2-1 • I-DDR PHY Interface

Igama Lembobo	Isiqondiso	Incazelo
MDDR_CAS_N	PHUMA	I-DRAM CASN
MDDR_CKE	PHUMA	I-DRAM CKE
MDDR_CLK	PHUMA	Iwashi, uhlangothi luka-P
MDDR_CLK_N	PHUMA	Iwashi, N side
MDDR_CS_N	PHUMA	I-DRAM CSN
MDDR_ODT	PHUMA	I-DRAM ODT
MDDR_RAS_N	PHUMA	I-DRAM RASN
MDDR_RESET_N	PHUMA	Setha kabusha i-DRAM ku-DDR3
MDDR_WE_N	PHUMA	I-DRAM WEN
MDDR_ADDR[15:0]	PHUMA	Izingcezu zekheli le-Drum
MDDR_BA[2:0]	PHUMA	Ikheli lasebhange le-Dram
MDDR_DM_RDQS ([3:0]/[1:0]/[0])	NGAPHAKATHI	Imaski Yedatha Yedram
MDDR_DQS ([3:0]/[1:0]/[0])	NGAPHAKATHI	Okokufaka/Okukhiphayo kwe-Dram Data Strobe – P Side
MDDR_DQS_N ([3:0]/[1:0]/[0])	NGAPHAKATHI	Okokufaka/Okukhiphayo kwe-Dram Data Strobe – N Side
MDDR_DQ ([31:0]/[15:0]/[7:0])	NGAPHAKATHI	I-DRAM Data Input/Output
MDDR_DQS_TMATCH_0_IN	IN	I-FIFO kusignali
MDDR_DQS_TMATCH_0_OUT	PHUMA	Isignali ye-FIFO
MDDR_DQS_TMATCH_1_IN	IN	I-FIFO kusignali (32-bit kuphela)
MDDR_DQS_TMATCH_1_OUT	PHUMA	I-FIFO out signal (32-bit kuphela)
MDDR_DM_RDQS_ECC	NGAPHAKATHI	Imaski yedatha ye-Dram ECC
MDDR_DQS_ECC	NGAPHAKATHI	I-Dram ECC Data Strobe Input/Output – P Side
MDDR_DQS_ECC_N	NGAPHAKATHI	I-Dram ECC Data Strobe Input/Output – N Side
MDDR_DQ_ECC ([3:0]/[1:0]/[0])	NGAPHAKATHI	I-DRAM ECC Data Input/Output
MDDR_DQS_TMATCH_ECC_IN	IN	I-ECC FIFO kusignali
MDDR_DQS_TMATCH_ECC_OUT	PHUMA	I-ECC FIFO isignali yokuphuma (32-bit kuphela)

Ububanzi bembobo kwezinye izimbobo buyashintsha kuye ngokukhethwa kobubanzi be-PHY. Isaziso “[a:0]/[b:0]/[c:0]” sisetshenziselwa ukuchaza izimbobo ezinjalo, lapho “[a:0]” ibhekisela kububanzi bembobo lapho kukhethwa ububanzi be-32-bit PHY. , “[b:0]” ihambisana nobubanzi obuyi-16-bit PHY, futhi “[c:0]” ihambisana nobubanzi obuyi-8-bit PHY.

Ukwesekwa Komkhiqizo

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Amadokhumenti / Izinsiza

Ukucushwa kwesilawuli se-Microsemi IGLOO2 HPMS DDR [pdf] Umhlahlandlela Womsebenzisi IGLOO2 HPMS DDR Configuration Controller, IGLOO2, HPMS DDR Controller Configuration, DDR Controller Configuration, Configuration

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