I-MICROCHIP UG0877 SLVS-EC Isamukeli se-Polar Fire FPGA Umhlahlandlela Womsebenzisi
Umlando Wokubuyekeza
Umlando wokubuyekeza uchaza izinguquko ezisetshenziswe kudokhumenti. Izinguquko zifakwe ohlwini ngokubukeza, kuqala ngokushicilelwa kwamanje.
Ukubuyekeza 4.0
Okulandelayo isifinyezo sezinguquko ezenziwe ekubuyekezweni 4.0 kwalo mbhalo.
- Ushintshiwe Umfanekiso 2, ikhasi 2, Umfanekiso 3, ikhasi 3, Umfanekiso 8, ikhasi 6, kanye noMfanekiso 9, ikhasi 7.
- Isigaba esisusiwe Thumela i-PLL, ikhasi 4.
- Ithebula 1 elibuyekeziwe, ikhasi 3, iThebula 3, ikhasi 7, iThebula 4, ikhasi 7, kanye neThebula 5, ikhasi 8.
- Isigaba esibuyekeziwe se-PLL se-Pixel Clock Generation, ikhasi 4.
- Isigaba esibuyekeziwe samapharamitha wokumisa, ikhasi 7.
Ukubuyekeza 3.0
Okulandelayo isifinyezo sezinguquko ezenziwe ekubuyekezweni 3.0 kwalo mbhalo.
- I-SLVS-EC IP, ikhasi 2
- Ithebula 3 ekhasini 7
Ukubuyekeza 2.0
Okulandelayo isifinyezo sezinguquko ezenziwe ekubuyekezweni 2.0 kwalo mbhalo.
- I-SLVS-EC IP, ikhasi 2
- Ukucushwa kwe-Transceiver, ikhasi 3
- Ithebula 3 ekhasini 7
Ukubuyekeza 1.0
Ukubuyekezwa 1.0 kwaba ukushicilelwa kokuqala kwalo mbhalo
I-SLVS-EC IP
I-SLVS-EC iyisixhumi esibonakalayo se-Sony esinesivinini esikhulu sezinzwa zesithombe ze-CMOS zesizukulwane esilandelayo. Leli zinga liyabekezelela i-skew ye-lane-to-lane ngenxa yobuchwepheshe bewashi obushunyekiwe. Kwenza idizayini yezinga lebhodi ibe lula mayelana nokudluliswa kwesivinini esikhulu kanye nokuhamba ibanga elide. I-SLVS-EC Rx IP core inikeza isixhumi esibonakalayo se-SLVS-EC se-PolarFire FPGA ukuthola idatha yenzwa yesithombe. I-IP isekela isivinini esifika ku-4.752 Gbps. I-IP core isekela imizila emibili, emine, nesishiyagalombili yokucushwa kwe-RAW 8, RAW 10, kanye ne-RAW 12. Isibalo esilandelayo sibonisa umdwebo wesistimu wesixazululo sekhamera ye-SLVS-EC.
Umfanekiso 1 • I-SLVS-EC IP Block Diagram
I-Polar Fire® transceiver isetshenziswa njengesixhumi esibonakalayo se-PHY senzwa ye-SLVS-EC njengoba isixhumi esibonakalayo se-SLVS-EC sisebenzisa ubuchwepheshe bewashi elishumekiwe. Iphinde isebenzise umbhalo wekhodi we-8b10b, ongatholwa kusetshenziswa i-PolarFire transceiver. I-PolarFire FPGA inemizila ye-transceiver enamandla aphansi engu-24 engu-12.7 Gbps. Le migqa ye-transceiver ingalungiselelwa njengemizila ye-SLVS-EC PHY yokwamukela. Njengoba kukhonjisiwe esithombeni esandulele, okuphumayo kwe-transceiver kuxhunywe ku-SLVS-EC Rx IP core.
Isixazululo Somamukeli we-SLVS-EC
Isibalo esilandelayo sibonisa ukuqaliswa kokwakhiwa kwesoftware ye-Libero SoC yezinga eliphezulu le-SLVS-EC IP kanye nezingxenye ezidingekayo zesixazululo somamukeli we-SLVS-EC.
Umfanekiso 2 • I-SLVS-EC IP SmartDesign
Ukucushwa kwe-Transceiver
Umfanekiso olandelayo ubonisa ukucushwa kwe-transceiver interface.
Umfanekiso 3 • I-Transceiver Interface Configurator
I-Transceiver ingalungiswa ibe imizila emibili noma emine. Futhi, isivinini se-transceiver singasethwa "Kuzinga ledatha ye-Transceiver". Isixhumi esibonakalayo se-SLVS-EC sisekela izilinganiso ezimbili ze-baud njengoba zibalwe kuthebula elilandelayo.
Ithebula 1 • Izinga le-Baud le-SLVS-EC
| Baud Grade | Isilinganiso se-Baud ku-Mbps |
| 1 | 1188 |
| 2 | 2376 |
| 3 | 4752 |
I-PLL ye-Pixel Clock Generation
I-PLL iyadingeka ukuze kukhiqizwe iwashi le-pixel ewashini Lendwangu ekhiqizwe i-Transceiver okungukuthi, LANE0_RX_CLOCK. Okulandelayo yifomula yokukhiqiza iwashi le-pixel.
Iwashi lephikseli = (LANE0_RX_CLOCK * 8)/DATA_WIDTH
Lungiselela i-PF_CCC ye-RAW 8 njengoba kuboniswe esithombeni esilandelayo.
Umfanekiso 4 • I-Clock Conditioning Circuitry
Incazelo Yomklamo
Umfanekiso olandelayo ubonisa ukwakheka kwefomethi yozimele ye-SLVS-EC.
Umfanekiso 5 • SLVS-EC Uhlaka Lwefomethi
Iheda Yephakethe iqukethe ulwazi mayelana namasignali okuqala nokuphela kozimele kanye nemigqa Evumelekile. Amakhodi okulawula e-PHY engezwa ngaphezu kwesihloko sephakethe ukuze akhe iphakethe le-SLVS-EC. Ithebula elilandelayo libala amakhodi okulawula e-PHY ahlukene asetshenziswa kuphrothokholi ye-SLVS-EC.
Ithebula 2 • Ikhodi Yokulawula ye-PHY
Ikhodi yokulawula ye-PHY 8b10b Inhlanganisela Yophawu
Qala Ikhodi K.28.5 - K.27.7 - K.28.2 - K.27.7
Ikhodi Yokugcina K.28.5 - K.29.7 - K.30.7 - K.29.7
Ikhodi yephedi K.23.7 - K.28.4 - K.28.6 - K.28.3
Vumelanisa Ikhodi K.28.5 - D.10.5 - D.10.5 - D.10.5
Ikhodi engenzi lutho D.00.0 - D.00.0 - D.00.0 - D.00.0
I-SLVS-EC RX IP Core
Lesi sigaba sichaza imininingwane yokusetshenziswa kwezingxenyekazi zekhompuyutha ye-SLVS-EC Receiver IP. Isibalo esilandelayo sibonisa isixazululo sesamukeli se-Sony SLVS-EC esiqukethe i-Polar Fire SLVS-EC RX IP. Le IP isetshenziswa ngokuhambisana ne-Polar Fire transceiver interface block. Umfanekiso olandelayo ubonisa amabhulokhi angaphakathi e-SLVS-EC Rx IP.
Umfanekiso 6 • Amabhulokhi angaphakathi e-SLVS-EC RX IP
i-aligner
Le mojula ithola idatha kumabhulokhi we-PolarFire transceiver futhi iqondaniswe nekhodi yokuvumelanisa. Le mojula ibheka ikhodi yokuvumelanisa kumabhayithi atholwe ku-transceiver futhi ikhiye emngceleni we-byte.
slvsec_phy_rx
Le mojula ithola idatha ku-alignner futhi ihlukanise amaphakethe angenayo e-SLVS PHY. Le mojula idlula ngokulandelana kokuvumelanisa bese, ikhiqiza isignali ye-pkt_en eqala ekhodini yokuqala futhi igcine ekupheleni kwekhodi. Iphinde ikhiphe ikhodi ye-PAD kumaphakethe wedatha futhi ithumele idatha kumojula elandelayo ethi slvsrx_decoder.
slvsrx_decoder
Le mojula ithola idatha kumojula ye-slvsec_phy_rx futhi ikhiphe idatha ye-pixel ekulayisheni. Le mojula ikhipha amaphikseli amane iwashi ngalinye emzileni ngamunye bese ithumela kokuphumayo. Ikhiqiza isignali evumelekile yemigqa esebenzayo eqinisekisa idatha yevidiyo esebenzayo. Iphinde ikhiqize isignali evumelekile yohlaka ngokubheka isiqalo sohlaka nezinqamu zokuphela kozimele kunhlokweni wephakethe lamaphakethe we-SLVS-EC.
I-FSM ene-Data Decoding States
Isibalo esilandelayo sibonisa i-FSM ye-SLVS-EC RX IP.
Umfanekiso 7 • I-FSM ye-SLVS-EC RX IP
I-SLVS-EC Receiver IP Configuration
Isibalo esilandelayo sibonisa isihleli se-IP esamukeli se-SLVS-EC.
Umfanekiso 8 • I-SLVS-EC Receiver IP Configurator
Ukucushwa Amapharamitha
Ithebula elilandelayo libala incazelo yemingcele yokumisa esetshenziswa ekusetshenzisweni kwezingxenyekazi zekhompuyutha ze-SLVS-EC vimba ye-IP yesitholi. Lawa amapharamitha ajwayelekile futhi angahluka ngokuya ngezidingo zohlelo lokusebenza.
Ithebula 3 • Amapharamitha wokumisa
Incazelo yegama
DATA_WIDTH Faka ububanzi bedatha yephikseli. Isekela RAW 8, RAW 10, kanye ne-RAW 12.
LANE_WIDTH Inombolo yemizila ye-SLVS-EC. Isekela imizila emibili, emine, nesishiyagalombili.
BUFF_DEPTH Ukujula kwebhafa. Inombolo yamaphikseli asebenzayo kulayini wevidiyo osebenzayo.
Ukujula kwebhafa kungabalwa ngokusebenzisa isibalo esilandelayo:
BUFF_DEPTH = Isilingi ((Ukulungiswa Okuvundlile * Ububanzi RAW) / (32 * Ububanzi bomzila))
Example: Ububanzi RAW = 8, Ububanzi bomzila = 4, kanye ne-Horizontal Resolution = 1920 pixels
BUFF_DEPTH = Iseyili ((1920 * 8)/ (32* 4)) = 120
Okokufaka kanye Nemiphumela
Ithebula elilandelayo libonisa izimbobo zokufaka nokuphumayo zamapharamitha wokumisa we-SLVS-EC RX IP
Ithebula 4 • Izimbobo Okokufaka Nokuphumayo
| Igama Lesignali | Isiqondiso | Ububanzi | Incazelo |
| LANE#_RX_CLK | Okokufaka | 1 | Iwashi elibuyisiwe ku-transceiver yalowo Mzila othile |
| LANE#_RX_READY | Okokufaka | 1 | Isignali elungile yedatha ye-Lane |
| LANE#_RX_VALID | Okokufaka | 1 | Isignali evumelekile yedatha Yomzila |
| LANE#_RX_DATA | Okokufaka | 32 | Umzila uthole idatha ku-transceiver |
| LINE_VALID_O | Okukhiphayo | 1 | Idatha evumelekile yesignali yamaphikseli asebenzayo emugqeni |
| FRAME_VALID_O | Okukhiphayo | 1 | Isignali evumelekile yemigqa esebenzayo kuhlaka |
| DATA_OUT_O | Okukhiphayo | DATA_WIDTH*LANE_WIDTH*4 | Okukhipha idatha ye-Pixel |
Umdwebo Wesikhathi
Isibalo esilandelayo sibonisa umdwebo wesikhathi we-SLVS-EC IP.
Umfanekiso 9 • I-SLVS-EC IP Timing Diagram
Ukusetshenziswa Kwezinsiza
Ithebula elilandelayo libonisa ukusetshenziswa kwensiza njengeampI-le SLVS-EC Receiver Core isetshenziswe ku-PolarFire FPGA (iphakheji ye-MPF300TS-1FCG1152I), ku-RAW 8 kanye nemizila emine kanye nokulungiswa kokuxazulula okuvundlile okungu-1920.
Ithebula 5 • Ukusetshenziswa Kwezinsiza
| Isici | Ukusetshenziswa |
| Ama-DFF | 3001 |
| 4-okufakiwe kwe-LUT | 1826 |
| Ama-LSRAM | 16 |
Amadokhumenti / Izinsiza
 |
I-MICROCHIP UG0877 SLVS-EC Isamukeli se-PolarFire FPGA [pdf] Umhlahlandlela Womsebenzisi UG0877, UG0877 SLVS-EC Isamukeli se-PolarFire FPGA, SLVS-EC Isamukeli se-PolarFire FPGA, Isamukeli se-PolarFire FPGA, i-PolarFire FPGA |
