Okuqukethwe fihla
1 I-MICROCHIP PolarFire FPGA High Definition Multimedia Interface HDMI Receiver
2 Isifinyezo
3 Izici
4 Amadivayisi Omthombo Ahloliwe (Buza Umbuzo)
5 Ukucushwa kwe-HDMI RX IP (Buza Umbuzo)
6 Ukwenziwa Kwezingxenyekazi Zekhompyutha (Buza Umbuzo)
7 Amapharamitha we-HDMI RX kanye nezimpawu zesibonisi (Buza umbuzo)
8 Ukulingisa kwe-Testbench (Buza Umbuzo)
9 Imiphumela Yokulingisa (Buza Umbuzo)
10 Ukusetshenziswa Kwensiza (Buza Umbuzo)
11 Ukuhlanganiswa Kwesistimu (Buza Umbuzo)
12 Umlando Wokubuyekeza (Buza Umbuzo)
13 Ulwazi lwe-Microchip
14 FAQ
15 Amadokhumenti / Izinsiza
15.1 Izithenjwa
16 Okuthunyelwe Okuhlobene

I-MICROCHIP-LOGO

I-MICROCHIP PolarFire FPGA High Definition Multimedia Interface HDMI Receiver

I-MICROCHIP-PolarFire-FPGA-High-Definition-Multimedia-Interface-HDMI-Receiver- PRODUCT-IMAGE

Isingeniso (Buza Umbuzo)
I-IP yesamukeli se-IP ye-Microchip's High-Definition Multimedia Interface (HDMI) isekela ukwamukelwa kwedatha yevidiyo nephakethe lomsindo elichazwe ekucacisweni okujwayelekile kwe-HDMI. I-HDMI RX IP yakhelwe ngokuqondile i-PolarFire® FPGA kanye ne-PolarFire System ku-Chip (SoC) amadivayisi we-FPGA asekela i-HDMI 2.0 ngezinqumo ezifika ku-1920 × 1080 ku-60 Hz kumodi ye-pixel eyodwa futhi kufika ku-3840 × 2160 ku-60 Hz kumodi yamaphikseli amane. I-RX IP isekela i-Hot Plug Detect (HPD) yamandla okuqapha avuliwe noma avaliwe futhi akhiphe noma axhume imicimbi ukuze abonise ukuxhumana phakathi komthombo we-HDMI nosinki we-HDMI.

Umthombo we-HDMI usebenzisa isiteshi sedatha yokubonisa (i-DDC) ukufunda Idatha Yokuhlonza Isibonisi Esandisiwe sikasinki (EDID) ukuze uthole ukucushwa kweSink kanye/noma amakhono. I-HDMI RX IP ine-EDID ehlelwe ngaphambilini, umthombo we-HDMI ongayifunda ngesiteshi esijwayelekile se-I2C. I-PolarFire FPGA kanye nama-transceivers edivayisi ye-PolarFire SoC FPGA asetshenziswa kanye ne-RX IP ukuze kususwe idatha ye-serial kudatha ye-10-bit. Amashaneli edatha ku-HDMI avunyelwe ukuthi abe nokugebenga okukhulu phakathi kwawo. I-HDMI RX IP isusa i-skew phakathi kwamashaneli edatha isebenzisa i-First-In First-Out (FIFOs). Le IP iguqula idatha ye-Transition Minimized Differential Differential (TMDS) etholwe kumthombo we-HDMI nge-transceiver ibe idatha yamaphikseli angu-24-bit RGB, idatha yomsindo engu-24-bit namasignali okulawula. Amathokheni amane okulawula ajwayelekile ashiwo kuphrothokholi ye-HDMI asetshenziselwa ukuqondisa ngezigaba idatha ngesikhathi sokuchithwa.

Isifinyezo

Ithebula elilandelayo linikeza isifinyezo sezimpawu ze-HDMI RX IP.

Ithebula 1. Izimpawu ze-HDMI RX IP

Inguqulo ye-Core Lo mhlahlandlela womsebenzisi usekela i-HDMI RX IP v5.4.
Imindeni Yedivayisi Esekelwe
  • I-PolarFire® SoC
  • I-PolarFire
Ukugeleza Kwethuluzi Okusekelwe Idinga i-Libero® SoC v12.0 noma ukukhishwa kwakamuva.
Ukusebenzelana Okusekelwe Izixhumi ezibonakalayo ezisekelwa i-HDMI RX IP yilezi:
  • I-AXI4-Stream: Lo mnyombo usekela i-AXI4-Stream kumachweba okukhiphayo. Uma ilungiselelwe kule modi, i-IP ikhipha amasiginali wesikhalazo se-AXI4 Stream ajwayelekile.
  • Okomdabu: Uma kulungiselelwe kule modi, i-IP ikhipha ividiyo yomdabu namasignali omsindo.
Ilayisensi I-HDMI RX IP ihlinzekwa ngezinketho ezimbili zelayisensi ezilandelayo:
  • Ibethelwe: Ikhodi ye-RTL ebethelwe ephelele inikezwa umnyombo. Itholakala mahhala nganoma iyiphi ilayisensi ye-Libero, ivumela umnyombo ukuthi uqiniswe nge-SmartDesign. Ungenza Ukulingisa, Ukuhlanganiswa, Isakhiwo futhi uhlele i-silicon ye-FPGA usebenzisa i-Libero design suite.
  • I-RTL: Ikhodi yomthombo ephelele ye-RTL ilayisense ikhiyiwe, edinga ukuthengwa ngokuhlukana.

Izici

I-HDMI RX IP inezici ezilandelayo:

  • Ihambisana ne-HDMI 2.0
  • Isekela 8, 10, 12 kanye 16 Bits Ukujula Kombala
  • Isekela Amafomethi Wombala njenge-RGB, YUV 4:2:2 kanye ne-YUV 4:4:4
  • Isekela Iphikseli Eyodwa noma Amane Okokufaka Kwewashi ngalinye
  • Isekela Izinqumo ezifika ku-1920 ✕ 1080 ku-60 Hz kumodi ye-One Pixel nokufika ku-3840 ✕ 2160 ku-60 Hz kumodi ye-Four Pixel.
  • Ithola i-Hot-Plug
  • Isekela i-Decoding Scheme - i-TMDS
  • Isekela Okokufaka kwe-DVI
  • Isekela i-Display Data Channel (DDC) kanye Nesiteshi Sedatha Esithuthukisiwe sokubonisa (E-DDC)
  • Isekela isixhumi esibonakalayo soMdabu ne-AXI4 Sokusakaza Sevidiyo Sokudlulisa Idatha Yevidiyo
  • Isekela i-Native kanye ne-AXI4 Stream Interface yomsindo wokudlulisa idatha yomsindo

Izici ezingasekelwe

Okulandelayo izici ezingasekelwe ze-HDMI RX IP:

  • 4:2:0 ifomethi yombala ayisekelwe.
  • I-High Dynamic Range (HDR) kanye ne-High-bandwidth Digital Content Protection (HDCP) azisekelwe.
  • I-variable Refresh Rate (VRR) kanye ne-Auto Low Latency Mode (ALLM) azisekelwe.
  • Amapharamitha e-Horizontal Timing angehlukaniseki ngamane kumodi ye-Four Pixel awasekelwe.

Imiyalelo yokufaka
I-IP core kufanele ifakwe ku-IP Catalogue yesofthiwe ye-Libero® SoC ngokuzenzakalelayo ngomsebenzi wokubuyekeza Ikhathalogi ye-IP kusofthiwe ye-Libero SoC, noma ilandwa mathupha kukhathalogi. Uma i-IP core isifakiwe kukhathalogi ye-IP yesofthiwe ye-Libero SoC, iyalungiswa, ikhiqizwe futhi iqiniswe ngaphakathi kwe-Smart Design ukuze ifakwe kuphrojekthi ye-Libero.

Amadivayisi Omthombo Ahloliwe (Buza Umbuzo)

Ithebula elilandelayo libonisa amadivayisi omthombo ahloliwe.

Ithebula 1-1. Amadivayisi Emithombo Ehloliwe

Amadivayisi Imodi ye-Pixel Izinqumo Zihloliwe Ukujula Kombala (Bit) Imodi Yombala Umsindo
I-quantumdata™ M41h HDMI Analyzer 1 720P 30 FPS, 720P 60 FPS kanye ne-1080P 60 FPS 8 I-RGB, YUV444 kanye ne-YUV422 Yebo
1080P 30 FPS 8, 10, 12 kanye no-16
4 720P 30 FPS, 1080P 30 FPS kanye ne-4K 60 FPS 8
1080P 60 FPS 8, 12 kanye 16
4K 30 FPS 8, 10, 12 kanye no-16
I-Lenovo™ 20U1A007IG 1 1080P 60 FPS 8 I-RGB Yebo
4 1080P 60 FPS kanye ne-4K 30 FPS
I-Dell Latitude 3420 1 1080P 60 FPS 8 I-RGB Yebo
4 I-4K 30 FPS ne-4K 60 FPS
I-Astro VA-1844A HDMI® Tester 1 720P 30 FPS, 720P 60 FPS kanye ne-1080P 60 FPS 8 I-RGB, YUV444 kanye ne-YUV422 Yebo
1080P 30 FPS 8, 10, 12 kanye no-16
4 720P 30 FPS, 1080P 30 FPS kanye ne-4K 30 FPS 8
1080P 30 FPS 8, 12 kanye 16
I-NVIDIA® Jetson AGX Orin 32GB H01 Kit 1 1080P 30 FPS 8 I-RGB Cha
4 4K 60 FPS

Ukucushwa kwe-HDMI RX IP (Buza Umbuzo)

Lesi sigaba sinikeza i-overview ye-HDMI RX IP Configurator interface kanye nezingxenye zayo. I-HDMI RX IP Configurator inikeza isixhumi esibonakalayo esinesithombe sokumisa umnyombo we-HDMI RX. Lesi silungiselelo sivumela umsebenzisi ukuthi akhethe amapharamitha afana nenombolo yamaphikseli, Inombolo yamashaneli omsindo, isixhumi esibonakalayo sevidiyo, isixhumi esibonakalayo somsindo, i-SCRAMBLER, ukujula kombala, ifomethi yombala, i-Testbench kanye nelayisensi. I-Configurator interface ihlanganisa amamenyu okwehlayo kanye nezinketho zokwenza izilungiselelo ngendlela oyifisayo. Ukucushwa okubalulekile kuchazwe kuThebula 4-1. Umfanekiso olandelayo unikeza imininingwane view ye-HDMI RX IP Configurator interface.

Umfanekiso 2-1. I-HDMI RX IP Configurator

I-MICROCHIP-PolarFire-FPGA-High-Definition-Multimedia-Interface-HDMI-Receiver- (1)

Isixhumi esibonakalayo sihlanganisa nezinkinobho OK kanye nethi Khansela ukuze uqinisekise noma ulahle ukulungiselelwa.

Ukwenziwa Kwezingxenyekazi Zekhompyutha (Buza Umbuzo)

Izibalo ezilandelayo zichaza isixhumi esibonakalayo se-HDMI RX IP ne-transceiver (XCVR).

Umfanekiso 3-1. I-HDMI RX Block Diagram

I-MICROCHIP-PolarFire-FPGA-High-Definition-Multimedia-Interface-HDMI-Receiver- (2)

Umfanekiso 3-2. Umdwebo Webhulokhi enemininingwane yomamukeli

I-MICROCHIP-PolarFire-FPGA-High-Definition-Multimedia-Interface-HDMI-Receiver- (3)

I-HDMI RX iqukethe amasekhondi amathathutages:

  • Ukuqondanisa kwesigaba kuqondanisa idatha ehambisanayo ngokuphathelene nokulawula imingcele yamathokheni kusetshenziswa isiliphu sebhithi se-transceiver.
  • Idikhoda ye-TMDS iguqula idatha efakwe ikhodi engu-10-bit ibe idatha yephikseli yevidiyo engu-8-bit, idatha yephakethe yomsindo engu-4-bit kanye namasiginali okulawula angu-2-bit.
  • Ama-FIFO asusa ukutsheka phakathi kwamawashi emizila engu-R, G no-B.

I-Phase Aligner (Buza umbuzo)
Idatha ye-10-bit parallel evela ku-XCVR ayihlali iqondaniswe ngokuphathelene nemingcele yamagama afakwe ikhodi ye-TMDS. Idatha ehambisanayo idinga ukushintshwa kancane futhi iqondaniswe ukuze kuqondwe idatha. Ukuqondanisa isigaba kuqondanisa idatha ehambisanayo engenayo nemingcele yamagama kusetshenziswa isici se-bit-slip ku-XCVR. I-XCVR kumodi ye-Per-Monitor DPI Awareness (PMA) ivumela isici sokushelela kancane, lapho ilungisa ukuqondana kwegama le-10-bit deserialized by 1-bit. Isikhathi ngasinye, ngemva kokulungisa igama le-10-bit ngokushelela kwebhithi elingu-1, liqhathaniswa nanoma yiliphi elinye lamathokheni okulawula amane ephrothokholi ye-HDMI ukukhiya indawo phakathi nesikhathi sokulawula. Igama le-10-bit liqondaniswe kahle futhi lithathwa njengelivumelekile ku-s olandelayotages. Isiteshi sombala ngasinye sinokuqondanisa kwesigaba saso, isikhiphi sekhodi se-TMDS siqala ukukhipha amakhodi kuphela lapho zonke izihlanganisi zesigaba zikhiyiwe ukuze kulungiswe imingcele yamagama.

Idekhoda ye-TMDS (Buza Umbuzo)
Idikhoda ye-TMDS iqoka i-10-bit ekhishwe ku-transceiver ibe yidatha yamaphikseli angu-8-bit ngesikhathi sevidiyo. I-HSYNC, VSYNC kanye ne-PACKET HEADER zenziwa ngesikhathi sokulawula kusukela kudatha yesiteshi esiluhlaza okwesibhakabhaka esingu-10-bit. Idatha yephakethe lomsindo iqoshwe esiteshini u-R no-G ngayinye inamabhithi amane. Idikhoda ye-TMDS yesiteshi ngasinye isebenza ngewashi laso. Ngakho-ke, ingaba ne-skew ethile phakathi kwamashaneli.

Isiteshi kuya ku-Channel De-Skew (Buza Umbuzo)
I-FIFO esuselwe ku-de-skew logic isetshenziselwa ukususa u-skew phakathi kwamashaneli. Isiteshi ngasinye sithola isignali evumelekile evela kumayunithi okuqondanisa kwesigaba ukuze abonise ukuthi idatha engenayo yamabhithi ayi-10 evela kukuqondanisa kwesigaba ivumelekile yini. Uma zonke iziteshi zivumelekile (zizuze ukuqondanisa kwesigaba), imojula ye-FIFO iqala ukudlulisa idatha ngemojula ye-FIFO isebenzisa amasiginali avumela ukufunda nokubhala (ibhala ngokuqhubekayo nokufunda). Uma kutholwa ithokheni yokulawula kunoma yimiphi imiphumela ye-FIFO, ukugeleza kokufunda kuyamiswa, futhi umaka otholiwe uyakhiqizwa ukukhombisa ukufika komaka othile ekusakazweni kwevidiyo. Ukugeleza kokufunda kuqala futhi kuphela uma lo maka usufikile kuzo zontathu iziteshi. Ngenxa yalokho, i-skew efanelekile iyasuswa. Ama-FIFO anewashi elikabili avumelanisa yonke imifudlana yedatha emithathu ewashini lesiteshi esiluhlaza okwesibhakabhaka ukuze asuse i-skew efanele. Umfanekiso olandelayo uchaza indlela yokususa uhlaka lwesiteshi.

Umfanekiso 3-3. Isiteshi kuya ku-Channel De-Skew

I-MICROCHIP-PolarFire-FPGA-High-Definition-Multimedia-Interface-HDMI-Receiver- (4)

I-DDC (Buza Umbuzo)
I-DDC iyisiteshi sokuxhumana esisekelwe esimisweni sebhasi se-I2C. Umthombo usebenzisa imiyalo ye-I2C ukuze ufunde ulwazi oluvela ku-E-EDID kasinki ngekheli lesigqila. I-HDMI RX IP isebenzisa i-EDID echazwe ngaphambilini enokulungiswa okuningi isekela izinqumo ezifika ku-1920 ✕ 1080 ku-60 Hz kumodi ye-One Pixel futhi kufika ku-3840 ✕ 2160 ku-60 Hz kumodi ye-Four Pixel.
I-EDID imele igama lesibonisi njengesibonisi se-Microchip HDMI.

Amapharamitha we-HDMI RX kanye nezimpawu zesibonisi (Buza umbuzo)

Lesi sigaba sidingida amapharamitha kusilungiselelo se-HDMI RX GUI kanye namasiginali we-I/O.

Amapharamitha wokumisa (Buza umbuzo)
Ithebula elilandelayo libala imingcele yokumisa ku-HDMI RX IP.

Ithebula 4-1. Ukucushwa Amapharamitha

Igama lepharamitha Incazelo
Ifomethi Yombala Ichaza isikhala sombala. Isekela amafomethi emibala alandelayo:
  • I-RGB
  • YCbCr422
  • YCbCr444
Ukujula Kombala Icacisa inani lamabhithi ngengxenye yombala ngayinye. Isekela amabhithi angu-8, 10, 12 no-16 engxenyeni ngayinye.
Inombolo yamaphikseli Ibonisa inani lamaphikseli ngokokufaka kwewashi ngalinye:
  • Iphikseli ngewashi = 1
  • Iphikseli ngewashi = 4
I-SCRAMBLER Ukusekela ukulungiswa kwe-4K kumafreyimu angu-60 ngomzuzwana:
  • Uma 1, ukwesekwa kweScrambler kunikwe amandla
  • Uma 0, ukwesekwa kweScrambler kuvaliwe
Inombolo yeziteshi zomsindo Isekela inani lamashaneli omsindo:
  • 2 amashaneli omsindo
  • 8 amashaneli omsindo
Isiguquli Sevidiyo Ukusakaza komdabu kanye ne-AXI
I-Audio Interface Ukusakaza komdabu kanye ne-AXI
Ibhentshi lokuhlola Ivumela ukukhethwa kwendawo yebhentshi lokuhlola. Isekela izinketho ezilandelayo zebhentshi lokuhlola:
  • Umsebenzisi
  • Lutho
Ilayisensi Icacisa uhlobo lwelayisensi. Inikeza izinketho ezimbili zelayisensi ezilandelayo:
  • I-RTL
  • Ibethelwe

Amachweba (Buza Umbuzo)
Ithebula elilandelayo libala okokufaka nokukhiphayo kwe-HDMI RX IP yesixhumi esibonakalayo Somdabu lapho Ifomethi Yombala iyi-RGB.

Ithebula 4-2. Okokufaka nokuphumayo kwesixhumi esibonakalayo somdabu

Igama Lesignali Isiqondiso Ububanzi (Amabhithi) Incazelo
SETHA KABUSHA_N_I Okokufaka 1 Isignali yokusetha kabusha ye-asynchronous esebenzayo-low
R_RX_CLK_I Okokufaka 1 Iwashi elihambisanayo lesiteshi esithi “R” esivela ku-XCVR
G_RX_CLK_I Okokufaka 1 Iwashi elihambisanayo lesiteshi esithi “G” esivela ku-XCVR
B_RX_CLK_I Okokufaka 1 Iwashi elihambisanayo lesiteshi esithi “B” esivela ku-XCVR
EDID_RESET_N_I Okokufaka 1 Isignali yokusetha kabusha esebenzayo-low esynchronous edid
R_RX_VALID_I Okokufaka 1 Isiginali evumelekile evela ku-XCVR yedatha ehambisanayo yesiteshi ethi “R”
G_RX_VALID_I Okokufaka 1 Isiginali evumelekile evela ku-XCVR yedatha ehambisanayo yesiteshi ethi “G”
B_RX_VALID_I Okokufaka 1 Isiginali evumelekile evela ku-XCVR yedatha ehambisanayo yesiteshi ethi “B”
Igama Lesignali Isiqondiso Ububanzi (Amabhithi) Incazelo
DATA_R_I Okokufaka INANI LAMAPHYISISA ✕ amabhithi ayi-10 Ithole idatha efanayo yesiteshi ethi “R” evela ku-XCVR
DATA_G_I Okokufaka INANI LAMAPHYISISA ✕ amabhithi ayi-10 Ithole idatha efanayo yesiteshi ethi “G” evela ku-XCVR
DATA_B_I Okokufaka INANI LAMAPHYISISA ✕ amabhithi ayi-10 Ithole idatha efanayo yesiteshi ethi “B” evela ku-XCVR
SCL_I Okokufaka 1 Okokufaka kwewashi lomkhiqizo le-I2C le-DDC
I-HPD_I Okokufaka 1 Ipulaki eshisayo ibona isignali yokufaka. Umthombo uxhunywe kusiginali ye-HPD kufanele ibe phezulu.
SDA_I Okokufaka 1 Okokufaka kwedatha yomkhiqizo ye-I2C ye-DDC
EDID_CLK_I Okokufaka 1 Iwashi lesistimu lemojula ye-I2C
BIT_SLIP_R_O Okukhiphayo 1 Isiginali ye-bit slip esiteshini "R" se-transceiver
BIT_SLIP_G_O Okukhiphayo 1 Isiginali ye-bit slip esiteshini "G" se-transceiver
BIT_SLIP_B_O Okukhiphayo 1 Isiginali ye-bit shelele esiteshini esithi “B” se-transceiver
VIDEO_DATA_VALID_O Okukhiphayo 1 Idatha yevidiyo ephumayo evumelekile
AUDIO_DATA_VALID_O Okukhiphayo 1 Idatha yomsindo ephumayo evumelekile
H_SYNC_O Okukhiphayo 1 I-pulse yokuvumelanisa evundlile
V_SYNC_O Okukhiphayo 1 I-pulse yokuvumelanisa eqondile esebenzayo
R_O Okukhiphayo INANI LAMAPHIKIHLI ✕ Izingcezu Zokujula Kombala Idatha "R" eqoshwe ikhodi
G_O Okukhiphayo INANI LAMAPHIKIHLI ✕ Izingcezu Zokujula Kombala Idatha ye-"G" ekhishwe ikhodi
B_O Okukhiphayo INANI LAMAPHIKIHLI ✕ Izingcezu Zokujula Kombala Idatha "B" eqoshwe ikhodi
SDA_O Okukhiphayo 1 Idatha yomkhiqizo ye-I2C ye-DDC
I-HPD_O Okukhiphayo 1 Ipulaki eshisayo ibona isignali yokuphumayo
ACR_CTS_O Okukhiphayo 20 I-Audio Clock Regeneration Cycle Timestamp inani
ACR_N_O Okukhiphayo 20 Ipharamitha yenani Lokuvuselela Iwashi Lomsindo (N).
ACR_VALID_O Okukhiphayo 1 Isignali evumelekile yokuvuselela iwashi lomsindo
I-AUDIO_SAMPLE_CH1_O Okukhiphayo 24 Umsindo wesiteshi 1ample data
I-AUDIO_SAMPLE_CH2_O Okukhiphayo 24 Umsindo wesiteshi 2ample data
I-AUDIO_SAMPLE_CH3_O Okukhiphayo 24 Umsindo wesiteshi 3ample data
I-AUDIO_SAMPLE_CH4_O Okukhiphayo 24 Umsindo wesiteshi 4ample data
I-AUDIO_SAMPLE_CH5_O Okukhiphayo 24 Umsindo wesiteshi 5ample data
I-AUDIO_SAMPLE_CH6_O Okukhiphayo 24 Umsindo wesiteshi 6ample data
I-AUDIO_SAMPLE_CH7_O Okukhiphayo 24 Umsindo wesiteshi 7ample data
I-AUDIO_SAMPLE_CH8_O Okukhiphayo 24 Umsindo wesiteshi 8ample data
I-HDMI_DVI_MODE_O Okukhiphayo 1 Okulandelayo izindlela ezimbili:
  • 1: Imodi ye-HDMI
  • 0: Imodi ye-DVI

Ithebula elilandelayo lichaza izimbobo zokufaka neziphumayo ze-HDMI RX IP ye-AXI4 Stream Video Interface.
Ithebula 4-3. Izimbobo Okokufaka Neziphumayo ze-AXI4 Stream Isibonisi Sevidiyo

Igama Lembobo Isiqondiso Ububanzi (Amabhithi) Incazelo
TDATA_O Okukhiphayo INANI LAMAPHIKIHLI ✕ Ukujula Kombala ✕ amabhithi angu-3 Idatha yevidiyo ephumayo [R, G, B]
TVALID_O Okukhiphayo 1 Ividiyo ephumayo ivumelekile
Igama Lembobo Isiqondiso Ububanzi (Amabhithi) Incazelo
I-TLAST_O Okukhiphayo 1 Isignali yokuphela kozimele wokukhiphayo
TUSER_O Okukhiphayo 3
  • kancane 0 = VSYNC
  • bit 1 = Hsync
  •  ibe 2 = 0
  • ibe 3 = 0
TSTRB_O Okukhiphayo 3 I-strobe yedatha yevidiyo ephumayo
TKEEP_O Okukhiphayo 3 Gcina idatha yevidiyo ephumayo

Ithebula elilandelayo lichaza okokufaka nokukhiphayo kwe-HDMI RX IP ye-AXI4 Stream Audio Interface.

Ithebula 4-4. Izimbobo Okokufaka Nezokukhiphayo ze-AXI4 Stream Audio Interface

Igama Lembobo Isiqondiso Ububanzi (Amabhithi) Incazelo
AUDIO_TDATA_O Okukhiphayo 24 Idatha yomsindo ophumayo
I-AUDIO_TID_O Okukhiphayo 3 Ishaneli yomsindo ephumayo
I-AUDIO_TVALID_O Okukhiphayo 1 Isignali evumelekile yomsindo wokukhiphayo

Ithebula elilandelayo libala okokufaka nokukhiphayo kwe-HDMI RX IP yokusetshenziswa kubonwa Komdabu lapho Ifomethi Yombala ithi YUV444.

Ithebula 4-5. Okokufaka nokuphumayo kwesixhumi esibonakalayo somdabu

Igama Lembobo Isiqondiso Ububanzi (Amabhithi) Incazelo
SETHA KABUSHA_N_I Okokufaka 1 Isignali yokusetha kabusha ye-asynchronous esebenzayo-low
LANE3_RX_CLK_I Okokufaka 1 Iwashi elihambisana nesiteshi se-Lane 3 kusuka ku-XCVR
LANE2_RX_CLK_I Okokufaka 1 Iwashi elihambisana nesiteshi se-Lane 2 kusuka ku-XCVR
LANE1_RX_CLK_I Okokufaka 1 Iwashi elihambisana nesiteshi se-Lane 1 kusuka ku-XCVR
EDID_RESET_N_I Okokufaka 1 Isignali yokusetha kabusha esebenzayo-low esynchronous edid
LANE3_RX_VALID_I Okokufaka 1 Isiginali evumelekile evela ku-XCVR yedatha ehambisanayo ye-Lane 3
LANE2_RX_VALID_I Okokufaka 1 Isiginali evumelekile evela ku-XCVR yedatha ehambisanayo ye-Lane 2
LANE1_RX_VALID_I Okokufaka 1 Isiginali evumelekile evela ku-XCVR yedatha ehambisanayo ye-Lane 1
DATA_LANE3_I Okokufaka INANI LAMAPHYISISA ✕ amabhithi ayi-10 Ithole idatha efanayo ye-Lane 3 evela ku-XCVR
DATA_LANE2_I Okokufaka INANI LAMAPHYISISA ✕ amabhithi ayi-10 Ithole idatha efanayo ye-Lane 2 evela ku-XCVR
DATA_LANE1_I Okokufaka INANI LAMAPHYISISA ✕ amabhithi ayi-10 Ithole idatha efanayo ye-Lane 1 evela ku-XCVR
SCL_I Okokufaka 1 Okokufaka kwewashi lomkhiqizo le-I2C le-DDC
I-HPD_I Okokufaka 1 Ipulaki eshisayo ibona isignali yokufaka. Umthombo uxhunywe kusiginali ye-HPD kufanele ibe phezulu.
SDA_I Okokufaka 1 Okokufaka kwedatha yomkhiqizo ye-I2C ye-DDC
EDID_CLK_I Okokufaka 1 Iwashi lesistimu lemojula ye-I2C
BIT_SLIP_LANE3_O Okukhiphayo 1 Isignali yokushelela kancane kuLane 3 we-transceiver
BIT_SLIP_LANE2_O Okukhiphayo 1 Isignali yokushelela kancane kuLane 2 we-transceiver
BIT_SLIP_LANE1_O Okukhiphayo 1 Isignali yokushelela kancane kuLane 1 we-transceiver
VIDEO_DATA_VALID_O Okukhiphayo 1 Idatha yevidiyo ephumayo evumelekile
AUDIO_DATA_VALID_O Okukhiphayo 1 Idatha yomsindo ephumayo evumelekile
H_SYNC_O Okukhiphayo 1 I-pulse yokuvumelanisa evundlile
V_SYNC_O Okukhiphayo 1 I-pulse yokuvumelanisa eqondile esebenzayo
Igama Lembobo Isiqondiso Ububanzi (Amabhithi) Incazelo
Y_O Okukhiphayo INANI LAMAPHIKIHLI ✕ Izingcezu Zokujula Kombala Idatha ethi "Y" eqoshwe
Cb_O Okukhiphayo INANI LAMAPHIKIHLI ✕ Izingcezu Zokujula Kombala Idatha ye-"Cb" ekhishwe ikhodi
Cr_O Okukhiphayo INANI LAMAPHIKIHLI ✕ Izingcezu Zokujula Kombala Idatha ye-"Cr" ekhishwe ikhodi
SDA_O Okukhiphayo 1 Idatha yomkhiqizo ye-I2C ye-DDC
I-HPD_O Okukhiphayo 1 Ipulaki eshisayo ibona isignali yokuphumayo
ACR_CTS_O Okukhiphayo 20 Izikhathi Zomjikelezo Wokuvuselela Iwashi Lomsindoamp inani
ACR_N_O Okukhiphayo 20 Ipharamitha yenani Lokuvuselela Iwashi Lomsindo (N).
ACR_VALID_O Okukhiphayo 1 Isignali evumelekile yokuvuselela iwashi lomsindo
I-AUDIO_SAMPLE_CH1_O Okukhiphayo 24 Umsindo wesiteshi 1ample data
I-AUDIO_SAMPLE_CH2_O Okukhiphayo 24 Umsindo wesiteshi 2ample data
I-AUDIO_SAMPLE_CH3_O Okukhiphayo 24 Umsindo wesiteshi 3ample data
I-AUDIO_SAMPLE_CH4_O Okukhiphayo 24 Umsindo wesiteshi 4ample data
I-AUDIO_SAMPLE_CH5_O Okukhiphayo 24 Umsindo wesiteshi 5ample data
I-AUDIO_SAMPLE_CH6_O Okukhiphayo 24 Umsindo wesiteshi 6ample data
I-AUDIO_SAMPLE_CH7_O Okukhiphayo 24 Umsindo wesiteshi 7ample data
I-AUDIO_SAMPLE_CH8_O Okukhiphayo 24 Umsindo wesiteshi 8ample data

Ithebula elilandelayo libala okokufaka nokukhiphayo kwe-HDMI RX IP yokusetshenziswa kubonwa Komdabu lapho Ifomethi Yombala ithi YUV422.

Ithebula 4-6. Okokufaka nokuphumayo kwesixhumi esibonakalayo somdabu

Igama Lembobo Isiqondiso Ububanzi (Amabhithi) Incazelo
SETHA KABUSHA_N_I Okokufaka 1 Isignali yokusetha kabusha ye-asynchronous esebenzayo-low
LANE3_RX_CLK_I Okokufaka 1 Iwashi elihambisana nesiteshi se-Lane 3 kusuka ku-XCVR
LANE2_RX_CLK_I Okokufaka 1 Iwashi elihambisana nesiteshi se-Lane 2 kusuka ku-XCVR
LANE1_RX_CLK_I Okokufaka 1 Iwashi elihambisana nesiteshi se-Lane 1 kusuka ku-XCVR
EDID_RESET_N_I Okokufaka 1 Isignali yokusetha kabusha esebenzayo-low esynchronous edid
LANE3_RX_VALID_I Okokufaka 1 Isiginali evumelekile evela ku-XCVR yedatha ehambisanayo ye-Lane 3
LANE2_RX_VALID_I Okokufaka 1 Isiginali evumelekile evela ku-XCVR yedatha ehambisanayo ye-Lane 2
LANE1_RX_VALID_I Okokufaka 1 Isiginali evumelekile evela ku-XCVR yedatha ehambisanayo ye-Lane 1
DATA_LANE3_I Okokufaka INANI LAMAPHYISISA ✕ amabhithi ayi-10 Ithole idatha efanayo ye-Lane 3 evela ku-XCVR
DATA_LANE2_I Okokufaka INANI LAMAPHYISISA ✕ amabhithi ayi-10 Ithole idatha efanayo ye-Lane 2 evela ku-XCVR
DATA_LANE1_I Okokufaka INANI LAMAPHYISISA ✕ amabhithi ayi-10 Ithole idatha efanayo ye-Lane 1 evela ku-XCVR
SCL_I Okokufaka 1 Okokufaka kwewashi lomkhiqizo le-I2C le-DDC
I-HPD_I Okokufaka 1 Ipulaki eshisayo ibona isignali yokufaka. Umthombo uxhunywe kusiginali ye-HPD kufanele ibe phezulu.
SDA_I Okokufaka 1 Okokufaka kwedatha yomkhiqizo ye-I2C ye-DDC
EDID_CLK_I Okokufaka 1 Iwashi lesistimu lemojula ye-I2C
BIT_SLIP_LANE3_O Okukhiphayo 1 Isignali yokushelela kancane kuLane 3 we-transceiver
BIT_SLIP_LANE2_O Okukhiphayo 1 Isignali yokushelela kancane kuLane 2 we-transceiver
BIT_SLIP_LANE1_O Okukhiphayo 1 Isignali yokushelela kancane kuLane 1 we-transceiver
VIDEO_DATA_VALID_O Okukhiphayo 1 Idatha yevidiyo ephumayo evumelekile
Igama Lembobo Isiqondiso Ububanzi (Amabhithi) Incazelo
AUDIO_DATA_VALID_O Okukhiphayo 1 Idatha yomsindo ephumayo evumelekile
H_SYNC_O Okukhiphayo 1 I-pulse yokuvumelanisa evundlile
V_SYNC_O Okukhiphayo 1 I-pulse yokuvumelanisa eqondile esebenzayo
Y_O Okukhiphayo INANI LAMAPHIKIHLI ✕ Izingcezu Zokujula Kombala Idatha ethi "Y" eqoshwe
C_O Okukhiphayo INANI LAMAPHIKIHLI ✕ Izingcezu Zokujula Kombala Idatha "C" eqoshwe ikhodi
SDA_O Okukhiphayo 1 Idatha yomkhiqizo ye-I2C ye-DDC
I-HPD_O Okukhiphayo 1 Ipulaki eshisayo ibona isignali yokuphumayo
ACR_CTS_O Okukhiphayo 20 Izikhathi Zomjikelezo Wokuvuselela Iwashi Lomsindoamp inani
ACR_N_O Okukhiphayo 20 Ipharamitha yenani Lokuvuselela Iwashi Lomsindo (N).
ACR_VALID_O Okukhiphayo 1 Isignali evumelekile yokuvuselela iwashi lomsindo
I-AUDIO_SAMPLE_CH1_O Okukhiphayo 24 Umsindo wesiteshi 1ample data
I-AUDIO_SAMPLE_CH2_O Okukhiphayo 24 Umsindo wesiteshi 2ample data
I-AUDIO_SAMPLE_CH3_O Okukhiphayo 24 Umsindo wesiteshi 3ample data
I-AUDIO_SAMPLE_CH4_O Okukhiphayo 24 Umsindo wesiteshi 4ample data
I-AUDIO_SAMPLE_CH5_O Okukhiphayo 24 Umsindo wesiteshi 5ample data
I-AUDIO_SAMPLE_CH6_O Okukhiphayo 24 Umsindo wesiteshi 6ample data
I-AUDIO_SAMPLE_CH7_O Okukhiphayo 24 Umsindo wesiteshi 7ample data
I-AUDIO_SAMPLE_CH8_O Okukhiphayo 24 Umsindo wesiteshi 8ample data

Ithebula elilandelayo libala okokufaka nokukhiphayo kwe-HDMI RX IP yesixhumi esibonakalayo Somdabu lapho i-SCRAMBLER Inikwe amandla.

Ithebula 4-7. Okokufaka nokuphumayo kwesixhumi esibonakalayo somdabu

Igama Lembobo Isiqondiso Ububanzi (Amabhithi) Incazelo
SETHA KABUSHA_N_I Okokufaka 1 Isignali yokusetha kabusha ye-asynchronous esebenzayo-low
R_RX_CLK_I Okokufaka 1 Iwashi elihambisanayo lesiteshi esithi “R” esivela ku-XCVR
G_RX_CLK_I Okokufaka 1 Iwashi elihambisanayo lesiteshi esithi “G” esivela ku-XCVR
B_RX_CLK_I Okokufaka 1 Iwashi elihambisanayo lesiteshi esithi “B” esivela ku-XCVR
EDID_RESET_N_I Okokufaka 1 Isignali yokusetha kabusha esebenzayo-low esynchronous edid
HDMI_CABLE_CLK_I Okokufaka 1 Iwashi lekhebula elisuka kumthombo we-HDMI
R_RX_VALID_I Okokufaka 1 Isiginali evumelekile evela ku-XCVR yedatha ehambisanayo yesiteshi ethi “R”
G_RX_VALID_I Okokufaka 1 Isiginali evumelekile evela ku-XCVR yedatha ehambisanayo yesiteshi ethi “G”
B_RX_VALID_I Okokufaka 1 Isiginali evumelekile evela ku-XCVR yedatha ehambisanayo yesiteshi ethi “B”
DATA_R_I Okokufaka INANI LAMAPHYISISA ✕ amabhithi ayi-10 Ithole idatha efanayo yesiteshi ethi “R” evela ku-XCVR
DATA_G_I Okokufaka INANI LAMAPHYISISA ✕ amabhithi ayi-10 Ithole idatha efanayo yesiteshi ethi “G” evela ku-XCVR
DATA_B_I Okokufaka INANI LAMAPHYISISA ✕ amabhithi ayi-10 Ithole idatha efanayo yesiteshi ethi “B” evela ku-XCVR
SCL_I Okokufaka 1 Okokufaka kwewashi lomkhiqizo le-I2C le-DDC
I-HPD_I Okokufaka 1 Ipulaki eshisayo ibona isignali yokufaka. Umthombo uxhunywe kusinki, futhi isignali ye-HPD kufanele ibe phezulu.
SDA_I Okokufaka 1 Okokufaka kwedatha yomkhiqizo ye-I2C ye-DDC
EDID_CLK_I Okokufaka 1 Iwashi lesistimu lemojula ye-I2C
BIT_SLIP_R_O Okukhiphayo 1 Isiginali ye-bit slip esiteshini "R" se-transceiver
BIT_SLIP_G_O Okukhiphayo 1 Isiginali ye-bit slip esiteshini "G" se-transceiver
Igama Lembobo Isiqondiso Ububanzi (Amabhithi) Incazelo
BIT_SLIP_B_O Okukhiphayo 1 Isiginali ye-bit shelele esiteshini esithi “B” se-transceiver
VIDEO_DATA_VALID_O Okukhiphayo 1 Idatha yevidiyo ephumayo evumelekile
AUDIO_DATA_VALID_O Okukhiphayo1 1 Idatha yomsindo ephumayo evumelekile
H_SYNC_O Okukhiphayo 1 I-pulse yokuvumelanisa evundlile
V_SYNC_O Okukhiphayo 1 I-pulse yokuvumelanisa eqondile esebenzayo
DATA_ RATE_O Okukhiphayo 16 Isilinganiso sedatha ye-Rx. Okulandelayo amanani esilinganiso sedatha:
  • x1734 = 5940 Mbps
  • x0B9A = 2960 Mbps
  •  x05CD = 1485 Mbps
  • x2E6 = 742.5 Mbps
R_O Okukhiphayo INANI LAMAPHIKIHLI ✕ Izingcezu Zokujula Kombala Idatha "R" eqoshwe ikhodi
G_O Okukhiphayo INANI LAMAPHIKIHLI ✕ Izingcezu Zokujula Kombala Idatha ye-"G" ekhishwe ikhodi
B_O Okukhiphayo INANI LAMAPHIKIHLI ✕ Izingcezu Zokujula Kombala Idatha "B" eqoshwe ikhodi
SDA_O Okukhiphayo 1 Idatha yomkhiqizo ye-I2C ye-DDC
I-HPD_O Okukhiphayo 1 Ipulaki eshisayo ibona isignali yokuphumayo
ACR_CTS_O Okukhiphayo 20 Izikhathi Zomjikelezo Wokuvuselela Iwashi Lomsindoamp inani
ACR_N_O Okukhiphayo 20 Ipharamitha yenani Lokuvuselela Iwashi Lomsindo (N).
ACR_VALID_O Okukhiphayo 1 Isignali evumelekile yokuvuselela iwashi lomsindo
I-AUDIO_SAMPLE_CH1_O Okukhiphayo 24 Umsindo wesiteshi 1ample data
I-AUDIO_SAMPLE_CH2_O Okukhiphayo 24 Umsindo wesiteshi 2ample data
I-AUDIO_SAMPLE_CH3_O Okukhiphayo 24 Umsindo wesiteshi 3ample data
I-AUDIO_SAMPLE_CH4_O Okukhiphayo 24 Umsindo wesiteshi 4ample data
I-AUDIO_SAMPLE_CH5_O Okukhiphayo 24 Umsindo wesiteshi 5ample data
I-AUDIO_SAMPLE_CH6_O Okukhiphayo 24 Umsindo wesiteshi 6ample data
I-AUDIO_SAMPLE_CH7_O Okukhiphayo 24 Umsindo wesiteshi 7ample data
I-AUDIO_SAMPLE_CH8_O Okukhiphayo 24 Umsindo wesiteshi 8ample data

Ukulingisa kwe-Testbench (Buza Umbuzo)

I-Testbench ihlinzekwa ukuhlola ukusebenza kwe-HDMI RX core. I-Testbench isebenza ku-Native Interface kuphela lapho inani lamaphikseli lilodwa.

Ukuze ulingise umongo usebenzisa i-testbench, yenza lezi zinyathelo ezilandelayo:

  1. Kuwindi Lokugeleza Kwedizayini, nweba Dala Idizayini.
  2. Chofoza kwesokudla Dala i-SmartDesign Testbench, bese uchofoza u-Run, njengoba kuboniswe esithombeni esilandelayo.
    Umfanekiso 5-1. Idala i-SmartDesign TestbenchI-MICROCHIP-PolarFire-FPGA-High-Definition-Multimedia-Interface-HDMI-Receiver- (5)
  3. Faka igama le-SmartDesign testbench, bese uchofoza okuthi KULUNGILE.
    Umfanekiso 5-2. Ukuqamba i-SmartDesign TestbenchI-MICROCHIP-PolarFire-FPGA-High-Definition-Multimedia-Interface-HDMI-Receiver- (6)I-SmartDesign testbench iyakhiwa, bese kuvela ikhanvasi kwesokudla sefasitelana le-Design Flow.
  4. Zulazulela kukhathalogi ye-Libero® SoC, khetha View > Windows > Ikhathalogi ye-IP, bese unweba Izixazululo-Ividiyo. Chofoza kabili i-HDMI RX IP (v5.4.0) bese uchofoza okuthi KULUNGILE.
  5. Khetha zonke izimbobo, chofoza kwesokudla bese ukhetha Nyusela Kwizinga eliphezulu.
  6. Kubha yamathuluzi ye-SmartDesign, chofoza okuthi Khiqiza Ingxenye.
  7. Kuthebhu ye-Stimulus Hierarchy, chofoza kwesokudla i-HDMI_RX_TB testbench file, bese uchofoza i-Linga Pre-Synth Design > Vula Ngokusebenzisana.

Ithuluzi le-ModelSim® livula ngebhentshi lokuhlola, njengoba kuboniswe emfanekisweni olandelayo.

Umfanekiso 5-3. Ithuluzi le-ModelSim eline-HDMI RX Testbench File

I-MICROCHIP-PolarFire-FPGA-High-Definition-Multimedia-Interface-HDMI-Receiver- (7)

Okubalulekile: If ukulingisa kuphazamisekile ngenxa yomkhawulo wesikhathi sokusebenza oshiwo ku-DO file, sebenzisa umyalo we-run -all ukuze uqedele ukulingisa.

Ilayisensi (Buza Umbuzo)

I-HDMI RX IP ihlinzekwa ngezinketho ezimbili zelayisensi ezilandelayo:

  • Ibethelwe: Ikhodi ye-RTL ebethelwe ephelele inikezwa umnyombo. Itholakala mahhala nganoma iyiphi ilayisensi ye-Libero, ivumela umnyombo ukuthi uqiniswe nge-SmartDesign. Ungenza Ukulingisa, Ukuhlanganiswa, Isakhiwo, futhi uhlele i-silicon ye-FPGA usebenzisa i-Libero design suite.
  • I-RTL: Ikhodi yomthombo ephelele ye-RTL ilayisense ikhiyiwe, edinga ukuthengwa ngokuhlukana.

Imiphumela Yokulingisa (Buza Umbuzo)

Umdwebo wesikhathi olandelayo we-HDMI RX IP ubonisa idatha yevidiyo nokulawula izikhathi zedatha.

Umfanekiso 6-1. Idatha Yevidiyo

I-MICROCHIP-PolarFire-FPGA-High-Definition-Multimedia-Interface-HDMI-Receiver- (8)

Umdwebo olandelayo ubonisa imiphumela ye-hsync ne-vsync yokokufaka kwedatha yokulawula okuhambisanayo.

Umfanekiso 6-2. Ukuvumelanisa Okuvundlile kanye Nezimpawu Zokuvumelanisa Eziqondile

I-MICROCHIP-PolarFire-FPGA-High-Definition-Multimedia-Interface-HDMI-Receiver- (9)

Umdwebo olandelayo ubonisa ingxenye ye-EDID.

Umfanekiso 6-3. Izimpawu ze-EDID

I-MICROCHIP-PolarFire-FPGA-High-Definition-Multimedia-Interface-HDMI-Receiver- (10)

Ukusetshenziswa Kwensiza (Buza Umbuzo)

I-HDMI RX IP isetshenziswa ku-PolarFire® FPGA (MPF300T – 1FCG1152I Package). Ithebula elilandelayo libonisa izinsiza ezisetshenziswa lapho Inombolo Yamaphikseli = 1 pixel.

Ithebula 7-1. Ukusetshenziswa Kwensiza kumodi ye-Pixel engu-1

Ifomethi Yombala Ukujula Kombala I-SCRAMBLER Indwangu 4LUT Indwangu DFF Isixhumi esibonakalayo 4LUT Isixhumi esibonakalayo se-DFF i-SRAM (64×12) I-LSRAM (20k)
I-RGB 8 Khubaza 987 1867 360 360 0 10
10 Khubaza 1585 1325 456 456 11 9
12 Khubaza 1544 1323 456 456 11 9
16 Khubaza 1599 1331 492 492 14 9
YCbCr422 8 Khubaza 1136 758 360 360 3 9
YCbCr444 8 Khubaza 1105 782 360 360 3 9
10 Khubaza 1574 1321 456 456 11 9
12 Khubaza 1517 1319 456 456 11 9
16 Khubaza 1585 1327 492 492 14 9

Ithebula elilandelayo libonisa izinsiza ezisetshenziswa lapho Inombolo Yamaphikseli = 4 pixels.

Ithebula 7-2. Ukusetshenziswa Kwensiza kumodi ye-Pixel engu-4

Ifomethi Yombala Ukujula Kombala I-SCRAMBLER Indwangu 4LUT Indwangu DFF Isixhumi esibonakalayo 4LUT Isixhumi esibonakalayo se-DFF i-SRAM (64×12) I-LSRAM (20k)
I-RGB 8 Khubaza 1559 1631 1080 1080 9 27
12 Khubaza 1975 2191 1344 1344 31 27
16 Khubaza 1880 2462 1428 1428 38 27
I-RGB 10 Nika amandla 4231 3306 1008 1008 3 27
12 Nika amandla 4253 3302 1008 1008 3 27
16 Nika amandla 3764 3374 1416 1416 37 27
YCbCr422 8 Khubaza 1485 1433 912 912 7 23
YCbCr444 8 Khubaza 1513 1694 1080 1080 9 27
12 Khubaza 2001 2099 1344 1344 31 27
16 Khubaza 1988 2555 1437 1437 38 27

Ithebula elilandelayo libonisa izinsiza ezisetshenziswa lapho Inombolo yamaphikiseli = 4 pixel kanye ne-SCRAMBLER inikwe amandla.

Ithebula 7-3. Ukusetshenziswa Kwensiza Yemodi ye-Pixel engu-4 kanye ne-SCRAMBLER kunikwe amandla

Ifomethi Yombala Ukujula Kombala I-SCRAMBLER Indwangu 4LUT Indwangu DFF Isixhumi esibonakalayo 4LUT Isixhumi esibonakalayo se-DFF i-SRAM (64×12) I-LSRAM (20k)
I-RGB 8 Nika amandla 5029 5243 1126 1126 9 28
YCbCr422 8 Nika amandla 4566 3625 1128 1128 13 27
YCbCr444 8 Nika amandla 4762 3844 1176 1176 17 27

Ukuhlanganiswa Kwesistimu (Buza Umbuzo)

Lesi sigaba sibonisa indlela yokuhlanganisa i-IP kumklamo we-Libero.
Ithebula elilandelayo libonisa ukucushwa kwe-PF XCVR, PF TX PLL kanye ne-PF CCC edingekayo ukuze kube nezinqumo ezihlukene nobubanzi bebhithi.

Ithebula 8-1. PF XCVR, PF TX PLL kanye nePF CCC Configurations

Isixazululo Ububanzi Obuncane PF XCVR Ukucushwa I-CDR REF AMAPHEDI WEWASHI Ukucushwa kwe-PF CCC
Isilinganiso sedatha ye-RX I-RX CDR Ref Clock Frequency RX PCS Fabric Width Imvamisa Yokufaka Imvamisa Yokuphuma
1 PXL (1080p60) 8 1485 148.5 10 AE27, AE28 NA NA
1 PXL (1080p30) 10 1485 148.5 10 AE27, AE28 92.5 74
12 1485 148.5 10 AE27, AE28 74.25 111.375
16 1485 148.5 10 AE27, AE28 74.25 148.5
4 PXL (1080p60) 8 1485 148.5 40 AE27, AE28 NA NA
12 1485 148.5 40 AE27, AE28 55.725 37.15
16 1485 148.5 40 AE27, AE28 74.25 37.125
4 PXL (4kp30) 8 1485 148.5 40 AE27, AE28 NA NA
10 3712.5 148.5 40 AE29, AE30 92.81 74.248
12 4455 148.5 40 AE29, AE30 111.375 74.25
16 5940 148.5 40 AE29, AE30 148.5 74.25
4 PXL (4Kp60) 8 5940 148.5 40 AE29, AE30 NA NA

I-HDMI RX SampI-Design 1: Uma kulungiselelwa Ukujula Kombala = 8-bit kanye Nenombolo Yamaphikseli = Imodi yePixel engu-1, iboniswa esithombeni esilandelayo.

Umfanekiso 8-1. I-HDMI RX Sample Design 1

I-MICROCHIP-PolarFire-FPGA-High-Definition-Multimedia-Interface-HDMI-Receiver- (11)

Okwesiboneloample, ekucushweni kwe-8-bit, izingxenye ezilandelayo ziyingxenye yomklamo:

  • I-PF_XCVR_ERM (PF_XCVR_ERM_C0_0) ilungiselelwe i-TX ne-RX egcwele imodi ye-duplex. Isilinganiso sedatha ye-RX esingu-1485 Mbps kumodi ye-PMA, ububanzi bedatha bulungiselelwe njengo-10 bit kumodi engu-1 PXL kanye newashi eliyireferensi elingu-148.5 MHz CDR. Isilinganiso sedatha ye-TX esingu-1485 Mbps kumodi ye-PMA, nobubanzi bedatha bulungiselelwe njengebhithi elingu-10 elinesici sokuhlukanisa iwashi 4.
  • I-LANE0_CDR_REF_CLK, LANE1_CDR_REF_CLK, LANE2_CDR_REF_CLK kanye ne-LANE3_CDR_REF_CLK ashayelwa ukusuka ku-PF_XCVR_REF_CLK ngamaphinikhodi e-AE27, AE28.
  • Iphinikhodi ye-EDID CLK_I kufanele ishayelwe ngewashi elingu-150 MHz nge-CCC.
  • I-R_RX_CLK_I, G_RX_CLK_I kanye ne-B_RX_CLK_I ishayelwa i-LANE3_TX_CLK_R, LANE2_TX_CLK_R kanye ne-LANE1_TX_CLK_R, ngokulandelana.
  • I-R_RX_VALID_I, G_RX_VALID_I kanye ne-B_RX_VALID_I ishayelwa yi-LANE3_RX_VAL, LANE2_RX_VAL kanye ne-LANE1_RX_VAL, ngokulandelana.
  • I-DATA_R_I, DATA_G_I kanye ne-DATA_B_I ishayelwa yi-LANE3_RX_DATA, LANE2_RX_DATA kanye ne-LANE1_RX_DATA, ngokulandelana.

I-HDMI RX SampI-Design 2: Uma kulungiselelwa Ukujula Kombala = 8-bit kanye Nenombolo Yamaphikseli = Imodi yePixel engu-4, iboniswa esithombeni esilandelayo.

Umfanekiso 8-2. I-HDMI RX Sample Design 2

I-MICROCHIP-PolarFire-FPGA-High-Definition-Multimedia-Interface-HDMI-Receiver- (12)

Okwesiboneloample, ekucushweni kwe-8-bit, izingxenye ezilandelayo ziyingxenye yomklamo:

  • I-PF_XCVR_ERM (PF_XCVR_ERM_C0_0) ilungiselelwe i-TX ne-RX egcwele imodi ye-duplex. Isilinganiso sedatha ye-RX esingu-1485 Mbps kumodi ye-PMA, ububanzi bedatha bulungiselelwe njengo-40 bit kumodi engu-4 PXL kanye newashi eliyireferensi elingu-148.5 MHz CDR. Isilinganiso sedatha ye-TX esingu-1485 Mbps kumodi ye-PMA, nobubanzi bedatha bulungiselelwe njengebhithi elingu-40 elinesici sokuhlukanisa iwashi 4.
  • I-LANE0_CDR_REF_CLK, LANE1_CDR_REF_CLK, LANE2_CDR_REF_CLK kanye ne-LANE3_CDR_REF_CLK ashayelwa ukusuka ku-PF_XCVR_REF_CLK ngamaphinikhodi e-AE27, AE28.
  • Iphinikhodi ye-EDID CLK_I kufanele ishayelwe ngewashi elingu-150 MHz nge-CCC.
  • I-R_RX_CLK_I, G_RX_CLK_I kanye ne-B_RX_CLK_I ishayelwa i-LANE3_TX_CLK_R, LANE2_TX_CLK_R kanye ne-LANE1_TX_CLK_R, ngokulandelana.
  • I-R_RX_VALID_I, G_RX_VALID_I kanye ne-B_RX_VALID_I ishayelwa yi-LANE3_RX_VAL, LANE2_RX_VAL kanye ne-LANE1_RX_VAL, ngokulandelana.
  • I-DATA_R_I, DATA_G_I kanye ne-DATA_B_I ishayelwa yi-LANE3_RX_DATA, LANE2_RX_DATA kanye ne-LANE1_RX_DATA, ngokulandelana.

I-HDMI RX SampI-Design 3: Uma kulungiselelwa Ukujula Kombala = 8-bit kanye Nenombolo Yamaphikseli = 4 Imodi yePixel kanye ne-SCRAMBLER = Inikwe amandla, iboniswa esithombeni esilandelayo.

Umfanekiso 8-3. I-HDMI RX Sample Design 3

I-MICROCHIP-PolarFire-FPGA-High-Definition-Multimedia-Interface-HDMI-Receiver- (13)

Okwesiboneloample, ekucushweni kwe-8-bit, izingxenye ezilandelayo ziyingxenye yomklamo:

  • I-PF_XCVR_ERM (PF_XCVR_ERM_C0_0) ilungiselelwe i-TX nemodi ezimele ye-RX. Izinga ledatha le-RX elingu-5940 Mbps kumodi ye-PMA, ububanzi bedatha bulungiselelwe njengo-40 bit kumodi engu-4 ye-PXL kanye newashi eliyireferensi elingu-148.5 MHz CDR. Izinga ledatha ye-TX elingu-5940 Mbps kumodi ye-PMA, nobubanzi bedatha bulungiselelwe njengo-40 bit nge-clock division factor 4.
  • I-LANE0_CDR_REF_CLK, LANE1_CDR_REF_CLK, LANE2_CDR_REF_CLK kanye ne-LANE3_CDR_REF_CLK ashayelwa ukusuka ku-PF_XCVR_REF_CLK ngamaphinikhodi angu-AF29, AF30.
  • Iphinikhodi ye-EDID CLK_I kufanele ishayele ngewashi elingu-150 MHz nge-CCC.
  • I-R_RX_CLK_I, G_RX_CLK_I kanye ne-B_RX_CLK_I ishayelwa i-LANE3_TX_CLK_R, LANE2_TX_CLK_R kanye ne-LANE1_TX_CLK_R, ngokulandelana.
  • I-R_RX_VALID_I, G_RX_VALID_I kanye ne-B_RX_VALID_I ishayelwa yi-LANE3_RX_VAL, LANE2_RX_VAL kanye ne-LANE1_RX_VAL, ngokulandelana.
  • I-DATA_R_I, DATA_G_I kanye ne-DATA_B_I ishayelwa yi-LANE3_RX_DATA, LANE2_RX_DATA kanye ne-LANE1_RX_DATA, ngokulandelana.

I-HDMI RX SampI-Design 4: Uma kulungiselelwa Ukujula Kombala = 12-bit kanye Nenombolo Yamaphikseli = 4 Imodi yePixel kanye ne-SCRAMBLER = Inikwe amandla, iboniswa esithombeni esilandelayo.

Umfanekiso 8-4. I-HDMI RX Sample Design 4

I-MICROCHIP-PolarFire-FPGA-High-Definition-Multimedia-Interface-HDMI-Receiver- (14)

Okwesiboneloample, ekucushweni kwe-12-bit, izingxenye ezilandelayo ziyingxenye yomklamo:

  • I-PF_XCVR_ERM (PF_XCVR_ERM_C0_0) ilungiselelwe imodi ye-RX Kuphela. Isilinganiso sedatha ye-RX esingu-4455 Mbps kumodi ye-PMA, ububanzi bedatha bulungiselelwe njengo-40 bit kumodi engu-4 ye-PXL kanye newashi eliyireferensi elingu-148.5 MHz CDR.
  • I-LANE0_CDR_REF_CLK, LANE1_CDR_REF_CLK, LANE2_CDR_REF_CLK kanye ne-LANE3_CDR_REF_CLK ashayelwa ukusuka ku-PF_XCVR_REF_CLK ngamaphinikhodi angu-AF29, AF30.
  • Iphinikhodi ye-EDID CLK_I kufanele ishayele ngewashi elingu-150 MHz nge-CCC.
  • I-R_RX_CLK_I, G_RX_CLK_I kanye ne-B_RX_CLK_I ishayelwa i-LANE3_TX_CLK_R, LANE2_TX_CLK_R kanye ne-LANE1_TX_CLK_R, ngokulandelana.
  • I-R_RX_VALID_I, G_RX_VALID_I kanye ne-B_RX_VALID_I ishayelwa yi-LANE3_RX_VAL, LANE2_RX_VAL kanye ne-LANE1_RX_VAL, ngokulandelana.
  • I-DATA_R_I, DATA_G_I kanye ne-DATA_B_I ishayelwa yi-LANE3_RX_DATA, LANE2_RX_DATA kanye ne-LANE1_RX_DATA, ngokulandelana.
  • Imojula ye-PF_CCC_C0 ikhiqiza iwashi eliqanjwe ngokuthi OUT0_FABCLK_0 elinemvamisa engu-74.25 MHz, ephuma ewashini lokokufaka elingu-111.375 MHz, elishayelwa i-LANE1_RX_CLK_R.

I-HDMI RX SampI-Design 5: Uma kulungiselelwa Ukujula Kombala = 8-bit, Inombolo Yamaphikseli = 4 Imodi yePixel kanye ne-SCRAMBLER = Inikwe amandla iboniswa esithombeni esilandelayo. Lo mklamo uyisilinganiso sedatha esiguqukayo nge-DRI.

Umfanekiso 8-5. I-HDMI RX Sample Design 5

I-MICROCHIP-PolarFire-FPGA-High-Definition-Multimedia-Interface-HDMI-Receiver- (15)

Okwesiboneloample, ekucushweni kwe-8-bit, izingxenye ezilandelayo ziyingxenye yomklamo:

  • I-PF_XCVR_ERM (PF_XCVR_ERM_C0_0) ilungiselelwe imodi ye-RX Kuphela ene-interface enikwe amandla yokulungisa kabusha. Izinga ledatha le-RX elingu-5940 Mbps kumodi ye-PMA, ububanzi bedatha bulungiselelwe njengo-40 bit kumodi engu-4 ye-PXL kanye newashi eliyireferensi elingu-148.5 MHz CDR.
  • I-LANE0_CDR_REF_CLK, LANE1_CDR_REF_CLK, LANE2_CDR_REF_CLK kanye ne-LANE3_CDR_REF_CLK ashayelwa ukusuka ku-PF_XCVR_REF_CLK ngamaphinikhodi angu-AF29, AF30.
  • Iphinikhodi ye-EDID CLK_I kufanele ishayele ngewashi elingu-150 MHz nge-CCC.
  • I-R_RX_CLK_I, G_RX_CLK_I kanye ne-B_RX_CLK_I ishayelwa i-LANE3_TX_CLK_R, LANE2_TX_CLK_R kanye ne-LANE1_TX_CLK_R, ngokulandelana.
  • I-R_RX_VALID_I, G_RX_VALID_I kanye ne-B_RX_VALID_I ishayelwa yi-LANE3_RX_VAL, LANE2_RX_VAL kanye ne-LANE1_RX_VAL, ngokulandelana.
  • I-DATA_R_I, DATA_G_I kanye ne-DATA_B_I ishayelwa yi-LANE3_RX_DATA, LANE2_RX_DATA kanye ne-LANE1_RX_DATA, ngokulandelana.

Umlando Wokubuyekeza (Buza Umbuzo)

Umlando wokubuyekeza uchaza izinguquko ezisetshenziswe kudokhumenti. Izinguquko zifakwe ohlwini ngokubukeza, kuqala ngokushicilelwa kwamanje.

Ithebula 9-1. Umlando Wokubuyekeza

Buyekeza Usuku Incazelo
D 02/2025 Okulandelayo uhlu lwezinguquko ezenziwe ekubuyekezweni C kwedokhumenti:
  • Kubuyekezwe inguqulo ye-HDMI RX IP yaba ngu-5.4.
  • Isingeniso Esibuyekeziwe esinezici nezici ezingasekelwe.
  • Isigaba Samadivayisi Omthombo Ahloliwe Wengeziwe.
  • Umfanekiso Obuyekeziwe 3-1 kanye noMfanekiso 3-3 esigabeni SokuSebenzisa Izingxenyekazi zekhompuyutha.
  • Isigaba se-Add Configuration Parameters.
  • Ithebula 4-2 elibuyekeziwe, Ithebula 4-4, Ithebula 4-5, Ithebula 4-6 kanye neThebula 4-7 esigabeni samachweba.
  • Kubuyekezwe Umfanekiso 5-2 kusigaba se-Testbench Simulation.
  • Ithebula 7-1 elibuyekeziwe kanye neThebula 7-2 lengeze Ithebula 7-3 esigabeni Sokusetshenziswa Kwezinsiza.
  • Umfanekiso Obuyekeziwe 8-1, Umfanekiso 8-2, Umfanekiso 8-3 kanye noMfanekiso 8-4 esigabeni Sokuhlanganiswa Kwesistimu.
  • Kwengezwe izinga ledatha eliguqukayo nge-DRI design example ku-System Integrationn ingxenye.
C 02/2023 Okulandelayo uhlu lwezinguquko ezenziwe ekubuyekezweni C kwedokhumenti:
  • Kubuyekezwe inguqulo ye-HDMI RX IP yaba ngu-5.2
  • Kubuyekezwe ukulungiswa okusekelwayo ngemodi yamaphikseli amane kuyo yonke idokhumenti
  • Kubuyekeziwe Umfanekiso 2-1
B 09/2022 Okulandelayo uhlu lwezinguquko ezenziwe ekubuyekezweni B kwedokhumenti:
  • Kubuyekezwe idokhumenti ye-v5.1
  • Kubuyekeziwe Ithebula 4-2 kanye neThebula 4-3
A 04/2022 Okulandelayo uhlu lwezinguquko ekubuyekezweni A kwedokhumenti:
  • Idokhumenti ithuthelwe kusifanekiso se-Microchip
  • Inombolo yedokhumenti ibuyekezelwe ku-DS50003298A isuka ku-50200863
  • I-Decoder ye-TMDS yesigaba esibuyekeziwe
  • Amathebula abuyekeziwe Ithebula 4-2 kanye neThebula 4-3
  •  Umfanekiso Obuyekeziwe 5-3, Umfanekiso 6-1, Umfanekiso 6-2
2.0 — Okulandelayo isifinyezo sezinguquko ezenziwe kulesi sibuyekezo.
  • Kwengezwe Ithebula 4-3
  • Amathebula Okusetshenziswa Kwensiza Okubuyekeziwe
1.0 08/2021 Ukubuyekezwa Kokuqala.

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I-ISBN: 979-8-3371-0744-8

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LOLU LWAZI LUNIKEZWA YI-MICROCHIP “NJENGOBA LUKHO”. I-MICROCHIP AYIKUMELELI NOMA IZIQINISEKISO ZANOMA YILUPHI UHLOBO NOMA KUCHAZEKILE NOMA OKUSHIWO, OKUBHALWE NOMA OKUSHIWO, OKUMTHETHO NOMA OKUNYE, OKUPHATHELENE NOLWAZI KUBANDAKANYA KODWA AKUkhawulelwe KUNOMA YILUPHI ISIQINISEKISO, UKWENZA, UKWENZA, UKWENZA, UKWENZA. NGENHLOSO ETHILE, NOMA IZIQINISEKISO EZIPHATHELENE NEsimo, IKHWALITHI, NOMA UKUSEBENZA KWAYO.
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Ukusetshenziswa kwamadivayisi e-Microchip ekusekeleni impilo kanye/noma izicelo zokuphepha kusengozini yomthengi ngokuphelele, futhi umthengi uyavuma ukuvikela, ukunxephezela nokubamba i-Microchip engenabungozi kunoma yimuphi nanoma yimuphi umonakalo, izimangalo, amasudi, noma izindleko ezibangelwa ukusetshenziswa okunjalo. Awekho amalayisensi adluliswayo, ngokusobala noma ngenye indlela, ngaphansi kwanoma imaphi amalungelo empahla yengqondo ye-Microchip ngaphandle kwalapho kushiwo ngenye indlela.

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FAQ

  • Q: Ngiyibuyekeza kanjani i-HDMI RX IP core?
    A: I-IP core ingabuyekezwa ngesofthiwe ye-Libero SoC noma ilandwe mathupha kukhathalogi. Uma isifakiwe kukhathalogi ye-IP yesofthiwe ye-Libero SoC, ingalungiswa, yenziwe, futhi ifakwe ngaphakathi kwe-SmartDesign ukuze ifakwe kuphrojekthi.

Amadokhumenti / Izinsiza

I-MICROCHIP PolarFire FPGA High Definition Multimedia Interface HDMI Receiver [pdf] Umhlahlandlela Womsebenzisi
PolarFire FPGA, PolarFire FPGA High Definition Multimedia Interface HDMI Receiver, High Definition Multimedia Interface HDMI Receiver, Multimedia Interface HDMI Receiver, Interface HDMI Receiver, HDMI Receiver.

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