I-PolarFire Family FPGA Custom Flow User Guide
I-Libero SoC v2024.2

Isingeniso (Buza Umbuzo)

Isoftware ye-Libero System-on-Chip (SoC) ihlinzeka ngendawo yokuklama ye-Field Programmable Gate Array (FPGA) ehlanganiswe ngokugcwele. Kodwa-ke, abasebenzisi abambalwa bangase bafune ukusebenzisa amathuluzi okuhlanganiswa okuvela eceleni namathuluzi okulingisa ngaphandle kwemvelo ye-Libero SoC. I-Libero manje ingahlanganiswa nemvelo yokuklama ye-FPGA. Kunconywa ukusebenzisa i-Libero SoC ukuphatha konke ukugeleza komklamo we-FPGA.
Lo mhlahlandlela womsebenzisi uchaza Ukugeleza Ngokwezifiso kwamadivayisi we-PolarFire kanye ne-PolarFire SoC Family, inqubo yokuhlanganisa i-Libero njengengxenye yokugeleza komklamo omkhulu we-FPGA. I-Supported Device Families® Ithebula elilandelayo libala imindeni yedivayisi esekelwa yi-Libero SoC. Nokho, olunye ulwazi kulo mhlahlandlela lungasebenza kuphela kumndeni othile wamadivayisi. Kulokhu, ulwazi olunjalo lubonakala ngokucacile.
Ithebula 1. Imindeni Yedivayisi Esekelwa I-Libero SoC

Umndeni Wedivayisi	Incazelo
I-PolarFire®	Ama-FPGA e-PolarFire aletha amandla aphansi embonini ekuminyaneni kwebanga elimaphakathi ngokuvikeleka okukhethekile nokwethembeka.
I-PolarFire SoC	I-PolarFire SoC iyi-SoC FPGA yokuqala eneqoqo le-CPU elinqunyiwe, elihambisanayo le-RISC-V, kanye nesistimu engaphansi yememori ye-L2 evumela i-Linux® kanye nezinhlelo zokusebenza zesikhathi sangempela.

Kuphelileview (Buza Umbuzo)

Ngenkathi i-Libero SoC ihlinzeka ngendawo yokuklama edidiyelwe ngokuphelele yokuphela-kuya-ekupheleni ukuze kuthuthukiswe imiklamo ye-SoC ne-FPGA, futhi ihlinzeka ngokuguquguquka kokuqalisa ukuhlanganisa nokulingisa ngamathuluzi ezinkampani zangaphandle ngaphandle kwemvelo ye-Libero SoC. Kodwa-ke, ezinye izinyathelo zokuklama kufanele zihlale ngaphakathi kwemvelo ye-Libero SoC.
Ithebula elilandelayo libonisa izinyathelo ezinkulu ekugelezeni komklamo we-FPGA futhi libonisa izinyathelo okufanele zisetshenziswe i-Libero SoC.
Ithebula 1-1. I-FPGA Design Flow

Isinyathelo Sokugeleza Kwedizayini	Kufanele usebenzise i-Libero	Incazelo
Ukufakwa Kwedizayini: HDL	Cha	Sebenzisa umhleli/ithuluzi lokuhlola le-HDL lenkampani yangaphandle ngaphandle kwe-Libero® SoC uma uthanda.
Ukufakwa Kwedizayini: Izihleli	Yebo	Dala iphrojekthi yokuqala ye-Libero yokukhiqiza ingxenye eyinhloko yekhathalogi ye-IP.
Ukukhiqiza okuzenzakalelayo kwe-PDC/SDC	Cha	Imikhawulo etholiwe idinga yonke i-HDL files kanye nensizakalo ye-derive_constraints lapho yenziwa ngaphandle kwe-Libero SoC, njengoba kuchazwe ku-Appendix C—Derive Constraints.
Ukulingisa	Cha	Sebenzisa ithuluzi lenkampani yangaphandle ngaphandle kwe-Libero SoC, uma uthanda. Idinga ukulandwa kwamalabhulali okulingisa ahlanganiswe ngaphambilini kudivayisi eqondiwe, isifanisi esiqondiwe, kanye nenguqulo ye-Libero eqondiwe esetshenziselwa ukusetshenziswa kwe-backend.
I-synthesis	Cha	Sebenzisa ithuluzi lenkampani yangaphandle ngaphandle kwe-Libero SoC uma uthanda.
Ukuqaliswa Kokuklama: Phatha Izithiyo, Hlanganisa Uhlu Lwe-Netlist, Indawo Nomzila (bona Ngaphezuluview)	Yebo	Dala iphrojekthi yesibili ye-Libero yokusetshenziswa kwe-backend.
Isikhathi nokuqinisekiswa kwamandla	Yebo	Hlala kuphrojekthi yesibili ye-Libero.
Lungiselela Idizayini Yokuqalisa Idatha Nezinkumbulo	Yebo	Sebenzisa leli thuluzi ukuze uphathe izinhlobo ezihlukene zezinkumbulo kanye nokuqaliswa kwedizayini kudivayisi. Hlala kuphrojekthi yesibili.
Ukuhlela File Isizukulwane	Yebo	Hlala kuphrojekthi yesibili.

Okubalulekile: Wena kufanele ulande imitapo yolwazi eseyakhiwe ngaphambilini etholakala ku Imitapo yolwazi yokulingisa ehlanganisiwe ikhasi lokusebenzisa isifanisi senkampani yangaphandle.
Ngokugeleza okumsulwa kwe-Fabric FPGA, faka umklamo wakho usebenzisa i-HDL noma okufakiwe okuhleliwe bese ukudlulisa lokho ngqo
kumathuluzi e-synthesis. Ukugeleza kusasekelwa. I-PolarFire kanye ne-PolarFire SoC FPGAs zibalulekile
amabhlogo aqinile we-IP adinga ukusetshenziswa kwama-cores okumiswa (SgCores) asuka ku-Libero SoC IP
ikhathalogi. Ukuphatha okukhethekile kuyadingeka kunoma imaphi amabhlogo ahlanganisa ukusebenza kwe-SoC:

• I-PolarFire
  – PF_UPROM
  – PF_SYSTEM_SERVICES
  – PF_CCC
  - I-PF CLK DIV
  – PF_CRYPTO
  – PF_DRI
  – PF_INIT_MONITOR
  – PF_NGMUX
  – PF_OSC
  - Ama-RAM (i-TPSRAM, i-DPSRAM, i-URAM)
  – PF_SRAM_AHBL_AXI
  – PF_XCVR_ERM
  – PF_XCVR_REF_CLK
  – PF_TX_PLL
  – PF_PCIE
  – PF_IO
  – PF_IOD_CDR
  – PF_IOD_CDR_CCC
  – PF_IOD_GENERIC_RX
  – PF_IOD_GENERIC_TX
  – PF_IOD_GENERIC_TX_CCC
  – PF_RGMII_TO_GMII
  – PF_IOD_OCTAL_DDR
  – PF_DDR3
  – PF_DDR4
  – PF_LPDDR3
  – PF_QDR
  – PF_CORESMARTBERT
  – PF_TAMPER
  - PF_TVS, njalonjalo.

Ngokungeziwe kuma-SgCores esohlwini olwandulele, maningi ama-IP athambile e-DirectCore atholakalayo emindenini yedivayisi ye-PolarFire kanye ne-PolarFire SoC kukhathalogi ye-Libero SoC esebenzisa izinsiza zendwangu ye-FPGA.
Ukungena kokuklama, uma usebenzisa noma iyiphi yezingxenye ezandulele, kufanele usebenzise i-Libero SoC njengengxenye yokufakiwe komklamo (Ukucushwa Kwengxenye), kodwa ungaqhubeka nakho konke Okufakiwe Kokuklama kwakho (okufakiwe kwe-HDL, nokunye) ngaphandle kwe-Libero. Ukuze uphathe ukugeleza kwedizayini ye-FPGA ngaphandle kwe-Libero, landela izinyathelo ezinikezwe kuwo wonke lo mhlahlandlela.
1.1 Umjikelezo Wempilo Yengxenye (Buza Umbuzo)
Izinyathelo ezilandelayo zichaza umjikelezo wempilo wengxenye ye-SoC futhi zinikeza imiyalelo yokuthi ungaphatha kanjani idatha.

1. Khiqiza ingxenye usebenzisa isihleli sayo ku-Libero SoC. Lokhu kukhiqiza izinhlobo ezilandelayo zedatha:
   - HDL files
   – Inkumbulo files
   - I-Stimulus kanye nokulingisa files
   - Ingxenye ye-SDC file
2. Okwe-HDL files, ziqinise futhi uzihlanganise kuwo wonke umklamo we-HDL usebenzisa ithuluzi/inqubo yokufaka umklamo wangaphandle.
3. Nikeza inkumbulo files kanye nesikhuthazo files kuthuluzi lakho lokulingisa.
4. Ukunikezwa kwengxenye ye-SDC file ukuze uthole ithuluzi le-Constraint for Constraint Generation. Bheka I-Appendix C—Derive Constraints ukuze uthole imininingwane eyengeziwe.
5. Kufanele udale iphrojekthi yesibili ye-Libero, lapho ungenisa khona uhlu lwe-post-Synthesis kanye nemethadatha yengxenye yakho, ngaleyo ndlela uqedele ukuxhumana phakathi kwalokho okukhiqizile nalokho okuhlelayo.

1.2 Ukudalwa kwephrojekthi ye-Libero SoC (Buza Umbuzo)
Ezinye izinyathelo zokuklama kufanele ziqhutshwe ngaphakathi kwemvelo ye-Libero SoC (Ithebula 1-1). Ukuze lezi zinyathelo zisebenze, kufanele udale amaphrojekthi amabili we-Libero SoC. Iphrojekthi yokuqala isetshenziselwa ukucushwa kwengxenye yedizayini kanye nokwenza, futhi iphrojekthi yesibili ingeyokusetshenziswa ngokomzimba komklamo wezinga eliphezulu.
1.3 Ukugeleza Ngokwezifiso (Buza Umbuzo)
Umfanekiso olandelayo ubonisa:

• I-Libero SoC ingahlanganiswa njengengxenye yokugeleza komklamo omkhulu we-FPGA ngokuhlanganisa okuvela eceleni namathuluzi okulingisa ngaphandle kwemvelo ye-Libero SoC.
• Izinyathelo ezihlukahlukene ezihilelekile ekugelezeni, kusukela ekudalweni kwedizayini nokuthunga yonke indlela ukuya ekuhleleni idivayisi.
• Ukushintshisana kwedatha (okokufaka kanye nokuphumayo) okufanele kwenzeke esinyathelweni ngasinye sokugeleza komklamo.

Ithiphu:

1. SNVM.cfg, UROMM.cfg
2. *.mem file isizukulwane Sokulingisa: i-pa4rtupromgen.exe ithatha i-UPROM.cfg njengokufaka bese ikhiqiza i-UPROM.mem.

Okulandelayo yizinyathelo zokugeleza ngokwezifiso:

1. Ukucushwa kwengxenye nokukhiqiza:
   a. Dala iphrojekthi yokuqala ye-Libero (ukuze usebenze njengeReference Project).
   b. Khetha i-Core ku-Catalog. Chofoza kabili indikimba ukuze uyinike igama lengxenye futhi ulungiselele ingxenye.
   Lokhu kuthumela ngokuzenzakalelayo idatha yengxenye futhi files. I-Component Manifest nayo iyakhiqizwa. Bona Imininingwane Yengxenye ukuze uthole imininingwane. Ukuze uthole imininingwane eyengeziwe, bheka Ukucushwa Kwengxenye.
2. Qedela umklamo wakho we-RTL ngaphandle kwe-Libero:
   a. Qinisekisa ingxenye ye-HDL files.
   b. Le yindawo ka HDL files isohlwini lwama-Manifest Engxenye files.
3. Khiqiza izithiyo ze-SDC zezingxenye. Sebenzisa insiza ye-Derive Constraints ukuze ukhiqize umkhawulo wesikhathi file(SDC) isekelwe ku:
   a. Ingxenye ye-HDL files
   b. Ingxenye ye-SDC files
   c. I-HDL yomsebenzisi files
   Ukuze uthole imininingwane eyengeziwe, bheka I-Appendix C—Derive Constraints.
4. Ithuluzi lokuhlanganisa/ithuluzi lokulingisa:
   a. Thola i-HDL files, i-stimulus files, kanye nedatha yengxenye evela ezindaweni ezithile njengoba kushiwo ku-Component Manifests.
   b. Hlanganisa futhi ulingise umklamo ngamathuluzi ezinkampani zangaphandle ngaphandle kwe-Libero SoC.
5. Dala iphrojekthi yakho yesibili (Ukusebenza) ye-Libero.
6. Khipha ukuhlanganisa ochungechungeni lwethuluzi lokugeleza kwedizayini (Iphrojekthi > Izilungiselelo Zephrojekthi > Ukugeleza Kwedizayini > sula ibhokisi lokuhlola elithi Vumela Ukuhlanganisa).
7. Ngenisa umthombo wokuklama files (post-synthesis *.vm netlist kusuka kuthuluzi lokuhlanganisa):
   – Ngenisa i-post-synthesis *.vm netlist (File>Ngenisa> I-Verilog Netlist Ehlanganisiwe (VM)).
   – Imethadatha yengxenye *.cfg files ye-uPROM kanye/noma i-sNVM.
8. Ngenisa noma iyiphi ingxenye yebhulokhi ye-Libero SoC files. Ibhulokhi fileu-s kufanele abe ku-*.cxz file ifomethi.
   Ukuze uthole ulwazi olwengeziwe mayelana nendlela yokudala i-block, bheka I-PolarFire Block Flow Umhlahlandlela Womsebenzisi.
9. Ngenisa izingqinamba zedizayini:
   – Ngenisa I/O umkhawulo files (Umphathi Wezingqinamba > I/OAttributes > Ngenisa).
   – Ngenisa i-floorplanning *.pdc files (Umphathi Wezingqinamba > Umhleli Waphansi > Ngenisa).
   – Ngenisa *.sdc umkhawulo wesikhathi files (Umphathi Wezingqinamba > Isikhathi >Ngenisa). Ngenisa iSDC file ekhiqizwa ngethuluzi le-Derive Constraint.
   – Ngenisa *.ndc umkhawulo files (Umphathi Wezingqinamba > I-NetlistAttributes > Ngenisa), uma ikhona.
10. Ukucindezela file kanye nokuhlangana kwamathuluzi
    – Kumphathi Wezingqinamba, hlobanisa *.pdc files ukubeka nomzila, i-*.sdc files ukubeka kanye nomzila kanye nokuqinisekiswa kwesikhathi, kanye ne-*.ndc files ukuhlanganisa i-Netlist.
11. Qedela ukuqaliswa komklamo
    - Indawo nomzila, qinisekisa isikhathi namandla, lungiselela idatha yokuqalisa idizayini nezinkumbulo, nohlelo file isizukulwane.
12. Qinisekisa umklamo
    - Qinisekisa umklamo ku-FPGA futhi ulungise iphutha usebenzisa amathuluzi okuklama anikezwe ne-Libero SoC design suite.

Ukucushwa kwengxenye (Buza Umbuzo)

Isinyathelo sokuqala sokugeleza ngokwezifiso ukulungisa izingxenye zakho usebenzisa iphrojekthi yereferensi ye-Libero (ebizwa nangokuthi iphrojekthi ye-Libero yokuqala kuThebula 1-1). Ezinyathelweni ezilandelayo, usebenzisa idatha esuka kule phrojekthi yesithenjwa.
Uma usebenzisa noma yiziphi izingxenye ezibalwe ngaphambili, ngaphansi kwe-Overview ekwakhiweni kwakho, yenza izinyathelo ezichazwe kulesi sigaba.
Uma ungasebenzisi noma yiziphi izingxenye zalezi ezingenhla, ungabhala i-RTL yakho ngaphandle kwe-Libero futhi uyingenise ngokuqondile kumathuluzi akho Okwenziwa kanye Nokulingisa. Ungabe usuqhubekela esigabeni sangemuva kokuhlanganiswa bese ungenisa kuphela i-post-synthesis yakho *.vm netlist kuphrojekthi yakho yokugcina yokusebenzisa i-Libero (ebizwa nangokuthi iphrojekthi yesibili ye-Libero kuThebula 1-1).
2.1 Ukucushwa kwengxenye usebenzisa i-Libero (Buza Umbuzo)
Ngemva kokukhetha izingxenye okufanele zisetshenziswe ohlwini oludlule, yenza lezi zinyathelo ezilandelayo:

1. Dala iphrojekthi entsha ye-Libero (Ukucushwa Okuyisisekelo Nesizukulwane): Khetha Idivayisi Nomndeni oqondise kuyo idizayini yakho yokugcina.
2. Sebenzisa i-cores eyodwa noma ngaphezulu okukhulunywe ngakho Ekugelezeni Ngokwezifiso.
   a. Dala i-SmartDesign futhi ulungiselele umongo owufunayo futhi uwuqinise engxenyeni ye-SmartDesign.
   b. Nyusa zonke izikhonkwane zibe sezingeni eliphezulu.
   c. Khiqiza i-SmartDesign.
   d. Chofoza kabili ithuluzi Lokulingisa (noma yiziphi izinketho ze-Pre-Synthesis noma Post-synthesis noma I-Post-Layout) ukuze ucele isifanisi. Ungaphuma kusifanisi ngemuva kokuthi siceliwe. Lesi sinyathelo sakha sekulingisa filekuyadingeka kuphrojekthi yakho.

Ithiphu: Wena kufanele wenze lesi sinyathelo uma ufuna ukulingisa umklamo wakho ngaphandle kwe-Libero.
Ukuze uthole ulwazi olwengeziwe, bona i-Simulating Your Design.
e. Londoloza iphrojekthi yakho—lena iphrojekthi yakho yesithenjwa.
2.2 Izimpawu zengxenye (Buza Umbuzo)
Uma ukhiqiza izingxenye zakho, isethi ye files kukhiqizwa engxenyeni ngayinye. Umbiko we-Component Manifest uchaza ngesethi ye files ekhiqizwe futhi isetshenziswe esinyathelweni ngasinye esilandelayo (I-Synthesis, Simulation, i-Firmware Generation, njalonjalo). Lo mbiko ukunika izindawo zazo zonke ezikhiqiziwe files ezidingekayo ukuze uqhubeke nokugeleza Ngokwezifiso. Ungakwazi ukufinyelela i-manifest yengxenye endaweni Yemibiko: Chofoza okuthi Dizayina > Imibiko ukuze uvule ithebhu yemibiko. Kuthebhu yemibiko, ubona isethi ye-manifest.txt files (Ngaphezuview), eyodwa yengxenye ngayinye oyikhiqizile.
Ithiphu: Kumelwe usethe ingxenye noma imojuli njenge-'”root”' ukuze ubone i-manifest yengxenye file okuqukethwe kuthebhu ethi Imibiko.
Okunye, ungakwazi ukufinyelela umbiko ngamunye we-manifest files engxenyeni ngayinye eyinhloko ekhiqizwayo noma ingxenye ye-SmartDesign kusuka /ingxenye/umsebenzi/ / / _manifest.txt noma /ingxenye/umsebenzi/ / _manifest.txt. Ungakwazi futhi ukufinyelela i-manifest file okuqukethwe kwengxenye ngayinye okukhiqizwa kuthebhu entsha ye-Components ku-Libero, lapho i- file izindawo zishiwo mayelana nenkomba yephrojekthi.Gxila emibikweni elandelayo ye-Component Manifest:

• Uma ufake ama-cores ku-SmartDesign, funda le file _manifest.txt.
• Uma udale izingxenye zama-cores, funda le _manifest.txt.

Kufanele usebenzise yonke imibiko ye-Component Manifest esebenza kumklamo wakho. Okwesiboneloampfuthi, uma iphrojekthi yakho ine-SmartDesign enengxenye eyodwa noma ngaphezulu ewumongo efakwe kuyo futhi uhlose ukuzisebenzisa zonke ekwakhiweni kwakho kokugcina, kufanele ukhethe. fileezisohlwini lwemibiko ye-Component Manifest yazo zonke lezo zingxenye ukuze zisetshenziswe ekugelezeni komklamo wakho.
2.3 Ukutolika Okuvezwayo Files (Buza Umbuzo)
Uma uvula i-manifest yengxenye file, ubona izindlela eziya files kuphrojekthi yakho ye-Libero nezikhombi zokuthi ukwakheka kugeleza kuphi ukuze uzisebenzise. Ungase ubone izinhlobo ezilandelayo ze files ku-manifest file:

• Umthombo we-HDL files yawo wonke amathuluzi Okuhlanganiswa kanye Nokulingiswa
• Isikhuthazo files yawo wonke amathuluzi Wokulingisa
• Ukucindezela files

Okulandelayo yi-Component Manifest yengxenye eyinhloko ye-PolarFire.Uhlobo ngalunye lwe file iyadingeka phansi komfula ekugelezeni komklamo wakho. Izigaba ezilandelayo zichaza ukuhlanganiswa kwe files ukusuka ku-manifest ukuya ekugelezeni komklamo wakho.

Isizukulwane esicindezelayo (Buza Umbuzo)

Lapho wenza ukumisa nokukhiqiza, qinisekisa ukubhala/ukukhiqiza umkhawulo weSDC/PDC/NDC files ukuze idizayini iwadlulisele ku-Synthesis, Indawo-kanye-Umzila, kanye namathuluzi Okuqinisekisa Isikhathi.
Sebenzisa insiza ye-Deive Constraints ngaphandle kwemvelo ye-Libero ukuze ukhiqize izingqinamba esikhundleni sokuzibhala mathupha. Ukuze usebenzise insiza ye-Derive Constraint ngaphandle kwemvelo ye-Libero, kufanele:

• Nikeza nge-HDL yomsebenzisi, ingxenye ye-HDL, kanye nomkhawulo we-SDC wengxenye files
• Cacisa imojuli yezinga eliphezulu
• Cacisa indawo lapho ungenza khona umkhawulo osuselwe files

Imikhawulo yengxenye ye-SDC iyatholakala ngaphansi /ingxenye/umsebenzi/ / / umkhombandlela ngemva kokucushwa kwengxenye nokukhiqizwa.
Ukuze uthole imininingwane eyengeziwe yokuthi ungayenza kanjani imingcele yomklamo wakho, bheka I-Appendix C—Derive Constraints.

Ihlanganisa Idizayini Yakho (Buza Umbuzo)

Esinye sezici eziyinhloko Zokugeleza Ngokwezifiso ukukuvumela ukuthi usebenzise ukuhlanganisa okuvela eceleni
ithuluzi ngaphandle Libero. Ukugeleza ngokwezifiso kusekela ukusetshenziswa kwe-Synopsys SynplifyPro. Ukuze synthesize yakho
iphrojekthi, sebenzisa inqubo elandelayo:

1. Dala iphrojekthi entsha kuthuluzi lakho le-Synthesis, uqondise kumndeni wedivayisi efanayo, kufa, kanye nephakheji njengephrojekthi ye-Libero oyidalile.
   a. Ngenisa eyakho i-RTL files njengoba ujwayele ukwenza.
   b. Setha okukhiphayo kwe-Synthesis ukuthi kube Structural Verilog (.vm).
   Ithiphu: Isakhiwo I-Verilog (.vm) iyona kuphela ifomethi yokuphumayo esekelwayo esekelwe ku-PolarFire.
2. Ngenisa Ingxenye ye-HDL filekuphrojekthi yakho ye-Synthesis:
   a. Kumbiko weManifest Engxenye ngayinye: Kwenye ngayinye file ngaphansi komthombo we-HDL files kuwo wonke amathuluzi Okuhlanganiswa kanye Nokulingiswa, ngenisa ifayela le file kuphrojekthi yakho ye-Synthesis.
3. Ngenisa i file polarfire_syn_comps.v (uma usebenzisa i-Synopsy Synplify) kusuka
   Indawo yokufaka>/idatha/aPA5M kuphrojekthi yakho ye-Synthesis.
4. Ngenisa i-SDC eyakhiwe ngaphambilini file ngokusebenzisa ithuluzi le-Derived Constraint (bona Isithasiselo
   A—Sample SDC Constraints) kuthuluzi le-Synthesis. Lo mkhawulo file icindezela ithuluzi lokuhlanganiswa ukuze kufinyelelwe ekuvaleni isikhathi ngomzamo omncane kanye nokuphindaphinda kwedizayini okumbalwa.

Okubalulekile: 

• Uma uhlela ukusebenzisa okufanayo *.sdc file ukuphoqa Indawo-kanye-Umzila phakathi nesigaba sokuqaliswa komklamo, kufanele ungenise le *.sdc kuphrojekthi yokuhlanganisa. Lokhu okokuqinisekisa ukuthi akukho ukungafani kwegama lento yedizayini ohlwini lwenethi oluhlanganisiwe kanye nezingqinamba Zendawo Nomzila phakathi nesigaba sokusetshenziswa senqubo yokuklama. Uma ungafaki lokhu *.sdc file esinyathelweni se-Synthesis, uhlu lwenethikhi olukhiqizwe ku-Synthesis lungase lwehluleke isinyathelo seNdawo kanye Nomzila ngenxa yokungafani kwegama lento yomklamo.
  a. Ngenisa Izichasiso ze-Netlist *.ndc, uma zikhona, kuthuluzi le-Synthesis.
  b. Run Synthesis.
• Indawo yokukhishwa kwethuluzi lakho le-Synthesis inohlu lwenethiwekhi lwe-*.vm file eyenziwe post Synthesis. Kufanele ungenise uhlu lwe-net ku-Libero Implementation Project ukuze uqhubeke nenqubo yokuklama.

Ukulingisa Umklamo Wakho (Buza Umbuzo)

Ukuze ulingise umklamo wakho ngaphandle kwe-Libero (okungukuthi, usebenzisa indawo yakho yokulingisa nesifanisi), yenza lezi zinyathelo ezilandelayo:

1. Idizayini Files:
   a. Ukulingisa kwangaphambili kwe-Synthesis:
   • Ngenisa i-RTL yakho kuphrojekthi yakho yokulingisa.
   • Ngombiko wengxenye ngayinye yamaManifest.
   – Ngenisa ngayinye file ngaphansi komthombo we-HDL files yawo wonke amathuluzi e-Synthesis nawekulingisa kuphrojekthi yakho yokulingisa.
   • Hlanganisa lezi files ngokwemiyalo yesifanisi sakho.
   b. Ukulingisa kwe-post-synthesis:
   • Ngenisa i-post-synthesis yakho *.vm netlist (ekhiqizwe kokuthi Ukwenziwa Kwedizayini Yakho) kuphrojekthi yakho yokulingisa futhi uyihlanganise.
   c. Ukulingisa ngemuva kwesakhiwo:
   • Okokuqala, qedela ukusebenzisa umklamo wakho (bheka Ukusebenzisa Umklamo Wakho). Qinisekisa ukuthi iphrojekthi yakho yokugcina ye-Libero isesimweni sangemuva kokuhlelwa.
   • Chofoza kabili Khiqiza i-BackAnnotated Files efasiteleni le-Libero Design Flow. Ikhiqiza ezimbili files:
   /umklami/ / _ba.v/vhd /umklami/
   / _ba.sdf
   • Ngenisa zombili lezi files kuthuluzi lakho lokulingisa.
2. Isikhuthazo Nokumisa files:
   a. Ngombiko wesici ngasinye seManifests:
   • Kopisha konke files ngaphansi kwe-Stimulus Files kuzo zonke izigaba Zamathuluzi Okulingisa kumkhombandlela oyimpande wephrojekthi yakho Yokulingisa.
   b. Qinisekisa ukuthi noma iyiphi i-Tcl files ezinhlwini ezandulele (esinyathelweni sesi-2.a) zisetshenziswa kuqala, ngaphambi kokuqala kokulingisa.
   c. I-UPROM.mem: Uma usebenzisa umongo we-UPROM ekwakhiweni kwakho ngenketho Sebenzisa okuqukethwe ukuze ulingise okunikwe amandla iklayenti elilodwa noma amaningi okugcina idatha ofisa ukulingisa, kufanele usebenzise i-pa4rtupromgen esebenzisekayo (pa4rtupromgen.exe kumawindi) ukuze ukhiqize i-UPROM.mem file. I-pa4rtupromgen esebenzisekayo ithatha i-UPROM.cfg file njengokufakwayo ngombhalo we-Tcl file futhi ikhipha i-UPROM.mem file edingekayo ekulingiseni. Lokhu UPROM.mem file kufanele ikopishelwe kufolda yokulingisa ngaphambi kokuqaliswa kokulingisa. IsibampI-le ebonisa ukusetshenziswa kwe-pa4rtupromgen okusebenzisekayo kunikezwa ezinyathelweni ezilandelayo. I-UPROM.cfg file iyatholakala ohlwini lwemibhalo /ingxenye/umsebenzi/ / kuphrojekthi ye-Libero oyisebenzisele ukukhiqiza ingxenye ye-UPROM.
   d. snvm.mem: Uma usebenzisa umgogodla Wamasevisi Esistimu ekwakhiweni kwakho futhi ulungise ithebhu ye-sNVM kumongo ngenketho Sebenzisa okuqukethwe kokulingisa okunikwe amandla iklayenti elilodwa noma amaningi ofisa ukukulingisa, i-snvm.mem file ikhiqizwa ngokuzenzakalelayo ukuze
   uhla lwemibhalo /ingxenye/umsebenzi/ / kuphrojekthi ye-Libero oyisebenzisele ukukhiqiza ingxenye Yezinsizakalo Zesistimu. Lokhu snvm.mem file kufanele ikopishelwe kufolda yokulingisa ngaphambi kokuqaliswa kokulingisa.
3. Dala ifolda esebenzayo kanye nefolda engaphansi ebizwa ngokuthi isifaniso ngaphansi kwefolda esebenzayo.
   I-pa4rtupromgen esebenzisekayo ilindele ukuba khona kwefolda encane yokulingisa kufolda esebenzayo futhi umbhalo we-*.tcl ubekwe kufolda encane yokulingisa.
4. Kopisha i-UPROM.cfg file kusuka kuphrojekthi yokuqala ye-Libero eyenzelwe ukukhiqizwa kwengxenye kufolda esebenzayo.
5. Namathisela imiyalo elandelayo kusikripthi *.tcl bese usibeka kufolda yokulingisa edalwe esinyathelweni sesi-3.
   Sample *.tcl yamadivayisi we-PolarFire kanye ne-PolarFire Soc Family ukuze akhiqize i-URPOM.mem file
   kusuka ku-UPROM.cfg
   set_device -fam -fa -pkg
   set_input_cfg -indlela
   set_sim_mem -indlelaFile/UPROM.mem>
   gen_sim -use_init amanga
   Ukuze uthole igama elifanele langaphakathi ongalisebenzisa ku-die and package, bona i-*.prjx file yephrojekthi yokuqala ye-Libero (esetshenziselwa ukukhiqiza ingxenye).
   I-agumenti use_init kumelwe isethelwe kumanga.
   Sebenzisa umyalo othi set_sim_mem ukuze ucacise indlela eya kokuphumayo file UPROM.mem lokho
   okwenziwe ngesikhathi kusetshenziswa iskripthi file nge-pa4rtupromgen esebenzisekayo.
6. Emyalweni womyalo noma ku-terminal ye-cygwin, iya kumkhombandlela osebenzayo odalwe esinyathelweni sesi-3.
   Sebenzisa umyalo we-pa4rtupromgen ngenketho ye-script bese udlulisela kuyo umbhalo *.tcl odalwe esinyathelweni sangaphambilini.
   OkweWindows
   /designer/bin/pa4rtupromgen.exe \
   -script./simulation/ .tcl
   Okwe-Linux:
   /bin/pa4rtupromgen
   -script./simulation/ .tcl
7. Ngemva kokukhishwa ngempumelelo kwe-pa4rtupromgen esebenzisekayo, hlola ukuthi i-UPROM.mem file ikhiqizwa endaweni eshiwo kumyalo we-set_sim_mem kusikripthi se-*.tcl.
8. Ukuze ulingise i-sNVM, kopisha ifayela elithi snvm.mem file kusukela kuphrojekthi yakho yokuqala ye-Libero (esetshenziselwa ukumisa ingxenye) kufolda yokulingisa yezinga eliphezulu yephrojekthi yakho yokulingisa ukuze iqalise ukulingisa (ngaphandle kwe-Libero SoC). Ukuze ulingise okuqukethwe kwe-UPROM, kopisha i-UPROM.mem ekhiqiziwe file kufolda yokulingisa yezinga eliphezulu yephrojekthi yakho yokulingisa ukuze usebenzise ukulingisa (ngaphandle kwe-Libero SoC).

Okubalulekile: Ku lingisa ukusebenza kwe-SoC Components, landa imitapo yolwazi yokulingisa ehlanganiswe ngaphambili ye-PolarFire futhi uyingenise endaweni yakho yokulingisa njengoba kuchazwe lapha. Ukuze uthole imininingwane eyengeziwe, bheka I-Appendix B—Importing Simulation Libraries endaweni yokulingisa.

Ukusebenzisa Umklamo Wakho (Buza Umbuzo)

Ngemuva kokuqeda ukulingisa kwe-Synthesis kanye ne-Post-Synthesis endaweni yakho, kufanele usebenzise i-Libero futhi ukuze usebenzise umklamo wakho, usebenzise isikhathi nokuhlaziya amandla, futhi ukhiqize izinhlelo zakho. file.

1. Dala iphrojekthi entsha ye-Libero yokusetshenziswa ngokomzimba kanye nesakhiwo somklamo. Qinisekisa ukukhomba idivayisi efanayo njengakuphrojekthi yesithenjwa oyidalile Ekucushweni Kwengxenye.
2. Ngemva kokudala iphrojekthi, susa i-Synthesis ochungechungeni lwamathuluzi efasiteleni Lokugeleza Kwedizayini (Iphrojekthi > Izilungiselelo Zephrojekthi > Ukugeleza Kwedizayini > Susa Ukuthikha Vumela Ukuhlanganisa).
3.  Ngenisa i-post-synthesis yakho *.vm file kule phrojekthi, (File > Ngenisa > I-synthesized Verilog Netlist (VM)).
   Ithiphu: Kunconywa ukuthi udale isixhumanisi salokhu file, ukuze kuthi uma uhlanganisa kabusha umklamo wakho, i-Libero ihlala isebenzisa uhlu lwakamuva lwe-post-synthesis.
   a. Efasiteleni le-Design Hierarchy, qaphela igama lemojuli yempande.
4. Ngenisa izingqinamba kuphrojekthi ye-Libero. Sebenzisa Umphathi Wokukhawulela ukuze ungenise *.pdc/*.sdc/*.ndc izingqinamba.
   a. Ngenisa i-I/O *.pdc umkhawulo files (Umphathi Wezingqinamba > Izibaluli ze-I/O >Ngenisa).
   b. Ngenisa i-Floorplanning *.pdc umkhawulo files (Umphathi Wezingqinamba > Isihleli Sesitezi > Ngenisa).
   c. Ngenisa *.sdc umkhawulo wesikhathi files (Umphathi Wezingqinamba > Isikhathi > Ngenisa). Uma idizayini yakho inanoma yimaphi ama-cores abhalwe ku-Overview, qinisekisa ukuthi uyangenisa iSDC file okukhiqizwa ngokusebenzisa ithuluzi le-derive constraint.
   d. Ngenisa *.ndc umkhawulo files (Umphathi Wezingqinamba > Izibaluli ze-Netlist > Ngenisa).
5. Hlanganisa Izithiyo Files ukuklama amathuluzi.
   a. Vula Isiphathi Sokukhawulela (Phatha Izithibelo > Vula Imikhawulo Yokuphatha View).
   Thikha ibhokisi lokuhlola Indawo Nomzila Nokuqinisekisa Isikhathi eduze kwesivimbelo file ukumisa umkhawulo file kanye nokuhlangana kwamathuluzi. Hlobanisa i-*.pdc isithiyo se-Place-andRoute kanye ne-*.sdc kukho kokubili Indawo-Nomzila kanye Nokuqinisekiswa Kwesikhathi. Hlanganisa i-*.ndc file ukuze Uhlanganise I-Netlist.
   Ithiphu: Uma Indawo kanye Nomzila wehluleka nalokhu *.sdc umkhawulo file, bese ungenisa yona le *.sdc file ukuhlanganisa nokusebenzisa kabusha ukuhlanganisa.
6. Chofoza okuthi Hlanganisa i-Netlist bese ubeka Indawo Nomzila ukuze uqedele isinyathelo sesakhiwo.
7. Ithuluzi Ledatha Yokuqalisa Idizayini Nezinkumbulo likuvumela ukuthi uqalise amabhulokhi edizayini, afana ne-LSRAM, µSRAM, XCVR (ama-transceivers), ne-PCIe usebenzisa idatha egcinwe ku-µPROM, i-sNVM, noma imemori yangaphandle ye-SPI Flash yesitoreji. Ithuluzi linamathebhu alandelayo okuchaza ukucaciswa kokulandelana kokuqaliswa komklamo, ukucaciswa kwamaklayenti okuqalisa, amaklayenti edatha yomsebenzisi.
   - Ithebhu yokuqalisa idizayini
   – µPROM ithebhu
   - ithebhu ye-sNVM
   - Ithebhu ye-SPI Flash
   - Ithebhu ye-RAM yendwangu
   Sebenzisa amathebhu ethuluzini ukuze ulungiselele idatha yokuqalisa idizayini nezinkumbulo.Ngemva kokuqeda ukumisa, yenza lezi zinyathelo ezilandelayo ukuhlela idatha yokuqalisa:
   • Khiqiza amaklayenti okuqalisa
   • Khiqiza noma thumela i-bitstream
   • Hlela idivayisi
   Ukuze uthole imininingwane enemininingwane yokuthi ungalisebenzisa kanjani leli thuluzi, bheka Umhlahlandlela Womsebenzisi Wokugeleza Kwedizayini ye-Libero SoC. Ukuze uthole ulwazi olwengeziwe ngemiyalo ye-Tcl esetshenziselwa ukulungisa amathebhu ahlukahlukene ethuluzini futhi ucacise ukucushwa kwememori files (*.cfg), bona I-Tcl Commands Reference Guide.
8. Khiqiza i-Programming File kusuka kule phrojekthi futhi uyisebenzise ukuhlela i-FPGA yakho.

Isithasiselo A—SampI-SDC Constraints (Buza Umbuzo

I-Libero SoC ikhiqiza izithiyo zesikhathi se-SDC kuma-cores athile we-IP, njenge-CCC, i-OSC, i-Transceiver nokunye. Ukwedlula imikhawulo ye-SDC kumathuluzi okuklama kukhulisa ithuba lokuvalwa kwesikhathi sokuhlangana ngomzamo omncane kanye nokuphindaphinda kwedizayini okumbalwa. Indlela egcwele ye-hierarchical evela esibonelweni sezinga eliphezulu inikezwa zonke izinto zedizayini ezibalulwe kwimikhawulo.
7.1 Izingqinamba Zesikhathi Se-SDC (Buza Umbuzo)
Kuphrojekthi yereferensi eyinhloko ye-Libero IP, lo mkhawulo wezinga eliphezulu we-SDC file itholakala kokuthi Umphathi Wokukhawulela (Ukugeleza Komklamo > Vula Ukucindezela Ukuphatha View >Isikhathi > Thola Izingqinamba).
Okubalulekile: Bheka lokhu file ukuze usethe imikhawulo ye-SDC uma idizayini yakho iqukethe i-CCC, i-OSC, i-Transceiver, nezinye izingxenye. Lungisa indlela egcwele yokulandelana kwezigaba, uma kudingekile, ukuze ifane nesigaba sakho sokuklama noma usebenzise insiza ye-Derive_Constraints kanye nezinyathelo ku-Appendix C—Thola Izingqinamba ezingeni lengxenye ye-SDC file.
Londoloza i- file egameni elehlukile bese ungenisa iSDC file ethuluzini lokuhlanganisa, Ithuluzi Lendawo Nomzila, kanye Nokuqinisekiswa Kwesikhathi, njenganoma yimuphi omunye umkhawulo we-SDC files.
7.1.1 Derived SDC File (Buza Umbuzo)
#Lokhu file yakhiwe ngokusekelwe kulo mthombo we-SDC olandelayo files:
# /drive/icicle_kit_ref_des/icicle-kit-reference-design-master/MPFS_ICICLE/component/work/
PF_CCC_C0/PF_CCC_C0_0/PF_CCC_C0_PF_CCC_C0_0_PF_CCC.sdc
# /drive/icicle_kit_ref_des/icicle-kit-reference-design-master/MPFS_ICICLE/component/work/
CLK_DIV/CLK_DIV_0/CLK_DIV_CLK_DIV_0_PF_CLK_DIV.sdc
# /drive/icicle_kit_ref_des/icicle-kit-reference-design-master/MPFS_ICICLE/component/work/
TRANSMIT_PLL/TRANSMIT_PLL_0/TRANSMIT_PLL_TRANSMIT_PLL_0_PF_TX_PLL.sdc
# /drive/icicle_kit_ref_des/icicle-kit-reference-design-master/MPFS_ICICLE/component/work/
DMA_INITIATOR/DMA_INITIATOR_0/DMA_INITIATOR.sdc
# /drive/icicle_kit_ref_des/icicle-kit-reference-design-master/MPFS_ICICLE/component/work/
FIC0_INITIATOR/FIC0_INITIATOR_0/FIC0_INITIATOR.sdc
# /drive/icicle_kit_ref_des/icicle-kit-reference-design-master/MPFS_ICICLE/component/work/
ICICLE_MSS/ICICLE_MSS.sdc
# /drive/icicle_kit_ref_des/icicle-kit-reference-design-master/MPFS_ICICLE/component/work/
PF_PCIE_C0/PF_PCIE_C0_0/PF_PCIE_C0_PF_PCIE_C0_0_PF_PCIE.sdc
# /drive/icicle_kit_ref_des/icicle-kit-reference-design-master/MPFS_ICICLE/component/work/
PCIE_INITIATOR/PCIE_INITIATOR_0/PCIE_INITIATOR.sdc
# /drive/aPA5M/cores/constraints/osc_rc160mhz.sdc
# *** Noma yiziphi izinguquko kulokhu file izolahleka uma izithiyo ezitholiwe ziphinda ziqaliswe. ***
create_clock -name {CLOCKS_AND_RESETS_inst_0/OSCILLATOR_160MHz_inst_0/OSCILLATOR_160MHz_0/
I_OSC_160/CLK} -inkathi 6.25
[ get_pins {CLOCKS_AND_RESETS_inst_0/OSCILLATOR_160MHz_inst_0/OSCILLATOR_160MHz_0/
I_OSC_160/CLK } ] create_clock -name {REF_CLK_PAD_P} -inkathi 10 [ get_ports { REF_CLK_PAD_P } ] create_clock -name {CLOCKS_AND_RESETS_inst_0/TRANSMIT_PLL_0/TRANSMIT_ist_PLL
DIV_CLK} -inkathi 8
[ get_pins { CLOCKS_AND_RESETS_inst_0/TRANSMIT_PLL_0/TRANSMIT_PLL_0/txpll_isnt_0/DIV_CLK } ] create_generated_clock -name {CLOCKS_AND_RESETS_inst_0/CCC_FIC_x_CCC_CLK_CLL_0_CLL_0
OUT0} -phindaphinda_nga-25 -hlukanisa_nga-32 -umthombo
[ get_pins { CLOCKS_AND_RESETS_inst_0/CCC_FIC_x_CLK/PF_CCC_C0_0/pll_inst_0/REF_CLK_0 } ] -isigaba 0
[ get_pins { CLOCKS_AND_RESETS_inst_0/CCC_FIC_x_CLK/PF_CCC_C0_0/pll_inst_0/OUT0 } ] create_generated_clock -name {CLOCKS_AND_RESETS_inst_0/CCC_FIC_x_CLK_CLL_Cll_0CLL_Cll_0CLL_
OUT1} -phindaphinda_nga-25 -hlukanisa_nga-32 -umthombo
[ get_pins { CLOCKS_AND_RESETS_inst_0/CCC_FIC_x_CLK/PF_CCC_C0_0/pll_inst_0/REF_CLK_0 } ] -isigaba 0
[ get_pins { CLOCKS_AND_RESETS_inst_0/CCC_FIC_x_CLK/PF_CCC_C0_0/pll_inst_0/OUT1 } ] create_generated_clock -name {CLOCKS_AND_RESETS_inst_0/CCC_FIC_x_CLK_CLL_Cll_0CLL_Cll_0CLL_
OUT2} -phindaphinda_nga-25 -hlukanisa_nga-32 -umthombo
[ get_pins { CLOCKS_AND_RESETS_inst_0/CCC_FIC_x_CLK/PF_CCC_C0_0/pll_inst_0/REF_CLK_0 } ] -isigaba 0
[ get_pins { CLOCKS_AND_RESETS_inst_0/CCC_FIC_x_CLK/PF_CCC_C0_0/pll_inst_0/OUT2 } ] create_generated_clock -name {CLOCKS_AND_RESETS_inst_0/CCC_FIC_x_CLK_CLL_Cll_0CLL_Cll_0CLL_
OUT3} -phindaphinda_nga-25 -hlukanisa_nga-64 -umthombo
[ get_pins { CLOCKS_AND_RESETS_inst_0/CCC_FIC_x_CLK/PF_CCC_C0_0/pll_inst_0/REF_CLK_0 } ] -isigaba 0
[ get_pins { CLOCKS_AND_RESETS_inst_0/CCC_FIC_x_CLK/PF_CCC_C0_0/pll_inst_0/OUT3 } ] create_generated_clock -name {CLOCKS_AND_RESETS_inst_0/CLK_160MHz_to_80MHz/CLK_CD_0_CD_XNUMX
Y_DIV} -hlukanisa_ngomthombo ongu-2
[ thola_amaphini { CLOCKS_AND_RESETS_inst_0/CLK_160MHz_to_CLK_80MHz/CLK_DIV_0/I_CD/A } ] [ thola_amaphini { CLOCKS_AND_RESETS_inst_0/CLK_160MHz_to_CLK_80MHz_DIV_CD_CD_CD_CD_CD_CLK_ set_false_path -through [ get_nets { DMA_INITIATOR_inst_0/ARESETN* } ] set_false_path -from [ get_cells { DMA_INITIATOR_inst_0/*/SlvConvertor_loop[*].slvcnv/slvCDC/
genblk1*/rdGrayCounter*/cntGray* } ] -kuya [ get_cells { DMA_INITIATOR_inst_0/*/SlvConvertor_loop[*].slvcnv/slvCDC/genblk1*/
rdPtr_s1* } ] set_false_path -from [ get_cells { DMA_INITIATOR_inst_0/*/SlvConvertor_loop[*].slvcnv/slvCDC/
genblk1*/wrGrayCounter*/cntGray* } ] -kuya [ thola_amaseli {DMA_INITIATOR_inst_0/*/SlvConvertor_loop[*].slvcnv/slvCDC/genblk1*/
wrPtr_s1* } ] set_false_path -through [ get_nets { FIC0_INITIATOR_inst_0/ARESETN* } ] set_false_path -to [ get_pins {PCIE/PF_PCIE_C0_0/PCIE_1/INTERRUPT[0] PCIE/PF_PC_0PF_
PCIE_1/INTERRUPT[1] PCIE/PF_PCIE_C0_0/PCIE_1/INTERRUPT[2] PCIE/PF_PCIE_C0_0/PCIE_1/
INTERRUPT[3] PCIE/PF_PCIE_C0_0/PCIE_1/INTERRUPT[4] PCIE/PF_PCIE_C0_0/PCIE_1/INTERRUPT[5] PCIE/PF_PCIE_C0_0/PCIE_1/INTERRUPT[6] PCIE/PF_PCIE_C0_0/PCIE_1/INTERRUPT[7] PCIE/PF_PCIE_C0_0/
I-PCIE_1/WAKEREQ PCIE/PF_PCIE_C0_0/PCIE_1/MPERST_N } ] set_false_path -from [ get_pins {PCIE/PF_PCIE_C0_0/PCIE_1/TL_CLK } ] set_false_path -through [get_stNTIATOR] Isithasiselo B—Ukungenisa Imitapo yolwazi yokulingisa endaweni yokulingisa (Buza Umbuzo)
Isifanisi esizenzakalelayo sokulingiswa kwe-RTL ne-Libero SoC yi-ModelSim ME Pro.
Imitapo yolwazi ehlanganiswe ngaphambilini yesifanisi esizenzakalelayo iyatholakala ngokufakwa kwe-Libero kumkhombandlela /Designer/lib/modelsimpro/precompiled/vlog for® imindeni esekelwe. I-Libero SoC futhi isekela ezinye izinhlelo zokulingisa ezivela eceleni ze-ModelSim, Questasim, VCS, Xcelium
, I-HDL esebenzayo, ne-Riviera Pro. Landa imitapo yolwazi ehlanganiswe ngaphambilini elandelanayo kusuka I-Libero SoC v12.0 nakamuva ngokusekelwe ku-simulator kanye nenguqulo yayo.
Ngokufana nemvelo ye-Libero, run.do file kumele idalwe ukuze kusetshenziswe ukulingisa ngaphandle kwe-Libero.
Dala i-run.do elula file enemiyalo yokusungula umtapo wolwazi ukuze uthole imiphumela yokuhlanganisa, imephu yelabhulali, ukuhlanganiswa, nokulingisa. Landela izinyathelo ukuze udale i-run.do eyisisekelo file.

1. Dala umtapo wolwazi ukuze ugcine imiphumela yokuhlanganisa usebenzisa i-vlib command vlib presynth.
2. Imephu yegama lomtapo wezincwadi eqondiswe kuhla lwemibhalo oluhlanganiswe ngaphambilini usebenzisa i-vmap command vmap .
3. Hlanganisa umthombo files—sebenzisa imiyalo yesihlanganisi yolimi oluthile ukuze uhlanganise umklamo files kumkhombandlela osebenzayo.
   – vlog ye-.v/.sv
   – i-vcom ye-.vhd
4. Layisha idizayini yokulingisa usebenzisa umyalo we-vsim ngokucacisa igama lanoma iyiphi imojuli yezinga eliphezulu.
5. Lingisa umklamo usebenzisa run command.
   Ngemva kokulayisha umklamo, isikhathi sokulingisa sisethelwe ku-zero, futhi ungafaka umyalo wokugijima ukuze uqale ukulingisa.
   Ewindini lokuloba lesifanisi, sebenzisa i-run.do file njengoba run.do sebenzisa ukulingisa. Sample run.do file Ngokulandelayo.

setha buthule i-ACTELLIBNAME PolarFire setha buthule i-PROJECT_DIR “W:/Test/basic_test” uma
{[file kukhona i-presynth/_info]} {echo “INFO: I-presynth yelabhulali yokulingisa ikhona” } okunye
{ file delete -force presynth vlib presynth } vmap presynth presynth vmap PolarFire
“X:/Libero/Designer/lib/modelsimpro/precompiled/vlog/PolarFire” vlog -sv -work presynth
“${PROJECT_DIR}/hdl/top.v” vlog “+incdir+${PROJECT_DIR}/stimulus” -sv -work presynth “$
{PROJECT_DIR}/stimulus/tb.v” vsim -L PolarFire -L presynth -t 1ps presynth.tb add wave /tb/*
sebenzisa i-1000ns log /tb/* phuma

Isithasiselo C—Izingqinamba Zokuthola (Buza Umbuzo)

Lesi sithasiselo sichaza imiyalo ye-Derive Constraints Tcl.
9.1 I-Deive Constraints Tcl Commands (Buza Umbuzo)
Isisetshenziswa se-derive_constraints sikusiza ukuthi uthole izithiyo ku-RTL noma kusihleli esingaphandle kwendawo yokuklama ye-Libero SoC. Ukuze ukhiqize imikhawulo yomklamo wakho, udinga i-HDL yomsebenzisi, i-Component HDL, kanye ne-Component Constraints files. Imikhawulo yengxenye ye-SDC files ayatholakala ngaphansi /ingxenye/umsebenzi/ / / umkhombandlela ngemva kokucushwa kwengxenye nokukhiqizwa.
Umkhawulo wengxenye ngayinye file iqukethe umyalo we-set_component tcl (icacisa igama lengxenye) kanye nohlu lwezingqinamba ezikhiqizwa ngemva kokucushwa. Izithiyo zikhiqizwa ngokusekelwe ekucushweni futhi ziqondene nengxenye ngayinye.
Exampngo 9-1. Umkhawulo Wengxenye File okwePF_CCC Core
Nansi i-example yomkhawulo wengxenye file kwe-PF_CCC core:
set_component PF_CCC_C0_PF_CCC_C0_0_PF_CCC
# I-Microchip Corp.
# Idethi: 2021-Oct-26 04:36:00
# Iwashi eliyisisekelo le-PLL #0
create_clock -period 10 [ get_pins { pll_inst_0/REF_CLK_0 } ] create_generated_clock -divide_by 1 -source [ get_pins { pll_inst_0/
REF_CLK_0 } ] -isigaba 0 [ get_pins { pll_inst_0/OUT0 } ] Lapha, ukudala_iwashi kanye newashi_elikhiqiziwe_lewashi kuyizingqinamba zewashi lereferensi nelokukhipha ngokulandelanayo, ezikhiqizwa ngokusekelwe ekucushweni.
9.1.1 Ukusebenza ne-derive_constraints Utility (Buza Umbuzo)
Thola izithiyo zinqamula ekwakhiweni futhi unikeze izithiyo ezintsha zesibonelo ngasinye sengxenye ngokusekelwe engxenyeni ye-SDC ehlinzekwe ngaphambilini. files. Kumawashi ayisethenjwa e-CCC, isakaza emuva ngomklamo ukuze kutholwe umthombo wewashi lesithenjwa. Uma umthombo kuyi-I/O, umkhawulo wewashi lesithenjwa uzosethwa ku-I/O. Uma kungumkhiqizo we-CCC noma omunye umthombo wewashi (ngokwesiboneloample, Transceiver, oscillator), isebenzisa iwashi elisuka kwenye ingxenye futhi ibike isexwayiso uma izikhawu zingafani. Imikhawulo ye-Derive izophinde yabe izithiyo kwamanye ama-macros njengama-on-chip oscillator uma unazo ku-RTL yakho.
Ukuze usebenzise i-derive_constraints insiza, kufanele unikeze i-.tcl file impikiswano yomugqa womyalo ngolwazi olulandelayo ngokulandelana okucacisiwe.

1. Cacisa ulwazi lwedivayisi usebenzisa ulwazi olukusigaba set_device.
2. Cacisa indlela eya ku-RTL fileusebenzisa ulwazi olusesigabeni esithi read_verilog noma read_vhdl.
3. Setha imojuli yezinga eliphezulu usebenzisa ulwazi olukusigaba set_top_level.
4. Cacisa indlela eya engxenyeni ye-SDC files sisebenzisa imininingwane esesigabeni esithi read_sdc noma read_ndc.
5. Yenza i- files sisebenzisa ulwazi olusesigabeni i-derive_constraints.
6.  Cacisa indlela eya kuzithiyo ezitholwe yi-SDC file usebenzisa ulwazi olusesigabeni bhala_sdc noma bhala_pdc noma bhala_ndc.

Exampibe 9-2. Ukwenziwa Nokuqukethwe kwe-derive.tcl File
Okulandelayo yi-example-agumenti yomugqa womyalo ukuze usebenzise i-derive_constraints utility.
$ /bin{64}/derive_constraints deive.tcl
Okuqukethwe kwe-derive.tcl file:
# Ulwazi lwedivayisi
set_device -umndeni PolarFire -die MPF100T -speed -1
#RTL files
read_verilog -mode system_verilog project/component/work/txpll0/
txpll0_txpll0_0_PF_TX_PLL.v
read_verilog -mode system_verilog {project/component/work/txpll0/txpll0.v}
read_verilog -mode system_verilog {project/component/work/xcvr0/I_XCVR/
xcvr0_I_XCVR_PF_XCVR.v}
read_verilog -mode system_verilog {project/component/work/xcvr0/xcvr0.v}
read_vhdl -mode vhdl_2008 {project/hdl/xcvr1.vhd}
#Ingxenye ye-SDC files
set_top_level {xcvr1}
read_sdc -component {project/component/work/txpll0/txpll0_0/
txpll0_txpll0_0_PF_TX_PLL.sdc}
read_sdc -component {project/component/work/xcvr0/I_XCVR/
xcvr0_I_XCVR_PF_XCVR.sdc}
#Sebenzisa i-derive_constraint command
thola_izingqinamba
#SDC/PDC/NDC umphumela files
write_sdc {project/constraint/xcvr1_derived_constraints.sdc}
write_pdc {project/constraint/fp/xcvr1_derived_constraints.pdc}
9.1.2 set_device (Buza Umbuzo)
Incazelo
Cacisa igama lomndeni, igama lokufa, kanye nebanga lesivinini.
set_device -umndeni -fa -isivinini
Izingxabano

Ipharamitha	Uhlobo	Incazelo
- umndeni	Intambo	Cacisa igama lomndeni. Amanani angenzeka i-PolarFire®, i-PolarFire SoC.
-fa	Intambo	Cacisa igama ledayi.
-isivinini	Intambo	Cacisa isivinini sedivayisi. Amanani angaba khona yi-STD noma -1.

Buyisela Uhlobo	Incazelo
0	Umyalo uphumelele.
1	Umyalo wehlulekile. Kunephutha. Ungabona umlayezo wephutha kukhonsoli.

Uhlu lwamaphutha

Ikhodi Yephutha	Umlayezo Wephutha	Incazelo
I-ERR0023	Ipharamitha edingekayo—i-die ayikho	Inketho yokufa iyisibopho futhi kufanele icaciswe.
I-ERR0005	Ifa elingaziwa elithi 'MPF30'	Inani le--die option alilungile. Bona uhlu olungaba khona lwamanani encazelweni yenketho.
I-ERR0023	Ipharamitha—i-die ayinani	Inketho yokufa icaciswe ngaphandle kwevelu.
I-ERR0023	Ipharamitha edingekayo—umndeni awukho	Inketho yomndeni iyisibopho futhi kufanele icaciswe.
I-ERR0004	Umndeni ongaziwa we-'PolarFire®'	Inketho yomndeni ayilungile. Bona uhlu olungaba khona lwamanani encazelweni yenketho.

………… waqhubeka
Ikhodi Yephutha	Umlayezo Wephutha	Incazelo
I-ERR0023	Ipharamitha—umndeni awunalo inani	Inketho yomndeni icaciswe ngaphandle kwenani.
I-ERR0023	Ipharamitha edingekayo—isivinini alikho	Inketho yesivinini iyisibopho futhi kufanele icaciswe.
I-ERR0007	Isivinini esingaziwa' '	Inketho yesivinini ayilungile. Bona uhlu olungaba khona lwamanani encazelweni yenketho.
I-ERR0023	Ipharamitha—isivinini asinalo inani	Inketho yesivinini icaciswe ngaphandle kwevelu.

Example
set_device -family {PolarFire} -die {MPF300T_ES} -speed -1
set_device -family SmartFusion 2 -die M2S090T -speed -1
9.1.3 read_verilog (Buza Umbuzo)
Incazelo
Funda i-Verilog file usebenzisa i-Verific.
funda_verilog [-lib ] [-imodi ]fileigama>
Izingxabano

Ipharamitha	Uhlobo	Incazelo
-lib	Intambo	Cacisa umtapo wolwazi oqukethe amamojula azokwengezwa kulabhulali.
-imodi	Intambo	Cacisa izinga le-Verilog. Amanani angaba khona yi-verilog_95, verilog_2k, system_verilog_2005, system_verilog_2009, system_verilog, verilog_ams, verilog_psl, system_verilog_mfcu. Amanani awazweli. Okuzenzakalelayo yi-verilog_2k.
fileigama	Intambo	I-Verilog file igama.

Buyisela Uhlobo	Incazelo
0	Umyalo uphumelele.
1	Umyalo wehlulekile. Kunephutha. Ungabona umlayezo wephutha kukhonsoli.

Uhlu lwamaphutha

Ikhodi Yephutha	Umlayezo Wephutha	Incazelo
I-ERR0023	Ipharamitha—i-lib ayinalo inani	Inketho ye-lib icaciswe ngaphandle kwevelu.
I-ERR0023	Ipharamitha—imodi ayinalo inani	Inketho yemodi icaciswe ngaphandle kwenani.
I-ERR0015	Imodi engaziwa ' '	Imodi ye-verilog eshiwo ayaziwa. Bona uhlu lwemodi ye-verilog engenzeka encazelweni yenketho yemodi.
I-ERR0023	Ipharamitha edingekayo file igama alikho	Ayikho i-verilog file indlela inikezwa.
I-ERR0016	Yehlulekile ngenxa yomhlahleli we-Verific	Iphutha le-syntax ku-verilog file. Umhlahleli we-Verific ungabonwa kukhonsoli engenhla komlayezo wephutha.
I-ERR0012	set_device ayibizwa	Ulwazi lwedivayisi alucacisiwe. Sebenzisa umyalo we-set_device ukuchaza idivayisi.

Example
read_verilog -mode system_verilog {component/work/top/top.v}
read_verilog -mode system_verilog_mfcu design.v
9.1.4 funda_vhdl (Buza Umbuzo)
Incazelo
Engeza i-VHDL file ohlwini lwe-VHDL files.
funda_vhdl [-lib ] [-imodi ]fileigama>
Izingxabano

Ipharamitha	Uhlobo	Incazelo
-lib	—	Cacisa umtapo wolwazi okufanele kwengezwe kuwo okuqukethwe.
-imodi	—	Icacisa izinga le-VHDL. Okuzenzakalelayo yi-VHDL_93. Amanani angaba khona ngu-vhdl_93, vhdl_87, vhdl_2k, vhdl_2008, vhdl_psl. Amanani awazweli.
fileigama	—	I-VHDL file igama.

Buyisela Uhlobo	Incazelo
0	Umyalo uphumelele.
1	Umyalo wehlulekile. Kunephutha. Ungabona umlayezo wephutha kukhonsoli.

Uhlu lwamaphutha

Ikhodi Yephutha	Umlayezo Wephutha	Incazelo
I-ERR0023	Ipharamitha—i-lib ayinalo inani	Inketho ye-lib icaciswe ngaphandle kwevelu.
I-ERR0023	Ipharamitha—imodi ayinalo inani	Inketho yemodi icaciswe ngaphandle kwenani.
I-ERR0018	Imodi engaziwa ' '	Imodi ye-VHDL eshiwo ayaziwa. Bona uhlu lwemodi ye-VHDL engenzeka encazelweni yenketho yemodi.
I-ERR0023	Ipharamitha edingekayo file igama alikho	Ayikho i-VHDL file indlela inikezwa.
I-ERR0019	Ayikwazi ukubhalisa invalid_path.v file	I-VHDL ecacisiwe file ayikho noma ayinazo izimvume zokufunda.
I-ERR0012	set_device ayibizwa	Ulwazi lwedivayisi alucacisiwe. Sebenzisa umyalo we-set_device ukuchaza idivayisi.

Example
read_vhdl -mode vhdl_2008 osc2dfn.vhd
read_vhdl {hdl/top.vhd}
9.1.5 set_top_level (Buza Umbuzo)
Incazelo
Cacisa igama lemojuli yezinga eliphezulu ku-RTL.
set_top_level [-lib ]
Izingxabano

Ipharamitha	Uhlobo	Incazelo
-lib	Intambo	Umtapo wolwazi wokusesha imojuli yezinga eliphezulu noma ibhizinisi (Ongakukhetha).
igama	Intambo	Imojuli yezinga eliphezulu noma igama lebhizinisi.

Buyisela Uhlobo	Incazelo
0	Umyalo uphumelele.
1	Umyalo wehlulekile. Kunephutha. Ungabona umlayezo wephutha kukhonsoli.

Uhlu lwamaphutha

Ikhodi Yephutha	Umlayezo Wephutha	Incazelo
I-ERR0023	Izinga eliphezulu lepharamitha elidingekayo alikho	Inketho yezinga eliphezulu iphoqelekile futhi kufanele icaciswe.
I-ERR0023	Ipharamitha—i-lib ayinalo inani	Inketho ye-lib icaciswe ngaphandle kwamanani.
I-ERR0014	Ayikwazi ukuthola izinga eliphezulu emtatsheni wezincwadi	Imojuli eshiwo yezinga eliphezulu ayichazwanga kulabhulali enikeziwe. Ukuze ulungise leli phutha, imojuli ephezulu noma igama lelabhulali kufanele lilungiswe.
I-ERR0017	Ukuchaza kabanzi kuhlulekile	Iphutha kunqubo yokuchaza i-RTL. Umlayezo wephutha ungabonwa kusuka ku-console.

Example
set_top_level {phezulu}
set_top_level -lib hdl phezulu
9.1.6 read_sdc (Buza Umbuzo)
Incazelo
Funda i-SDC file kusizindalwazi sengxenye.
funda_sdc -ingxenyefileigama>
Izingxabano

Ipharamitha	Uhlobo	Incazelo
-ingxenye	—	Leli ifulegi eliyisibopho lomyalo we-read_sdc lapho sithola imingcele.
fileigama	Intambo	Indlela eya ku-SDC file.

Buyisela Uhlobo	Incazelo
0	Umyalo uphumelele.
1	Umyalo wehlulekile. Kunephutha. Ungabona umlayezo wephutha kukhonsoli.

Uhlu lwamaphutha

Ikhodi Yephutha	Umlayezo Wephutha	Incazelo
I-ERR0023	Ipharamitha edingekayo file igama alikho.	Inketho eyisibopho file igama alicacisiwe.
I-ERR0000	I-SDC file <file_indlela> ayifundeki.	I-SDC eshiwo file ayinazo izimvume zokufunda.
I-ERR0001	Ayikwazi ukuvulafile_indlela> file.	I-SDC file akekho. Indlela kumele ilungiswe.
I-ERR0008	Umyalo we-set_component awukhofile_indlela> file	Ingxenye eshiwo ye-SDC file ayicacisi ingxenye.

Ikhodi Yephutha	Umlayezo Wephutha	Incazelo
I-ERR0009	<List of errors from sdc file>	I-SDC file iqukethe imiyalo ye-sdc engalungile. Okwesiboneloample, uma kunephutha ku-set_multicycle_path constraint: Iphutha ngenkathi kufakwa umyalo read_sdc: infile_indlela> file: Iphutha kumyalo set_multicycle_path: Ipharamitha engaziwa [get_cells {reg_a}].

Example
read_sdc -component {./component/work/ccc0/ccc0_0/ccc0_ccc0_0_PF_CCC.sdc}
9.1.7 funda_ndc (Buza Umbuzo)
Incazelo
Funda i-NDC file kusizindalwazi sengxenye.
funda_ndc -ingxenyefileigama>
Izingxabano

Ipharamitha	Uhlobo	Incazelo
-ingxenye	—	Leli ifulegi eliyisibopho lomyalo we-read_ndc lapho sithola imikhawulo.
fileigama	Intambo	Indlela eya ku-NDC file.

Buyisela Uhlobo	Incazelo
0	Umyalo uphumelele.
1	Umyalo wehlulekile. Kunephutha. Ungabona umlayezo wephutha kukhonsoli.

Uhlu lwamaphutha

Ikhodi Yephutha	Umlayezo Wephutha	Incazelo
I-ERR0001	Ayikwazi ukuvulafile_indlela> file	I-NDC file akekho. Indlela kumele ilungiswe.
I-ERR0023	Ipharamitha edingekayo—AtclParamO_ ayikho.	Inketho eyisibopho fileigama alicacisiwe.
I-ERR0023	Ipharamitha edingekayo—ingxenye ayikho.	Inketho yengxenye iyisibopho futhi kufanele icaciswe.
I-ERR0000	NDC file 'file_path>' ayifundeki.	I-NDC eshiwo file ayinazo izimvume zokufunda.

Example
read_ndc -component {component/work/ccc1/ccc1_0/ccc_comp.ndc}
9.1.8 i-derive_constraints (Buza Umbuzo)
Incazelo
Qinisekisa ingxenye ye-SDC files kusizindalwazi sezinga lokuklama.
thola_izingqinamba
Izingxabano

Buyisela Uhlobo	Incazelo
0	Umyalo uphumelele.
1	Umyalo wehlulekile. Kunephutha. Ungabona umlayezo wephutha kukhonsoli.

Uhlu lwamaphutha

Ikhodi Yephutha	Umlayezo Wephutha	Incazelo
I-ERR0013	Izinga eliphezulu alichazwanga	Lokhu kusho ukuthi imojuli yezinga eliphezulu noma ibhizinisi alicacisiwe. Ukuze ulungise le kholi, khipha ifayela set_top_level umyalo ngaphambi komyalo we-derive_constraints.

Example
thola_izingqinamba
9.1.9 bhala_sdc (Buza Umbuzo)
Incazelo
Ubhala umgoqo file ngefomethi ye-SDC.
bhala_sdcfileigama>
Izingxabano

Ipharamitha	Uhlobo	Incazelo
<fileigama>	Intambo	Indlela eya ku-SDC file izokwenziwa. Lena inketho eyisibopho. Uma i file ikhona, izosulwa.

Buyisela Uhlobo	Incazelo
0	Umyalo uphumelele.
1	Umyalo wehlulekile. Kunephutha. Ungabona umlayezo wephutha kukhonsoli.

Uhlu lwamaphutha

Ikhodi Yephutha	Umlayezo Wephutha	Incazelo
I-ERR0003	Ayikwazi ukuvulafile indlela> file.	File indlela ayilungile. Hlola ukuthi uhla lwemibhalo lomzali lukhona yini.
I-ERR0002	I-SDC file 'file path>' ayibhaleki.	I-SDC eshiwo file ayinayo imvume yokubhala.
I-ERR0023	Ipharamitha edingekayo file igama alikho.	I-SDC file indlela iyinketho eyisibopho futhi kufanele icaciswe.

Example
write_sdc “derived.sdc”
9.1.10 bhala_pdc (Buza Umbuzo)
Incazelo
Ubhala izingqinamba zomzimba (Thola Izingqinamba kuphela).
bhala_pdcfileigama>
Izingxabano

Ipharamitha	Uhlobo	Incazelo
<fileigama>	Intambo	Indlela eya ku-PDC file izokwenziwa. Lena inketho eyisibopho. Uma i file indlela ikhona, izosulwa.

Buyisela Uhlobo	Incazelo
0	Umyalo uphumelele.
1	Umyalo wehlulekile. Kunephutha. Ungabona umlayezo wephutha kukhonsoli.

Uhlu lwamaphutha

Ikhodi Yephutha	Imilayezo Yephutha	Incazelo
I-ERR0003	Ayikwazi ukuvulafile indlela> file	I file indlela ayilungile. Hlola ukuthi uhla lwemibhalo lomzali lukhona yini.
I-ERR0002	I-PDC file 'file path>' ayibhaleki.	I-PDC ecacisiwe file ayinayo imvume yokubhala.
I-ERR0023	Ipharamitha edingekayo file igama alikho	I-PDC file indlela iyinketho eyisibopho futhi kufanele icaciswe.

Example
write_pdc “derived.pdc”
9.1.11 bhala_ndc (Buza Umbuzo)
Incazelo
Ubhala izingqinamba ze-NDC zibe a file.
bhala_ndcfileigama>
Izingxabano

Ipharamitha	Uhlobo	Incazelo
fileigama	Intambo	Indlela eya ku-NDC file izokwenziwa. Lena inketho eyisibopho. Uma i file ikhona, izosulwa.

Buyisela Uhlobo	Incazelo
0	Umyalo uphumelele.
1	Umyalo wehlulekile. Kunephutha. Ungabona umlayezo wephutha kukhonsoli.

Uhlu lwamaphutha

Ikhodi Yephutha	Imilayezo Yephutha	Incazelo
I-ERR0003	Ayikwazi ukuvulafile_indlela> file.	File indlela ayilungile. Izinkomba zomzali azikho.
I-ERR0002	NDC file 'file_path>' ayibhaleki.	I-NDC eshiwo file ayinayo imvume yokubhala.
I-ERR0023	Ipharamitha edingekayo _AtclParamO_ ayikho.	I-NDC file indlela iyinketho eyisibopho futhi kufanele icaciswe.

Example
write_ndc “derved.ndc”
9.1.12 add_include_path (Buza Umbuzo)
Incazelo
Icacisa indlela yokusesha hlanganisa files lapho ufunda i-RTL files.
add_include_path
Izingxabano

Ipharamitha	Uhlobo	Incazelo
umkhombandlela	Intambo	Icacisa indlela yokusesha hlanganisa files lapho ufunda i-RTL files. Lolu khetho luyisibopho.

Buyisela Uhlobo	Incazelo
0	Umyalo uphumelele.

Buyisela Uhlobo	Incazelo
1	Umyalo wehlulekile. Kunephutha. Ungabona umlayezo wephutha kukhonsoli.

Uhlu lwamaphutha

Ikhodi Yephutha	Umlayezo Wephutha	Incazelo
I-ERR0023	Ipharamitha edingekayo ehlanganisa indlela ayikho.	Inketho yohla lwemibhalo iyisibopho futhi kufanele ihlinzekwe.

Qaphela: Uma indlela yohla lwemibhalo ayilungile, bese kuthi add_include_path izodluliswa ngaphandle kwephutha.
Nokho, imiyalo ye-read_verilog/read_vhd izohluleka ngenxa yomhlahleli we-Verific.
Example
add_include_path ingxenye/work/CORABC0/CORABC0_0/rtl/vlog/core

Umlando Wokubuyekeza (Buza Umbuzo)

Umlando wokubuyekeza uchaza izinguquko ezisetshenziswe kudokhumenti. Izinguquko zifakwe ohlwini ngokubukeza, kuqala ngokushicilelwa kwamanje.

Buyekeza	Usuku	Incazelo
F	08/2024	Izinguquko ezilandelayo zenziwe kulesi sibuyekezo: • Isigaba esibuyekeziwe seSithasiselo B—Ukungenisa Imitapo Yolwazi Yokulingisa Endaweni Yokulingisa.
E	08/2024	Izinguquko ezilandelayo zenziwe kulesi sibuyekezo: • Isigaba esibuyekeziwe Phezuview. • Isigaba esibuyekeziwe se-Derived SDC File. • Isigaba esibuyekeziwe seSithasiselo B—Ukungenisa Imitapo Yolwazi Yokulingisa Endaweni Yokulingisa.
D	02/2024	Lo mbhalo ukhishwe nge-Libero 2024.1 SoC Design Suite ngaphandle kwezinguquko kusuka ku-v2023.2. Isigaba esibuyekeziwe Ukusebenza ne-derive_constraints Utility
C	08/2023	Lo mbhalo ukhishwe nge-Libero 2023.2 SoC Design Suite ngaphandle kwezinguquko kusuka ku-v2023.1.
B	04/2023	Lo mbhalo ukhishwe nge-Libero 2023.1 SoC Design Suite ngaphandle kwezinguquko kusuka ku-v2022.3.
A	12/2022	Ukubuyekezwa Kokuqala.

Ukusekelwa kwe-Microchip FPGA
Iqembu lemikhiqizo ye-Microchip FPGA lisekela imikhiqizo yalo ngezinkonzo ezehlukene zokusekela, okuhlanganisa Isevisi Yamakhasimende, Isikhungo Sokusekela Ubuchwepheshe Bekhasimende, a webindawo, kanye namahhovisi okuthengisa emhlabeni wonke.
Amakhasimende aphakanyiswa ukuthi avakashele izinsiza ze-inthanethi ze-Microchip ngaphambi kokuxhumana nosekelo njengoba kungenzeka ukuthi imibuzo yawo isiphenduliwe.
Xhumana Nesikhungo Sosizo Lobuchwepheshe ngokusebenzisa i webindawo ku www.microchip.com/support. Yisho inombolo Yengxenye Yedivayisi ye-FPGA, khetha isigaba samacala afanelekile, bese ulayisha idizayini files ngenkathi udala ikesi lokusekela lobuchwepheshe.
Xhumana Nesevisi Yekhasimende ukuze uthole ukwesekwa kwemikhiqizo okungeyona eyobuchwepheshe, njengentengo yomkhiqizo, ukuthuthukiswa komkhiqizo, ulwazi lokubuyekeza, isimo soku-oda, nokugunyazwa.

• Ukusuka eNyakatho Melika, shayela u-800.262.1060
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Ulwazi lwe-Microchip
I-Microchip Webindawo
I-Microchip inikeza ukusekelwa kwe-inthanethi nge-ethu webindawo ku www.microchip.com/. Lokhu webindawo isetshenziselwa ukwenza files kanye nolwazi olutholakala kalula kumakhasimende. Okunye okuqukethwe okutholakalayo kuhlanganisa:

• Ukusekelwa Komkhiqizo - Amashidi wedatha kanye nephutha, amanothi ohlelo lokusebenza kanye ne-sampizinhlelo, izinsiza zokuklama, imihlahlandlela yabasebenzisi kanye nemibhalo yokwesekwa kwezingxenyekazi zekhompuyutha, ukukhishwa kwesofthiwe yakamuva kanye nesofthiwe efakwe kungobo yomlando
• Ukusekelwa Okujwayelekile Kwezobuchwepheshe - Imibuzo Evame Ukubuzwa (FAQs), izicelo zokusekelwa kwezobuchwepheshe, amaqembu ezingxoxo eziku-inthanethi, ukufakwa kuhlu kwamalungu ohlelo lukazakwethu we-Microchip design
• Ibhizinisi le-Microchip - Isikhethi somkhiqizo nemihlahlandlela yoku-oda, ukukhishwa kwakamuva kwabezindaba kwe-Microchip, uhlu lwamasemina nemicimbi, uhlu lwamahhovisi okuthengisa e-Microchip, abasabalalisi nabamele imboni

Isevisi yesaziso sokushintsha umkhiqizo
Isevisi yesaziso sokushintsha umkhiqizo we-Microchip isiza ukugcina amakhasimende enolwazi ngemikhiqizo ye-Microchip. Ababhalisile bazothola isaziso se-imeyili noma nini lapho kukhona izinguquko, izibuyekezo, izibuyekezo noma iziphambeko ezihlobene nomndeni womkhiqizo othile noma ithuluzi lokuthuthukisa elithandwayo. Ukuze ubhalise, yiya ku www.microchip.com/pcn bese ulandela imiyalelo yokubhalisa.

Ukwesekwa Kwamakhasimende
Abasebenzisi bemikhiqizo ye-Microchip bangathola usizo ngeziteshi ezimbalwa:

• Umsabalalisi noma Ummeleli
• Ihhovisi Lokuthengisa Lendawo
• I-Embedded Solutions Engineer (ESE)
• Ukusekela kwezobuchwepheshe

Amakhasimende kufanele athinte umsabalalisi wawo, ummeleli noma i-ESE ukuze bathole ukwesekwa. Amahhovisi okuthengisa endawo nawo ayatholakala ukuze asize amakhasimende. Uhlu lwamahhovisi okuthengisa nezindawo lufakiwe kulo mbhalo. Ukwesekwa kwezobuchwepheshe kuyatholakala nge- webisayithi ku: www.microchip.com/support
Isici Sokuvikela Ikhodi Yamadivayisi e-Microchip
Qaphela imininingwane elandelayo yesici sokuvikela ikhodi emikhiqizweni ye-Microchip:

• Imikhiqizo ye-Microchip ihlangabezana nokucaciswa okuqukethwe ku-Microchip Data Sheet yayo.
• I-Microchip ikholelwa ukuthi umkhaya wayo wemikhiqizo uvikelekile uma usetshenziswa ngendlela ehlosiwe, ngaphakathi kwezicaciso zokusebenza, nangaphansi kwezimo ezivamile.
• Amanani e-Microchip futhi avikela ngokunamandla amalungelo ayo okuvikela ubunikazi bokusungula. Imizamo yokwephula izici zokuvikela ikhodi yomkhiqizo we-Microchip inqatshelwe ngokuphelele futhi ingase yephule uMthetho we-Digital Millennium Copyright Act.
• I-Microchip nanoma yimuphi omunye umkhiqizi we-semiconductor ongaqinisekisa ukuphepha kwekhodi yayo. Ukuvikelwa kwekhodi akusho ukuthi siqinisekisa ukuthi umkhiqizo “awunakunqamuka”. Ukuvikelwa kwekhodi kuhlala kuvela njalo. I-Microchip izinikele ekuthuthukiseni ngokuqhubekayo izici zokuvikela ikhodi zemikhiqizo yethu.

Isaziso Somthetho
Lokhu kushicilelwa kanye nolwazi olulapha kungasetshenziswa kuphela emikhiqizweni ye-Microchip, okuhlanganisa ukuklama, ukuhlola, nokuhlanganisa imikhiqizo ye-Microchip nohlelo lwakho lokusebenza. Ukusetshenziswa kwalolu lwazi nganoma iyiphi enye indlela kwephula le migomo. Ulwazi olumayelana nezinhlelo zokusebenza zedivayisi lunikezwa ukuze kube lula kuwe futhi lungase luthathelwe indawo yizibuyekezo. Kuyisibopho sakho ukuqinisekisa ukuthi isicelo sakho sihlangabezana nezicaciso zakho. Xhumana nehhovisi lakho lendawo yokuthengisa le-Microchip ukuze uthole ukwesekwa okwengeziwe noma, thola ukwesekwa okwengeziwe kokuthi www.microchip.com/en-us/support/design-help/client-support-services.
LOLU LWAZI LUNIKEZWA YI-MICROCHIP “NJENGOBA LUKHO”. I-MICROCHIP AYIKUMELELI NOMA IZIQINISEKISO ZANOMA YILUPHI UHLOBO ENGAPHAMBILI NOMA OKUSHIWO, OKUBHALWE NOMA OKUSHIWO, OKUSHIWO UMTHETHO NOMA OKUNYE, OKUPHATHELENE NOLWAZI KUBANDAKANYA KODWA AKUkhawulelwe KUNOMA YILUPHI ISIQINISEKISO, UKWENZA ISIQINISEKISO, UKWENZA OKUSHIWO. INHLOSO YAMHLABA, NOMA IZIQINISEKISO OKUPHATHANA NEsimo, IKHWALITHI, NOMA UKUSEBENZA KWAYO. AKUKHO MCIMBI ONGAZOBA NESIbophezelo I-MICROCHIP NGANOMA YILUPHI ULWAZI , ESIKHETHEKILE, ESIJEZISO, ISENZAKALO, NOMA OKULANDELAYO, UMONAKALO, Izindleko, NOMA Izindleko zanoma yiluphi uhlobo oluhlotshaniswa noLWAZI NOMA UKUSETSHENZISWA KWALO, NOMA KUBE NEZINTO EZIPHUMAYO, OKUNGENZEKA NOMA UMONAKALO UNGABONAKALA. NGENXA ESIPHELELE NGENXA YOKUMTHETHO, ISIBOPHO SE-MICROCHIP SONKE KUZO ZONKE IZINKINGA NGANOMA YIYIPHI INDLELA EPHATHANA NOLWAZI NOMA UKUSETSHENZISWA KWALO NGEKE KWEQE INANI LEZINKOKHELO, UMA LIKHONA, OYIKHOKHE NGOKUQONDILE UKUZE UKWAZISE.
Ukusetshenziswa kwamadivayisi e-Microchip ekusekeleni impilo kanye/noma izicelo zokuphepha kusengozini yomthengi ngokuphelele, futhi umthengi uyavuma ukuvikela, ukunxephezela kanye nokubamba i-Microchip engenabungozi kunoma yimuphi nanoma yimuphi umonakalo, ukukhokhelwa, amasudi, noma izindleko ezibangelwa ukusetshenziswa okunjalo. Awekho amalayisensi adluliswayo, ngokusobala noma ngenye indlela, ngaphansi kwanoma imaphi amalungelo empahla yengqondo ye-Microchip ngaphandle kwalapho kushiwo ngenye indlela.
Izimpawu zokuhweba
Igama le-Microchip nelogo, ilogo ye-Microchip, i-Adaptec, i-AVR, i-logo ye-AVR, i-AVR Freaks, i-BesTime, i-BitCloud, i-CryptoMemory, i-CryptoRF, i-dsPIC, i-flexPWR, i-HELDO, i-IGLOO, i-JukeBlox, i-KeeLoq, i-Kleer, i-LANCheck, i-LinkMD, i-maXSty MediaLB, megaAVR, Microsemi, Microsemi logo, MOST, MOST logo, MPLAB, OptoLyzer, PIC, picoPower, PICSTART, PIC32 logo, PolarFire, Prochip Designer, QTouch, SAM-BA, SenGenuity, SpyNIC, SST, SST Logo, SuperFlash, Symmetri , SyncServer, Tachyon, TimeSource, tinyAVR, UNI/O, Vectron, kanye ne-XMEGA izimpawu zokuthengisa ezibhalisiwe ze-Microchip Technology Incorporated e-USA nakwamanye amazwe.
AgileSwitch, ClockWorks, The Embedded Control Solutions Company, EtherSynch, Flashtec, Hyper Speed ​​Control, HyperLight Load, Libero, motorBench, mTouch, Powermite 3, Precision Edge, ProASIC, ProASIC Plus, ProASIC Plus logo, Quiet-Wire, SmartFusion, SyncWorld, I-TimeCesium, i-TimeHub, i-TimePictra, i-TimeProvider, ne-ZL yizimpawu zokuthengisa ezibhalisiwe ze-Microchip Technology Incorporated e-USA.
Ukucindezelwa kokhiye abaseduze, i-AKS, i-Analog-for-the-Digital Age, AnyIn, AnyOut, Augmented Switching, BlueSky, BodyCom, Clockstudio, CodeGuard, CryptoAuthentication, CryptoAutomotive, CryptoCompanion, CryptoController, dsPICDEM, dsPICDEM Average, dsPICDEM.net , DAM, ECAN, Espresso T1S, EtherGREEN, EyeOpen, GridTime, IdealBridge, IGaT, In-Circuit Serial Programming, ICSP, INICnet, Intelligent Paralleling, IntelliMOS, Inter-Chip Connectivity, JitterBlocker, Knob-on-Display, maxCripto-Display, Marc ubuningiView, memBrain, Mindi, MiWi, MPASM, MPF, MPLAB Certified logo, MPLIB, MPLINK, mSiC, MultiTRAK, NetDetach, Omniscient Code Generation, PICDEM, PICDEM.net, PICkit, PICtail, Power MOS IV, Power MOS 7, PowerSmart, PowerSmart, , QMatrix, REAL ICE, Ripple Blocker, RTAX, RTG4, SAM-ICE, Serial Quad I/O, simpleMAP, SimpliPHY, SmartBuffer, SmartHLS, SMART-IS, storClad, SQI, SuperSwitcher, SuperSwitcher II, Switchtec, SynchroPHY, Total Endurance , Isikhathi Esethenjwayo, TSHARC, Turing, USBCheck, VariSense, VectorBlox, VeriPHY, ViewI-Span, i-WiperLock, i-XpressConnect, ne-ZENA izimpawu zokuthengisa ze-Microchip Technology Incorporated e-USA nakwamanye amazwe.
I-SQTP iwuphawu lwesevisi lwe-Microchip Technology Incorporated e-USA
Ilogo ye-Adaptec, Frequency on Demand, Silicon Storage Technology, ne-Symmcom izimpawu zokuthengisa ezibhalisiwe ze-Microchip Technology Inc. kwamanye amazwe.
I-GestIC inguphawu lokuthengisa olubhalisiwe lwe-Microchip Technology Germany II GmbH & Co. KG, inkampani ephethwe yi-Microchip Technology Inc., kwamanye amazwe.
Zonke ezinye izimpawu zokuthengisa ezishiwo lapha ziyimpahla yezinkampani zazo.
2024, iMicrochip Technology Incorporated kanye nezinkampani ezingaphansi kwayo. Wonke Amalungelo Agodliwe.
ISBN: 978-1-6683-0183-8
Uhlelo Lokuphatha Ikhwalithi
Ukuze uthole ulwazi mayelana ne-Microchip's Quality Management Systems, sicela uvakashele www.microchip.com/quality.
Ukuthengisa Nesevisi Yomhlaba Wonke

I-AMERICAS	I-ASIA/PACIFIC	I-ASIA/PACIFIC	I-Europe
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