I-DSP Builder ye-Intel FPGAs
Ulwazi Lomkhiqizo
Umkhiqizo ubizwa ngokuthi i-DSP Builder ye-Intel FPGAs. Kuyithuluzi lesofthiwe elivumela abasebenzisi ukuthi baklame futhi basebenzise ama-algorithms wokucubungula isignali yedijithali (i-DSP) kuma-Intel FPGAs. Ithuluzi linikeza ukusebenzelana kwesithombe okuhlanganisa nethuluzi le-MathWorks MATLAB neSimulink, okuvumela abasebenzisi ukuthi baklame izinhlelo ze-DSP besebenzisa indlela yomdwebo webhulokhi. Ithuluzi linezinguqulo ezihlukene, inguqulo yakamuva ithi 22.4. Umkhiqizo udlule ezibuyekezweni ezimbalwa, isibuyekezo ngasinye sethula izici ezintsha, ukulungiswa kweziphazamisi, nokuthuthukiswa. Ithebula lomlando wokubuyekeza linikeza isifinyezo sezinguquko ezenziwe enguqulweni ngayinye. Umkhiqizo unezinhlelo ezimbili ze-blockset: i-blockset ejwayelekile kanye ne-blockset ethuthukisiwe. I-blockset ejwayelekile iyatholakala ku-Intel Quartus Prime Standard Edition, kuyilapho i-blockset ethuthukisiwe itholakala kuzo zombili i-Intel Quartus Prime Pro Edition ne-Intel Quartus Prime Standard Edition. Umkhiqizo unezidingo zesistimu okudingeka zihlangatshezwe ukuze ufakwe kahle futhi usetshenziswe. Idinga okungenani inguqulo eyodwa ye-MathWorks MATLAB kanye nethuluzi le-Simulink, elisekelwa izinguqulo ezingu-64-bit ze-MATLAB. Inguqulo yesofthiwe ye-Intel Quartus Prime kufanele ifane nenguqulo ye-DSP Builder ye-Intel FPGAs esetshenziswayo. I-blockset ethuthukisiwe isebenzisa izinhlobo zamaphoyinti angashintshi we-Simulink kukho konke ukusebenza futhi idinga izinguqulo ezinelayisensi ye-Simulink Fixed Point. I-Intel iphinde income Ibhokisi Lamathuluzi Esistimu ye-DSP kanye neBhokisi Lamathuluzi Lesistimu Yezokuxhumana ukuze kusebenze okwengeziwe.
Imiyalo yokusetshenziswa komkhiqizo
- Qinisekisa ukuthi unenguqulo ehambisanayo ye-MathWorks MATLAB kanye nethuluzi le-Simulink elifakwe endaweni yakho yokusebenza. Ithuluzi lisekela kuphela izinguqulo ezingamabhithi angu-64 ze-MATLAB.
- Qiniseka ukuthi unenguqulo efanele yesofthiwe ye-Intel Quartus Prime efakiwe. Inguqulo kufanele ifane nenguqulo ye-DSP Builder ye-Intel FPGAs oyisebenzisayo.
- Yethula i-DSP Builder ye-Intel FPGAs futhi uvule i-graphical interface.
- Dizayina isistimu yakho ye-DSP usebenzisa indlela yomdwebo webhulokhi onikezwe ithuluzi. Sebenzisa amabhulokhi atholakalayo nezici ukuze wakhe i-algorithm oyifunayo.
- Thatha i-advantage yezinhlobo zamaphoyinti e-Simulink ayo yonke imisebenzi edizayini yakho. Qinisekisa ukuthi unamalayisensi adingekayo e-Simulink Fixed Point.
- Uma udinga ukusebenza okwengeziwe, cabanga ukusebenzisa i-DSP System Toolbox kanye ne-Communications System Toolbox, okunconywe yi-Intel.
- Uma umklamo wakho usuqedile, ungakwazi ukukhiqiza okudingekayo files yokuhlela i-Intel FPGA.
Ngokulandela le miyalo yokusebenzisa, uzokwazi ukuklama futhi usebenzise ngempumelelo ama-algorithms e-DSP ku-Intel FPGAs usebenzisa i-DSP Builder ye-Intel FPGAs.
I-DSP Builder ye-Intel® FPGAs Amanothi Okukhishwa
Ulwazi Oluhlobene
- Isisekelo Solwazi
- Ukufakwa Kwesofthiwe Nokunika Ilayisensi
Iphutha
Ama-Errata amaphutha okusebenza noma amaphutha, angabangela umkhiqizo ukuthi uphambuke ekucacisweni okushicilelwe. Izinkinga zamadokhumenti zifaka amaphutha, izincazelo ezingacacile, noma okushiywe ezicacisweni ezishicilelwe manje noma amadokhumenti omkhiqizo.
Ukuze uthole ulwazi olugcwele mayelana ne-errata kanye nezinguqulo ezithintekayo, bheka ikhasi le-Knowledge Base le-Intel®. webindawo.
Ulwazi Oluhlobene
Isisekelo Solwazi
I-DSP Builder ye-Intel FPGAs Advanced Blockset Revision Umlando
| Inguqulo | Usuku | Incazelo |
| 22.4 | 2022.12.12 | Kwengezwe I-Matrix Multiply Engine Design Example. |
| 22.3 | 2022.09.30 | • Ukusebenza okuthuthukisiwe:
- I-DSP Builder manje isebenzisa ibhulokhi ye-FP DSP ye-FP16 ne-Bfloat16, eyindilinga kahle, Engeza, I-Sub or AddSub kumadivayisi we-Intel Agilex - Inikeze ukufinyelela kuzakhiwo ezisindayo ze-DSP kanye ne-DSP yokungena okucacile nemvelo ku-blockset ye-DSP Builder. - Kuthuthukiswe ukusetshenziswa komqondo we-FP FFT kumafomethi amabili e-FP anembe kancane: FP16 ne-FP19. • Ukuhlanganiswa okuthuthukisiwe kwemiklamo ye-DSP Builder nenye i-IP Kumklami Wenkundla. - I-DSP Builder ayivuli kodwa igcina ndawonye ama-vector amasiginali ayinkimbinkimbi (ngokuzithandela) njengebhizinisi elilodwa lomsele. - Ungakwazi futhi ukwabela indima yangokwezifiso kumsele. I-DSP Builder yabela ngokuzenzakalelayo amapayipi amaningi anamagama ahlukile ngokufaka kuqala isixhumi esibonakalayo ngegama lemodeli ye-DSP Builder. • Kuthuthukiswe ukucushwa okumisiwe kwe- I-FFT amabhlogo ukuze kuncishiswe amaphutha lapho ushintsha amapharamitha we-FFT. • Inketho enikeziwe yokusetha kabusha isimo sangaphakathi se- UMlilo vimba ngesikhathi sokusetha kabusha okufudumele. • Kwengezwe umtapo wolwazi oqukethe amabhulokhi we-Simulink asekelwa i-DSP Builder. |
| 22.2 | 2022.03.30 | Isibalo esincishisiwe sokuphindaphinda kwangaphakathi I-CORDIC vimba ukunciphisa ukusetshenziswa kwensiza nokwandisa ukunemba. |
| waqhubeka... | ||
| Inguqulo | Usuku | Incazelo |
| 22.1 | 2022.06.30 | • Kwengezwe umbiko wokubambezeleka ku I-GPIO block (okufana nokubika kwe-latency ku- Isiteshi IO
amabhlogo). • Kwengezwe i-hybrid back-to-back I-VFFT block, esekela ukusakazwa okuqhubekayo kwedatha lapho usayizi we-FFT ushintsha ngaphandle kokushaya ipayipi le-FFT. • Usekelo olungeziwe lwe-Intel Cyclone 10 LP, Intel MAX 10, Cyclone IV E+GX ku-DSP Builder Advanced Pro. Kufanele uhlanganise i-RTL ekhiqiziwe ne-Intel Quartus Std edition. • Kunwetshwe indlela yokulawula ukufinyelela kokufunda ukuze SharedMems vimba • Ukupakishwa kwebhulokhi ye-DSP okuthuthukisiwe ngokuguqula Engeza, I-Sub, futhi Mux ku-dynamic AddSub vimba |
| 21.4 | 2021.12.30 | Kwengeziwe I-AXI4StreamReceiver futhi I-AXI4StreamTransmitter kwe Ukusakaza umtapo wolwazi |
| 21.3 | 2021.09.30 | • Kwengezwe i-DFT Library nge I-DFT, Hlela kabushaBlock, futhi Hlela kabushaAndRescale amabhlogo
• Usekelo olungeziwe lwamadivayisi e-Cyclone V • Kwengezwe izilawuli zokufinyelela kokufunda (i-RA) kumabhulokhi enkumbulo ye-DSP Builder • Kwengezwe isethi ye-FFT eyenziwe lula yokubuyela emuva • Amandla angeziwe okufaka i-DSP Builder ezimele ngaphandle kokudinga ukufakwa kwe-Intel Quartus Prime okuhambisana nenguqulo |
| 21.1 | 2021.06.30 | • Kwengezwe Finite State Machine vimba kanye nomklamo example.
• Ukwesekwa okwengeziwe kwenguqulo ye-MATLAB: R2020b |
| 20.1 | 2020.04.13 | Kukhishwe isikhethi sedivayisi phakathi Amapharamitha wedivayisi iphaneli. |
| 2019.09.01 | Usekelo olungeziwe lwamadivayisi e-Intel Agilex®. | |
| 19.1 | 2019.04.01 | • Ukwesekwa okwengeziwe kwezinhlobo ezimbili zamaphuzu antantayo e-float16_m7 (bfloat) kanye ne-float19_m10.
• Isici sokulinda esincike esingeziwe. • Kwengezwe ukubika kweleveli yebhafa ye-FIFO. |
| 18.1 | 2018.09.17 | • Kwengezwe ukungenisa kwe-HDL.
• Kungezwe amamodeli esoftware ye-C++. |
| 18.0 | 2018.05.08 | • Ukwesekwa okwengeziwe kokunciphisa ukusetha kabusha okuzenzakalelayo kwemiklamo ye-DSP Builder. Ukunciphisa ukusetha kabusha kunquma isethi encane yamarejista esakhiweni esidinga ukusetha kabusha, kuyilapho kugcinwa ukusebenza okulungile komklamo. Ukunciphisa inani lamarejista ukusetha kabusha kwe-DSP Builder kungase kunikeze ikhwalithi ethuthukisiwe yemiphumela okungukuthi indawo encishisiwe kanye nokwenyuka kwe-Fmax.
• Kwengezwe ukusekelwa kwezinkambu zebhithi ku- SharedMem vimba. Lezi zinkambu zihlinzeka ngokusebenza okufana nokusekelayo kwenkambu yebhithi ekhona ku- I-RegField futhi I-RegOut amabhlogo. • Usekelo lwe-beta olungeziwe lokungenisa kwe-HDL, oluhlanganisa imiklamo ye-VHDL noma ye-Verilog HDL ehlanganisiwe ibe idizayini ye-DSP Builder. Ungakwazi ke ukufanisa idizayini engenisiwe nge-DSP Builder Simulink components. Ukungenisa kwe-HDL kufaka phakathi isixhumi esibonakalayo esincane somsebenzisi, kodwa kudinga ukusetha okwenziwa mathupha. Ukuze usebenzise lesi sici, udinga ilayisensi yethuluzi le-MathWorks HDL Verifier. |
| 17.1 | 2017.11.06 | • Kwengezwe ama-super-sample NCO design example.
• Usekelo olungeziwe lwamadivayisi e-Intel Cyclone® 10 kanye ne-Intel Stratix® 10. • Izimo ezisusiwe ze Amasignali vimba. • Inketho ye-WYSIWYG esusiwe ivuliwe I-SynthesisInfo vimba. |
| 17.0 | 2017.05.05 | • Iqanjwe kabusha njenge-Intel
• Kwehlisiwe Amasignali vimba • Kwengezwe i-Gaussian kanye ne-Random Number Generator design exampLes • Kwengezwe ama-super anosayizi oguquguqukayoampi-led FFT design example • Kwengezwe IHybridVFFT vimba • Kwengezwe GeneralVTwiddle futhi I-GeneralMultVTwiddle amabhlogo |
| 16.1 | 2016.11.10 | • Kwengezwe i-4-channel 2-antenna DUC kanye ne-DDC yedizayini yesithenjwa ye-LTE
• Kwengezwe BFU_simple block • Kudalwe ama-edishini ajwayelekile kanye ne-Pro. I-Pro isekela amadivayisi we-Arria 10; Okujwayelekile kusekela yonke eminye imindeni. • Yehlisiwe i Amasignali vimba • Umsebenzi owengeziwe wokusetha izilungiselelo zesixhumi esibonakalayo se-Avalon-MM kumenyu ye-DSP Builder |
| waqhubeka... | ||
| Inguqulo | Usuku | Incazelo |
| 16.0 | 2016.05.02 | • Imitapo yolwazi ehlelwe kabusha
• Imiphumela yokugoqa ethuthukisiwe kumadivayisi angu-MAX 10 • Kwengezwe isib somklamo omushaampkancane: - I-Gaussian Random Number Generator — DUC_4C4T4R kanye ne-DDC_4C4T4R LTE ukuguqulwa kwedijithali phezulu naphansi • Kwengezwe isu elisha lokuthena le-FFT: prune_to_widths() |
| 15.1 | 2015.11.11 | • Kwehlisiwe Qalisa i-Quartus II futhi Qalisa i-Modelsim amabhlogo
• Kwengezwe usekelo lokuwela iwashi • Kwengezwe izihlungi ezingalungiseka kabusha ze-FIR • Izixhumanisi zebhasi ezithuthukisiwe: - Ukuhlola amaphutha kanye nokubika okuthuthukisiwe - Ukunemba okuthuthukisiwe kokulingisa - Ukwenziwa ngcono komqondo wesigqila sebhasi - Ukuwela iwashi okuthuthukisiwe • Kushintshwe ezinye izixhumi ezibonakalayo ze-Avalon-MM • Kwengezwe amabhulokhi amasha: — Thwebula Amanani — Fanout — Misa isikhashana — I-Vectorfanout • I-IIR eyengeziwe: indawo egxilile enesilinganiso esigcwele kanye ne-IIR: amademo ephoyinti elintantayo anesilinganiso esigcwele • Kungezwe ukudlulisa nokwamukela idizayini yereferensi yemodemu |
| 15.0 | Meyi 2015 | • Usekelo olungeziwe lokuphumayo kwe-SystemVerilog
• Kwengezwe umtapo wezinkumbulo zangaphandle • Kwengezwe Inkumbulo Yangaphandle vimba • Kwengezwe okusha Vumela ukubhala kuzo zombili izimbobo ipharamitha kuya I-DualMem vimba • Amapharamitha ashintshiwe avuliwe Izilungiselelo ze-AvalonMMSlave vimba |
| 14.1 | Disemba 2014 | • Kungezwe usekelo lwamabhulokhi angu-10 aqinile antantayo
• Kwengezwe i-BusStimulus kanye ne-BusStimulusFileAmabhulokhi okufunda kumarejista amephuzwe ngenkumbulo aklama isibample. • Kwengezwe i-AvalonMMSlaveSettings block futhi I-DSP Builder > I-Avalon Interfaces > Isigqila se-Avalon-MM inketho yemenyu • Kukhishwe amapharamitha ebhasi kumabhulokhi Wokulawula kanye Nesiginali • Kususwe umklamo olandelayo exampkancane: - I-Color Space Converter (Ukugoqa Kokwabelana Ngezinsiza) - Ihlanganisa Isihlungi se-FIR esine-Updating Coefficients - Isihlungi sokuqala se-FIR (Ukugoqa Kokwabelana Ngezinsiza) — I-Single-StagIsihlungi se-IIR (Ukugoqa Kokwabelana Ngezinsiza) - Imizuzwana emithathutagIsihlungi se-IIR (Ukugoqa Kokwabelana Ngezinsiza) • Kwengezwe usekelo lwesistimu-in-the-loop • Kwengezwe amabhulokhi amasha: - Isigaba sephuzu elintantayo - Iphuzu elintantayo liphindaphindeka - Kwengezwe umsebenzi we-hypotenuse kubhulokhi yezibalo • Umklamo ongeziwe exampkancane: - Isiguquli sesikhala sombala -I-FIR eyinkimbinkimbi - I-CORDIC evela ku-Primitive Blocks - Ukuncishiswa kwe-Crest factor - Ukugoqa UMlilo - Isihlungi se-Integer Rate Decimation eguquguqukayo - Ukuhlunga kweVector - ngokulandelana futhi kuyaphindaphinda |
| waqhubeka... | ||
| Inguqulo | Usuku | Incazelo |
| • Imiklamo yereferensi engeziwe:
- Ukuncishiswa kwe-Crest factor - I-RF eqondile ene-Synthesizable Testbench - Isihlungi se-Dynamic Decimation — Isihlungi Esilungiseka Kabusha Sokunquma - Isihlungi se-Integer Rate Decimation eguquguqukayo • Kukhishwe ifolda yokwabelana ngezisetshenziswa • Ifolda ye-ALU ebuyekeziwe |
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| 14.0 | Juni 2014 | • Kwengezwe usekelo lwe-MAX 10 FPGAs.
• Kususwe usekelo lwamadivayisi e-Cyclone III kanye ne-Stratix III • Ithuthukisiwe I-DSP Builder Run ModelSim inketho, manje ekuvumela ukuthi usebenzise i-ModelSim yomklamo wezinga eliphezulu noma ama-submodule angawodwana • Kushintshwe ukukhiqizwa kwe-HDL kuhla lwemibhalo lweleveli yedivayisi (ngaphansi kohla lwemibhalo olucacisiwe lwe-RTL) esikhundleni sokulandelana kwezinhla • Kwengezwe isignali yokufunda kusixhumi esibonakalayo sebhasi • Kwengezwe ichweba elicacile ku-FIFO • Amabhulokhi angu-13 FFT ahoxisiwe • Kwengezwe isib somklamo omushaampkancane: - Isixhumi esibonakalayo se-Avalon-ST (Okokufaka nokuphumayo kwe-FIFO Buffer) ene-Backpressure - Isixhumi esibonakalayo se-Avalon-ST (Okukhipha i-FIFO Buffer) ene-Backpressure - Imisebenzi yezibalo ze-Fixed-point - Impande yesikwele esiyingxenye usebenzisa i-CORDIC - Normalizer - I-FFT ehambisanayo - I-Parallel Floating-Point FFT - Izimpande eziyisikwele usebenzisa i-CORDIC - I-FFT/iFFT eshintshwayo — Usayizi Oguquguqukayo Ongaguquki we-FFT - Usayizi Oguquguqukayo Ongaguquki we-FFT ngaphandle kwe-BitReverseCoreC Block - Iphuzu Eliguquguqukayo Losayizi Ongaguquki iFFT - I-variable-Size Fixed-Point iFFT ngaphandle kwe-BitReverseCoreC Block — Usayizi Oguquguqukayo Ontantayo-Iphuzu le-FFT - Usayizi Oguquguqukayo We-Floating-Point FFT ngaphandle kwe-BitReverseCoreC Block - Iphuzu Elintantayo Losayizi Oguquguqukayo iFFT - I-variable-Size Floating-Point iFFT ngaphandle kwe-BitReverseCoreC Block • Kwengezwe amabhulokhi amasha: - Ukubambezeleka Okumisiwe - Ulayini Wokubambezeleka unikwe amandla - Kuvunyelwe Ukulibaziseka Kwempendulo - FFT2P, FFT4P, FFT8P, FFT16P, FFT32P, kanye ne-FFT64P - FFT2X, FFT4X, FFT8X, FFT16X, FFT32X, kanye neFFT64X - FFT2, FFT4, VFFT2, kanye ne-VFFT4 - I-General Multitwiddle kanye ne-General Twiddle (I-GeneralMultiTwiddle, i-GeneralTwiddle) - I-Hybrid FFT (Hybrid_FFT) - I-Parallel Pipelined FFT (PFFT_Pipe) — Lungile |
| 13.1 | Novemba 2013 | • Kususwe usekelo lwamadivayisi alandelayo:
- I-Arria GX - I-Cyclone II — I-HardCopy II, i-HardCopy III, ne-HardCopy IV - I-Stratix, i-Stratix II, i-Stratix GX, ne-Stratix II GX • Ukugeleza kokugoqa kwe-ALU okuthuthukisiwe • Kwengezwe imisebenzi emisha ebhulokhini Lezibalo. |
| waqhubeka... | ||
| Inguqulo | Usuku | Incazelo |
| • Kwengezwe inketho ye-Simulink fi block kumabhulokhi we-Const, i-DualMem, ne-LUT
• Kwengezwe isib somklamo omushaampkancane: - Iyaguquguquka-nemba real-time FFT - I-interpolating FIR Isihlungi esinama-coefficients abuyekeziwe - I-beamformer yokubambezeleka kwesikhathi • Kwengezwe amabhulokhi amasha: - Ukubambezeleka Okumisiwe - I-Polynomial - I-TwiddleAngle - I-TwiddleROM ne-TwiddleROMF - VariableBitReverse - VFF |
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| 13.0 | Meyi 2013 | • Ibhulokhi yedivayisi ebuyekeziwe enemenyu entsha Yesikhethi Sedivayisi.
• Kwengezwe amabhulokhi amasha e-ModelPrim: - Const Mult — Hlukanisa - MinMax — Negate - Umkhiqizo we-Scalar • Kwengezwe amabhlogo ayisishiyagalolunye amasha e-FFT • Kwengezwe imibukiso emisha eyishumi ye-FFT |
| 12.1 | Novemba 2012 | • Isici sokugoqa se-ALU esingeziwe
• Kungezwe izinketho zamaphoyinti antantayo anembayo athuthukisiwe • Kwengezwe amabhulokhi amasha alandelayo e-ModelPrim: - EngezaSub - EngezaSubFused - CmpCtrl — Izibalo - Maximum and Minimum - MinMaxCtrl - Umjikelezo - I-Trig • Kwengezwe amabhulokhi amasha e-FFT alandelayo: - I-Edge Detect (i-EdgeDetect) - I-Pulse Divider (i-PulseDivider) - I-Pulse Multiplier (PulseMultiplier) — I-Bit-Reverse FFT nge-Natural Output (FFT_BR_Natural) • Kwengezwe umklamo omusha we-FIR exampkancane: - Super-sampisihlungi se-FIR esinciphisa - Super-sampisihlungi se-FIR esiyingxenye • Kwengezwe indawo, isivinini, nokulawula kwamanje kwamamotho e-AC (anokugoqeka kwe-ALU) umklamo example |
Ulwazi Oluhlobene
I-DSP Builder Advanced Blockset Handbook
Izidingo Zesistimu
- I-DSP Builder ye-Intel FPGAs ihlanganisa ne-MathWorks MATLAB namathuluzi e-Simulink kanye nesofthiwe ye-Intel Quartus® Prime.
- Qinisekisa ukuthi okungenani inguqulo eyodwa ye-MathWorks MATLAB nethuluzi le-Simulink iyatholakala endaweni yakho yokusebenza ngaphambi kokufaka i-DSP Builder ye-Intel FPGAs. Kufanele usebenzise inguqulo efanayo yesofthiwe ye-Intel Quartus Prime kanye ne-DSP Builder ye-Intel FPGAs. I-DSP Builder ye-Intel FPGAs isekela kuphela izinguqulo ezingu-64-bit ze-MATLAB.
- Kusukela ku-v18.0, i-DSP Builder ye-Intel FPGAs i-blockset ethuthukisiwe iyatholakala ku-Intel Quartus Prime Pro Edition kanye ne-Intel Quartus Prime Standard Edition. I-DSP Builder ye-Intel FPGAs blockset ejwayelekile itholakala kuphela ku-Intel Quartus Prime Standard Edition.
Ithebula 2. I-DSP Builder ye-Intel FPGAs MATLAB Dependencies
| Inguqulo | Izinhlobo Ezisekelwayo ze-MATLAB | ||
| I-DSP Builder Standard Blockset | I-DSP Builder Advanced Blockset | ||
| I-Intel Quartus Prime Standard Edition | I-Intel Quartus Prime Pro Edition | ||
| 22.4 | Akutholakali | R2022a R2021b R2021a R2020b R2020a | |
| 22.3 | Akutholakali | R2022a R2021b R2021a R2020b R2020a | |
| 22.1 | Akutholakali | R2021b R2021a R2020b R2020a R2019b | |
| 21.3 | Akutholakali | R2021a R2020b R2020a R2019b R2019a | |
| 21.1 | Akutholakali | R2020b R2020a R2019b R2019a R2018b | |
| 20.1 | Akutholakali | R2019b R2019a R2018b R2018a R2017b R2017a | |
| 19.3 | Akutholakali | R2019a R2018b R2018a R2017b | |
| waqhubeka... | |||
| Inguqulo | Izinhlobo Ezisekelwayo ze-MATLAB | ||
| I-DSP Builder Standard Blockset | I-DSP Builder Advanced Blockset | ||
| I-Intel Quartus Prime Standard Edition | I-Intel Quartus Prime Pro Edition | ||
| R2017a R2016b | |||
| 19.1 | Ayisekelwe | R2013a | R2018b R2018a R2017b R2017a R2016b |
| 18.1 | R2013a | R2013a | R2018a R2017b R2017a R2016b |
| 18.0 | R2013a | R2013a | R2017b R2017a R2016b R2016a R2015b |
| 17.1 | R2013a | R2013a | R2016a R2015b R2015a R2014b R2014a R2013b |
Qaphela:
I-DSP Builder ye-Intel FPGAs i-blockset ethuthukisiwe isebenzisa izinhlobo zamaphoyinti angashintshi we-Simulink kuyo yonke imisebenzi futhi idinga izinguqulo ezinelayisensi ye-Simulink Fixed Point. I-Intel iphinde income Ibhokisi Lamathuluzi Esistimu ye-DSP kanye neBhokisi Lamathuluzi Lesistimu Yezokuxhumana, okuthi abanye baklame exampukusetshenziswa kancane.
Ulwazi Oluhlobene
Ukufakwa kweSoftware ye-Intel nokunikezwa kwelayisensi.
I-DSP Builder ye-Intel® FPGAs Amanothi Okukhishwa 9
Amadokhumenti / Izinsiza
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I-intel DSP Builder ye-Intel FPGAs [pdf] Umhlahlandlela Womsebenzisi I-DSP Builder ye-Intel FPGAs, Umakhi we-Intel FPGAs, Intel FPGAs, FPGAs |