Intel 50G Ethernet Design Example Umhlahlandlela Womsebenzisi

Okuqukethwe fihla

1 Intel 50G Ethernet Design Example

2 I-50GbE Quick Start Guide

3 I-Design Example Ukwakheka Kwemibhalo

4 Idizayini yokulingisa Isibample Components

5 Ukukhiqiza I-Design Example

6 Ukulingisa i-50GbE Design Example Testbench

7 I-Design Example Incazelo

8 I-50GbE Design Example Registers

9 Amadokhumenti / Izinsiza

9.1 Izithenjwa

10 Okuthunyelwe Okuhlobene

Intel 50G Ethernet Design Example

I-50GbE Quick Start Guide

I-50GbE IP core inikeza ibhentshi lokuhlola lokulingisa kanye ne-ex yedizayini yehadiweample esekela ukuhlanganiswa nokuhlolwa kwehadiwe. Uma udala i-ex designample, umhleli wepharamitha udala ngokuzenzakalelayo i filekudingekile ukulingisa, ukuhlanganisa, nokuhlola idizayini kuhadiwe. Ungalanda idizayini yehadiwe ehlanganisiwe kudivayisi ye-Arria 10 GT.

Qaphela: Lo mklamo example iqondise idivayisi ye-Arria 10 GT futhi idinga isibali sikhathi esingu-25G. Sicela uxhumane noqokelwe ukumela i-Intel FPGA ukuze ubuze mayelana nenkundla efanele ukusebenzisa lesi sici sezingxenyekazi zekhompuyuthaample. Kwezinye izimo kungase kutholakale imali ebolekiwe yehadiwe efanele. Ngaphezu kwalokho, i-Intel inikeza i-ex yokuhlanganisa kuphelaample phrojekthi ongayisebenzisa ukuze ulinganisele ngokushesha indawo eyinhloko ye-IP nesikhathi.

Umfanekiso 1. Umklamo Example Ukusetshenziswa

Inkampani ye-Intel Wonke Amalungelo Agodliwe. I-Intel, ilogo ye-Intel, nezinye izimpawu ze-Intel yizimpawu zokuthengisa ze-Intel Corporation noma izinkampani ezingaphansi kwayo. I-Intel iqinisekisa ukusebenza kwe-FPGA yayo kanye nemikhiqizo yesemiconductor ekucacisweni kwamanje ngokuvumelana newaranti evamile ye-Intel, kodwa igodla ilungelo lokwenza izinguquko kunoma imiphi imikhiqizo namasevisi nganoma yisiphi isikhathi ngaphandle kwesaziso. I-Intel ayithathi mthwalo noma isikweletu esivele ngenxa yesicelo noma ukusetshenziswa kwanoma yiluphi ulwazi, umkhiqizo, noma isevisi echazwe lapha ngaphandle kwalapho okuvunyelwene ngakho ngokubhaliwe yi-Intel. Amakhasimende e-Intel ayelulekwa ukuthi athole inguqulo yakamuva yokucaciswa kwedivayisi ngaphambi kokuthembela kunoma yiluphi ulwazi olushicilelwe nangaphambi kokufaka ama-oda emikhiqizo noma amasevisi. *Amanye amagama namabhrendi angafunwa njengempahla yabanye.

I-Design Example Ukwakheka Kwemibhalo

Umfanekiso 2. 50GbE Design Example Ukwakheka Kwemibhalo

Ukucushwa kwezingxenyekazi zekhompuyutha nokuhlola files (i-hardware design example) zitholakala kuample_dir>/hardware_test_design. Ukulingiswa files (i-testbench yokulingisa kuphela) itholakala kuample_dir>/isbample_testbench.Umklamo wokuhlanganisa kuphela example itholakala kuample_dir>/compilation_test_design.

Idizayini yokulingisa Isibample Components

Umfanekiso 3. 50GbE Idizayini Yokulingisa Example Block Diagram

Ukulingisa isbample design level top test file i-basic_avl_tb_top.sv Lokhu file iqinisekisa futhi ixhuma i-ATX PLL. Kuhlanganisa umsebenzi, send_packets_50g_avl, ukuthumela nokwamukela amaphakethe ayi-10.

Ithebula 1. 50GbE IP Core Testbench File Izincazelo

File Igama	Incazelo
Testbench futhi Simulation Files
basic_avl_tb_top.sv	I-testbench yezinga eliphezulu file. I-testbench iqinisekisa i-DUT futhi isebenzisa imisebenzi ye-Verilog HDL ukuze ikhiqize futhi yamukele amaphakethe.
Izikripthi ze-Testbench
run_vsim.do	Isikripthi se-ModelSim sokuqalisa ibhentshi le-test.
run_vcs.sh	Iskripthi se-Synopsy VCS sokuqalisa ibhentshi lokuhlola.
run_ncsim.sh	Iskripthi se-Cadence NCSim sokuqalisa ibhentshi lokuhlola.
run_xcelium.sh	Iskripthi se-cadence Xcelium* sokuqalisa ibhentshi lokuhlola.

I-rdware Design Example Components

Umfanekiso 4. 50GbE Idizayini Yezingxenyekazi zekhompuyutha Example High Level Block Diagram

I-50GbE hardware design example ihlanganisa izingxenye ezilandelayo

I-50GbE IP core.
I-logic yeklayenti ehlanganisa ukuhlelwa kwe-IP core kanye nokukhiqizwa kwephakethe.

I-ATX PLL ukushayela iziteshi ze-transceiver zedivayisi.
I-IOPLL ukukhiqiza iwashi elingu-100 MHz ukusuka ewashi lokokufaka elingu-50 MHz ukuya ku-ex yedizayini yehadiwe.ample.

JTAG isilawuli esixhumana Nekhonsoli Yesistimu. Uxhumana ne-logic yeklayenti nge-System Console.

Ithebula 2. 50GbE IP Core Hardware Design Example File Izincazelo

File Amagama	Incazelo
ethi_ex_50g.qpf	Iphrojekthi ye-Quartus Prime file
eth_ex_50g.qsf	Izilungiselelo zephrojekthi ye-Quartus file
eth_ex_50g.sdc	I-Synopsys Design Constrants file. Ungakopisha futhi ulungise lokhu file ngomklamo wakho we-50GbE.
*waqhubeka...*

I-50GbE Quick Start Guide

File Amagama	Incazelo
eth_ex_50g.v	Idizayini yezinga eliphezulu ye-Verilog HDL example file
okuvamile/	Idizayini yezingxenyekazi zekhompuyutha example support files
hwtest/main.tcl	Okuyinhloko file ukuze ufinyelele Ikhonsoli Yesistimu

Ukukhiqiza I-Design Example

Umfanekiso 5. Inqubo

Umfanekiso 6. Isbample-Design Tab ku-50GbE Parameter Editor

Landela lezi zinyathelo ukuze ukhiqize i-ex ye-hardware designample kanye ne-testbench

Kuya ngokuthi usebenzisa isofthiwe ye-Intel Quartus® Prime Pro Edition noma isofthiwe ye-Intel Quartus Prime Standard Edition, yenza esinye salezi zenzo ezilandelayo: Ku-Intel Quartus Prime Pro Edition, chofoza File ➤ Iseluleki Sephrojekthi Esisha sokudala iphrojekthi entsha ye-Quartus Prime, noma File ➤ Vula Iphrojekthi ukuze uvule iphrojekthi ekhona ye-Quartus Prime. Iwizadi ikutshela ukuthi ucacise idivayisi. Kusofthiwe ye-Intel Quartus Prime Standard Edition, kukhathalogi ye-IP (Ikhathalogi ye-IP yamathuluzi), khetha umndeni wedivayisi eqondiwe ye-Arria 10.
Kukhathalogi ye-IP, thola bese ukhetha i-50G Ethernet. Iwindi le-New IP Variation liyavela.

Cacisa igama lezinga eliphezulu lokuhluka kwakho kwe-IP bese uchofoza okuthi KULUNGILE. Umhleli wepharamitha wengeza izinga eliphezulu elithi .qsys (ku-Intel Quartus Prime Standard Edition) noma .ip (ku-Intel Quartus Prime Pro Edition) file kuphrojekthi yamanje ngokuzenzakalela. Uma ucelwa ukuthi wengeze ngokwakho i-.qsys noma i-.ip file kuphrojekthi, chofoza Iphrojekthi ➤ Engeza/Susa Files kuphrojekthi yokwengeza i file.
Kusofthiwe ye-Intel Quartus Prime Standard Edition, kufanele ukhethe idivayisi ethile ye-Arria 10 endaweni yeDivayisi, noma ugcine idivayisi emisiwe isofthiwe ye-Quartus Prime ehlongozwayo.
Qaphela: I-hardware design exampibhala phezu kwalokho okukhethiwe ngocingo ebhodini eliqondiwe. Ucacisa ibhodi eliqondiwe kusuka kumenyu ye-design example ongakhetha kukho Example Dizayini ithebhu (Isinyathelo 8).

Chofoza okuthi KULUNGILE. Umhleli wepharamitha uyavela.
Kuthebhu ye-IP, cacisa imingcele yokuhluka kwakho okubalulekile kwe-IP.

Ku-Example Dizayini ithebhu, Example Design Files, khetha inketho yokulingisa ukuze ukhiqize ibhentshi lokuhlola, bese ukhetha inketho ye-Synthesis ukuze ukhiqize i-ex yedizayini yehadiwe.ample. Kuphela Verilog HDL files ziyakhiqizwa.
Qaphela: I-VHDL IP core esebenzayo ayitholakali. Cacisa i-Verilog HDL kuphela, ye-IP core design ex yakhoample.
Ku-Hardware Board khetha Ikhithi Yokuthuthukiswa Kwesiginali ye-Arria 10 GX Transceiver Integrity.
Qaphela: Xhumana nommeleli wakho we-Intel FPGA ukuze uthole ulwazi mayelana nenkundla efanele ukusebenzisa lesi sici sezingxenyekazi zekhompuyuthaample.

Chofoza okuthi Khiqiza i-Exampinkinobho ethi Design. Khetha ExampIwindi le-Design Directory liyavela.
Uma ufisa ukuguqula i-design example mkhombandlela noma igama elivela kokumisiwe okubonisiwe (alt_e50_0_example_design), phequlula endleleni entsha bese uthayipha umklamo omusha exampigama lenkomba (ample_dir>).
Chofoza okuthi KULUNGILE.
Bheka Impendulo ye-KDB Ngiyinxephezela kanjani i-jitter ye-PLL cascading noma indlela yewashi elingazinikele yewashi eliyireferensi le-Arria 10 PLL? ukuze uthole umsebenzi kufanele usebenzise kuhla lwemibhalo lwehadiwe_test_design ku-.sdc file.

Qaphela: Kufanele uthintane nale Mpendulo ye-KDB ngoba indlela ye-RX kumongo we-50GbE IP ihlanganisa nama-PLL acashile. Ngakho-ke, amawashi ayinhloko we-IP angase abe ne-jitter eyengeziwe kumadivayisi we-Arria 10. Le mpendulo ye-KDB icacisa ukukhishwa kwesofthiwe lapho i-workaround idingeka khona.

Ulwazi Oluhlobene
Impendulo ye-KDB: Ngiyinxephezela kanjani i-jitter ye-PLL cascading noma indlela yewashi elingazinikele yewashi eliyireferensi le-Arria 10 PLL?

Ukulingisa i-50GbE Design Example Testbench

Umfanekiso 7. Inqubo

Landela lezi zinyathelo ukuze ulingise ibhentshi le-test

Shintshela kumkhombandlela wokulingisa we-testbenchample_dir>/isbample_testbench.
Qalisa iskripthi sokulingisa sesifanisi esisekelwayo ozikhethele sona. Umbhalo uhlanganisa futhi uqhube ibhentshi lokuhlola kusifanisi. Bheka ithebula elithi “Izinyathelo Zokulingisa i-Testbench”.
Hlaziya imiphumela. I-testbench ephumelelayo ithumela amaphakethe ayishumi, ithola amaphakethe ayishumi, futhi ibonise “i-Testbench ephelele.”

Ithebula 3. Izinyathelo Zokulingisa I-Testbench

Isifanisi	Iziyalezo
ImodeliSim	Emugqeni womyalo, thayipha i-vsim -do run_vsim.do Uma ukhetha ukulingisa ngaphandle kokuletha i-ModelSim GUI, thayipha i-vsim -c -do run_vsim.do Qaphela: Isifanisi se-ModelSim* - Intel FPGA Edition asinawo amandla okulingisa lo mgogodla we-IP. Kufanele usebenzise esinye isifanisi se-ModelSim esisekelwayo njenge-ModelSim SE.
I-NCSim	Emugqeni womyalo, thayipha okuthi sh run_ncsim.sh
I-VCS	Emugqeni womyalo, thayipha okuthi sh run_vcs.sh
I-Xcelium	Emugqeni womyalo, thayipha okuthi sh run_xcelium.sh

Ukuhlolwa okuphumelelayo kubonisa okukhiphayo okuqinisekisa ukuziphatha okulandelayo

Ilinde iwashi le-RX ukuthi lizinze
Iphrinta isimo se-PHY
Ithumela amaphakethe ayi-10
Ithola amaphakethe ayi-10

Ibonisa okuthi “Testbench iqedile.”

Okulandelayo sampokukhiphayo kubonisa ukuqaliswa kokuhlolwa kokulingisa okuyimpumelelo

Iwashi elingu-#Ref lisebenza ngo-625 MHz ukuze izinombolo eziphelele zisetshenziswe kuzo zonke izikhathi zewashi.

#Phindaphinda ubike amaza ngo-33/32 ukuze uthole amaza ewashi angempela.
#Ilinde ukulungiswa kwe-RX
#RX deskew ikhiyiwe

#Ukuqondanisa komzila we-RX kukhiyiwe
#TX inikwe amandla
#**Ithumela Iphakethe 1…

#**Ithumela Iphakethe 2…
#**Ithumela Iphakethe 3…
#**Ithumela Iphakethe 4…

#**Ithumela Iphakethe 5…
#**Ithumela Iphakethe 6…
#**Ithumela Iphakethe 7…

#**Iphakethe elitholiwe 1…
#**Ithumela Iphakethe 8…
#**Iphakethe elitholiwe 2…

#**Ithumela Iphakethe 9…
#**Iphakethe elitholiwe 3…
#**Ithumela Iphakethe 10…

#**Iphakethe elitholiwe 4…
#**Iphakethe elitholiwe 5…
#**Iphakethe elitholiwe 6…

#**Iphakethe elitholiwe 7…
#**Iphakethe elitholiwe 8…
#**Iphakethe elitholiwe 9…

#**Iphakethe elitholiwe 10…
#**
#** I-Testbench iqedile.

#**
#****************************************

Ukuhlanganisa kanye nokulungiselela i-Design Exampku-Hardware

Ukuhlanganisa i-hardware design example futhi uyilungiselele kudivayisi yakho ye-Arria 10 GT, landela lezi zinyathelo

Qinisekisa ukuthi i-hardware design exampisizukulwane sesiphelile.
Kuhlelo lwe-Intel Quartus Prime, vula iphrojekthi ye-Intel Quartus Primeample_dir>/hardware_test_design/eth_ex_50g.qpf.

Ngaphambi kokuhlanganisa, qiniseka ukuthi usebenzise indlela yokusebenza evela kokuthi Impendulo ye-KDB Ngiyinxephezela kanjani i-jitter ye-PLL cascading noma indlela yewashi elinganikezelwe yewashi eliyinkomba le-Arria 10 PLL? uma kufaneleka ekukhishweni kwesofthiwe yakho.
Kumenyu Yokucubungula, chofoza Qala Ukuhlanganisa.
Ngemva kokwenza into ye-SRAM file .sof, landela lezi zinyathelo ukuze uhlele i-hardware design example kudivayisi ye-Arria 10:

Kumenyu yamathuluzi, chofoza uMhleli.
Ku-Programmer, chofoza Ukusethwa Kwezingxenyekazi zekhompuyutha.
Khetha idivayisi yokuhlela.

Khetha futhi wengeze ibhodi le-Arria 10 GT eline-retimer engu-25G kuseshini yakho ye-Intel Quartus Prime.
Qinisekisa ukuthi Imodi isethwe ku-JTAG.
Khetha idivayisi ye-Arria 10 bese uchofoza Engeza idivayisi. I-Programmer ibonisa idayagramu yebhlokhi yokuxhumana phakathi kwamadivayisi ebhodini lakho.

Emgqeni ne-.sof yakho, hlola ibhokisi le-.sof.
Thikha ibhokisi kokuthi Uhlelo/Lungisa ikholomu.
Chofoza Qala

Qaphela: Lo mklamo example iqondise idivayisi ye-Arria 10 GT. Sicela uxhumane noqokelwe ukumela i-Intel FPGA ukuze ubuze mayelana nenkundla efanele ukusebenzisa lesi sici sezingxenyekazi zekhompuyuthaample

Ulwazi Oluhlobene

Impendulo ye-KDB: Ngiyinxephezela kanjani i-jitter ye-PLL cascading noma indlela yewashi elinganikeziwe yewashi eliyireferensi le-Arria 10 PLL?

Ukuhlanganiswa Okukhulayo Kwedizayini Esekwe Emaqenjini
Izinhlelo ze-Intel FPGA Amadivayisi

Ihlola i-50GbE Hardware Design Example

Ngemva kokuhlanganisa i-50GbE IP core design example futhi uyilungiselele kudivayisi yakho ye-Arria 10 GT, ungasebenzisa Ikhonsoli Yesistimu ukuze uhlele umongo we-IP kanye namarejista awo ayinhloko e-PHY IP ashumekiwe. Ukuze uvule ikhonsoli Yesistimu futhi uhlole idizayini yezingxenyekazi zekhompuyutha example, landela lezi zinyathelo:

Ngemva kwe-hardware design example ilungiselelwe kudivayisi ye-Arria 10, kusofthiwe ye-Intel Quartus Prime, kumenyu ethi Amathuluzi, chofoza Amathuluzi Okulungisa Amaphutha Esistimu ➤ Ikhonsoli Yesistimu.
Kufasitelana le-Tcl Console, thayipha i-cd hwtest ozoshintshela kuyo uhla lwemibhaloample_dir>/hardware_test_design/hwtest.

Thayipha umthombo main.tcl ukuze uvule uxhumano ku-JTAG inkosi.

Ungakwazi ukuhlela i-IP core nge-ex yedizayini elandelayoample imiyalo

chkphy_status: Ibonisa amaza wewashi nesimo sokukhiya se-PHY.

start_pkt_gen: Iqala ijeneretha yephakethe.
stop_pkt_gen: Imisa ijeneretha yephakethe.
i-loop_on: Ivula i-loopback ye-serial yangaphakathi

i-loop_off: Ivala i-loopback ye-serial yangaphakathi.
reg_funda : Ibuyisela inani lerejista eyinhloko ye-IP kokuthi .
bhala_bhala : Uyabhala kurejista ye-IP eyinhloko ekhelini .

Ulwazi Oluhlobene

I-50GbE Design Example Amarejista ekhasini 13 Bhalisa imephu ye-hardware design example.
Ukuhlaziya nokulungisa amadizayini nge-System Console

I-Design Example Incazelo

Umklamo exampi-le ibonisa imisebenzi ye-50GbE core ene-transceiver interface ethobelana ne-IEEE 802.3ba ejwayelekile ye-CAUI-4. Ungakwazi ukukhiqiza umklamo kusukela Example Design ithebhu kusihleli sepharamitha ye-50GbE. Ukukhiqiza i-design exampNokho, kufanele uqale usethe amanani epharamitha okuhluka okuyinhloko kwe-IP ohlose ukukukhiqiza kumkhiqizo wakho wokugcina. Ikhiqiza i-ex designample idala ikhophi ye-IP core; i-testbench kanye ne-hardware design exampngisebenzise lokhu kuhluka njenge-DUT. Uma ungasethi amanani epharamitha e-DUT ukuze afane namanani epharamitha kumkhiqizo wakho wokugcina, i-design ex.ampokukhiqizayo akusebenzisi ukuhluka okuyinhloko kwe-IP ohlosile.

Qaphela: I-testbench ibonisa ukuhlolwa okuyisisekelo kwe-IP core. Akuhloselwe ukuba esikhundleni sendawo yokuqinisekisa egcwele. Kufanele wenze ukuqinisekiswa okubanzi okwengeziwe kwedizayini yakho engu-50GbE ekulingiseni nakwihardware.

Ulwazi Oluhlobene
Intel Arria® 10 50Gbps Ethernet IP Core User Guide

I-Design Example Behaviour
I-testbench ithumela ithrafikhi nge-IP core, isebenzisa uhlangothi lokudlulisa futhi yamukele uhlangothi lwe-IP core. Kumklamo wehadiwe example, ungakwazi ukuhlela i-IP core kumodi yangaphakathi ye-serial loopback futhi ukhiqize ithrafikhi kuhlangothi lokudlulisa olujikela emuva ngohlangothi lokwamukela.

I-Design Example Interface Signals
I-50GbE testbench izimele futhi ayidingi ukuthi ushayele noma yiziphi izimpawu zokufaka.

Ithebula 4. 50GbE I-Hardware Design Example Interface Signals

Isiginali	Isiqondiso	Amazwana
cl50	Okokufaka	Shayela ngo-50 MHz. Inhloso ukushayela lokhu kusuka ku-oscillator engu-50 Mhz ebhodini.
clk_ref	Okokufaka	Shayela ku-644.53125 MHz.
cpu_resetn	Okokufaka	Isetha kabusha i-IP core. Okuphansi okusebenzayo. Ishayela ukusetha kabusha kanzima komhlaba wonke i-csr_reset_n ku-IP core.
*waqhubeka...*

Isiginali	Isiqondiso	Amazwana
i-tx_serial[1:0]	Okukhiphayo	I-Transceiver PHY yomkhiqizo wedatha ye-serial.
rx_serial[1:0]	Okokufaka	I-Transceiver PHY idatha yesiriyeli yokufaka.
umsebenzisi_uholwa[7:0]	Okukhiphayo	Izimpawu zesimo. I-hardware design example ixhuma lezi zingcezu ukushayela ama-LED ebhodini eliqondiwe. Amabhithi angawodwana abonisa amanani esignali alandelayo nokuziphatha kwewashi: • [0]: Isiginali yokusetha kabusha eyinhloko kumongo we-IP • [1]: Inguqulo ehlukanisiwe ye-clk_ref • [2]: Inguqulo ehlukanisiwe ye-clk50 • [3]: Inguqulo ehlukanisiwe yewashi lesimo le-100 MHz • [4]: tx_lanes_stable • [5]: rx_block_lock • [6]: rx_am_lock • [7]: rx_pcs_ready

Ulwazi Oluhlobene
Ukusebenzelana Nezincazelo Zesiginali Inikeza izincazelo ezinemininingwane yamasiginali angumongo we-50GbE IP kanye nezindawo eziyingxenye yazo.

I-50GbE Design Example Registers

Ithebula 5. 50GbE I-Hardware Design Example Bhalisa imephu
Iklelisa ububanzi berejista ebhalwe kumephu ye-hardware example. Ufinyelela lawa marejista ngemisebenzi ethi reg_read and reg_write kukhonsoli Yesistimu.

I-Word Offset	Bhalisa Isigaba
0x300–0x5FF	50GbE IP core amarejista.
0x4000–0x4C00	I-Arria 10 amarejista okulungisa kabusha ashukumisayo. Ikheli lesisekelo sokubhalisa ngu-0x4000 ku-Lane 0 kanye no-0x4400 ku-Lane 1.

Ulwazi Oluhlobene

Ihlola i-50GbE Hardware Design Example ekhasini 11 Ikhonsoli Yesistimu iyala ukufinyelela umgogodla we-IP kanye namarejista oMdabu e-PHY.
50GbE Ukulawula kanye Nezincazelo Zerejista Yesimo Ichaza amarejista awumongo we-50GbE IP.

Umlando Wokubuyekeza Idokhumenti

Ithebula 6. 50G Ethernet Design Example Umlando Wokubuyekeza Umhlahlandlela Womsebenzisi

Usuku	Khulula	Izinguquko
2019.04.03	17.0	Kwengezwe umyalo wokuqalisa ukulingisa kwe-Xcelium.
2017.11.08	17.0	Kungezwe isixhumanisi kokuthi Impendulo ye-KDB ehlinzeka ngokusebenza nge-jitter engaba khona kumadivayisi we-Intel Arria® 10 ngenxa yokuphuma kwe-ATX PLL kumongo we-IP. Bukela ku Ukukhiqiza I-Design Example ekhasini 7 no Ukuhlanganisa kanye Ilungiselela i-Design Exampku-Hardware ekhasini lesi-10. Lo mklamo exampi-user guide ayizange ibuyekezwe ukuze ibonise Qaphela: izinguquko ezincane ekwenziweni kokuklama ku-Intel Quartus Prime ekhishwa kamuva kunokukhishwa kwesoftware ye-Intel Quartus Prime v17.0.
2017.05.08	17.0	Ukukhishwa kokuqala esidlangalaleni.

Amadokhumenti / Izinsiza

Intel 50G Ethernet Design Example [pdf] Umhlahlandlela Womsebenzisi
I-50G Ethernet Design Example, 50G, Ethernet Design Example, Design Example

Izithenjwa

Imaniwali yosebenzisayo

Intel 50G Ethernet Design Example

I-50GbE Quick Start Guide

I-Design Example Ukwakheka Kwemibhalo

Idizayini yokulingisa Isibample Components

Ukukhiqiza I-Design Example

Ukulingisa i-50GbE Design Example Testbench

I-Design Example Incazelo

I-50GbE Design Example Registers

Amadokhumenti / Izinsiza

Izithenjwa

Shiya amazwana

Khansela impendulo