I-intel Migration Guidelines ukusuka ku-Arria 10 kuya ku-Stratix 10 ye-10G Ethernet Subsystem

Imihlahlandlela Yokuthutha ukusuka ku-Intel® Arria® 10 ukuya ku-Intel® Stratix® 10 ye-10G Ethernet Subsystem
I-Low Latency (LL) Ethernet 10G (10GbE) Media Access Controller (MAC) Intel® FPGA IP core ihlanganisa i-Intel Stratix® 10 kanye ne-Intel Arria® 10 ye-design ex.amples ezihambisana nokucaciswa kwe-IEEE 802.3-2008. Izixhumanisi phakathi kwe-Intel Stratix 10 LL 10GbE MAC Intel FPGA IP core nesixhumi esibonakalayo (PHY) IP core zihlukile uma ziqhathaniswa ne-Intel Arria 10 LL 10GbE MAC Intel FPGA IP core ne-PHY IP core.
Le mihlahlandlela yokufuduka yenzelwe labo abajwayele i-Intel Arria 10 LL 10GbE MAC Intel FPGA IP core. Sebenzisa le mihlahlandlela yokufuduka uma ufuna ukuthutha idizayini yakho ye-Intel Arria 10 LL 10GbE MAC ukuze usebenzise amadivayisi we-Intel Stratix 10.
I-Intel Stratix 10 LL 10GbE MAC System

Ukuqhathaniswa phakathi kwe-Intel Stratix 10 ne-Intel Arria 10 Design Examples ye-LL 10GbE MAC Intel FPGA IP Core
| I-Design Example | Okuhlukile kwe-MAC | I-PHY | Ikhithi Yokuthuthukisa | I-Intel Arria 10 | I-Intel Stratix 10 |
| 10GBASE-R
I-Ethernet |
10G | I-PHY yomdabu (Ukusekela i-L/H-tile Native PHY ye-Intel Stratix 10) | I-Intel Arria 10/ Intel Stratix 10 GX Transceiver Signal Integrity | Yebo | Yebo |
| 1G/2.5G Ethernet nge-1588 | I-1G/2.5G | 1G/2.5G/5G/10G
Multi-rate Ethernet PHY |
I-Intel Arria 10/ Intel Stratix 10 GX Transceiver Signal Integrity | Yebo | Yebo |
| 1G/2.5G/10G
I-Ethernet |
1G/2.5G/10G | 1G/2.5G/5G/10G
Multi-rate Ethernet PHY |
I-Intel Arria 10/ Intel Stratix 10 GX Transceiver Signal Integrity | Yebo | Yebo |
| 10GBASE-R
Bhalisa Imodi ye-Ethernet |
10G | I-PHY yomdabu | Intel Arria 10 GX Transceiver Signal Ubuqotho | Yebo | Akutholakali |
| I-XAUI Ethernet | 10G | XAUI PHY | I-Intel Arria 10 GX FPGA | Yebo | Akutholakali |
| 1G/10G Ethernet | I-1G/10G | I-1G/10GbE kanye ne-10GBASE-KR PHY | Intel Arria 10 GX Transceiver Signal Ubuqotho | Yebo | Akutholakali |
| waqhubeka. | |||||
Inkampani ye-Intel Wonke Amalungelo Agodliwe. I-Intel, ilogo ye-Intel, nezinye izimpawu ze-Intel yizimpawu zokuthengisa ze-Intel Corporation noma izinkampani ezingaphansi kwayo. I-Intel iqinisekisa ukusebenza kwe-FPGA yayo kanye nemikhiqizo ye-semiconductor ezicacisweni zamanje ngokuhambisana newaranti evamile ye-Intel kodwa igodla ilungelo lokwenza izinguquko kunoma imiphi imikhiqizo namasevisi nganoma yisiphi isikhathi ngaphandle kwesaziso. I-Intel ayithathi mthwalo noma isikweletu esivele ngenxa yesicelo noma ukusetshenziswa kwanoma yiluphi ulwazi, umkhiqizo, noma isevisi echazwe lapha ngaphandle kwalapho okuvunyelwene ngakho ngokubhaliwe yi-Intel. Amakhasimende e-Intel ayelulekwa ukuthi athole inguqulo yakamuva yokucaciswa kwedivayisi ngaphambi kokuthembela kunoma yiluphi ulwazi olushicilelwe nangaphambi kokufaka ama-oda emikhiqizo noma amasevisi.
Amanye amagama namabhrendi angafunwa njengempahla yabanye.
| I-Design Example | Okuhlukile kwe-MAC | I-PHY | Ikhithi Yokuthuthukisa | I-Intel Arria 10 | I-Intel Stratix 10 |
| 1G/10G Ethernet nge-1588 | I-1G/10G | I-1G/10GbE kanye ne-10GBASE-KR PHY | Intel Arria 10 GX Transceiver Signal Ubuqotho | Yebo | Akutholakali |
| 10M/
100M/1G/10G I-Ethernet |
10M/
100M/1G/10G |
I-1G/10GbE kanye ne-10GBASE-KR PHY | Intel Arria 10 GX Transceiver Signal Ubuqotho | Yebo | Akutholakali |
| 10M/
100M/1G/10G I-Ethernet nge-1588 |
10M/
100M/1G/10G |
I-1G/10GbE kanye ne-10GBASE-KR PHY | Intel Arria 10 GX Transceiver Signal Ubuqotho | Yebo | Akutholakali |
| 1G/2.5G Ethernet | I-1G/2.5G | 1G/2.5G/5G/10G
Multi-rate Ethernet PHY |
Intel Arria 10 GX Transceiver Signal Ubuqotho | Yebo | Akutholakali |
| 10G USXGMII
I-Ethernet |
1G/2.5G/5G/10G (USXGMII) | 1G/2.5G/5G/10G
Multi-rate Ethernet PHY |
Intel Arria 10 GX Transceiver Signal Ubuqotho | Yebo | Akutholakali |
Qaphela:
Ungakwazi ukufinyelela i-ex yedizayini esohlwiniampkancane ngomhleli wepharamitha we-LL 10GbE MAC kusofthiwe ye-Intel Quartus® Prime Pro Edition.
Ulwazi Oluhlobene
- I-Low Latency Ethernet 10G MAC User Guide
- I-Intel Stratix 10 Low Latency Ethernet 10G MAC Design Example Umhlahlandlela Womsebenzisi
- I-Intel Stratix 10 L- kanye ne-H-Tile Transceiver PHY Umhlahlandlela Womsebenzisi
Ukucushwa okusekelwe kwe-Intel Stratix 10 kanye ne-Intel Arria 10 LL 10GbE MAC Designs
Ithebula elilandelayo libala konke ukulungiselelwa kwe-Intel Stratix 10 kanye ne-Intel Arria 10 Ethernet IP.
Ukucushwa okusekelwe kwe-Intel Arria 10 ne-Intel Stratix 10 Ethernet IP Configuration
| IP Core | I-Intel Arria 10 | I-Intel Stratix 10 | |
| I-LL 10GbE MAC | Isivinini | • 10G | |
| • 1G/10G | |||
| • 10M/100M/1G/10G | |||
| • 1G/2.5G | |||
| • 1G/2.5G/10G | |||
| • 1G/2.5G/5G/10G (USXGMII interface) | |||
| • 10M/100M/1G/2.5G | |||
| • 10M/100M/1G/2.5G/10G | |||
| I-IEEE 1588v2 isici | • 10G | • 10G | |
| • 1G/10G | • 1G/10G | ||
| • 10M/100M/1G/10G | • 10M/100M/1G/10G | ||
| • 1G/2.5G | • 1G/2.5G | ||
| • 1G/2.5G/10G | |||
| waqhubeka. | |||
| IP Core | I-Intel Arria 10 | I-Intel Stratix 10 | |
| 1G/2.5G/5G/10G Multi-rate Ethernet PHY | Isivinini | • 2.5G
• 1G/2.5G • 1G/2.5G/10G (MGBASE-T PHY) • 1G/2.5G/5G/10G (USXGMII interface/NBASE-T PHY) |
|
| I-IEEE 1588v2 isici | • 2.5G
• 1G/2.5G |
• 2.5G
• 1G/2.5G • 1G/2.5G/10G Ayisekelwe kumodi ye-SGMII enikwe amandla. |
|
| Imodi ye-SGMII | Akutholakali | • 1G/2.5G
• 1G/2.5G/10G |
|
| XAUI PHY | Iyatholakala | Akutholakali | |
| I-Intel Stratix 10 L-tile/H-tile Transceiver Native PHY | Akutholakali | Ukusetha ngaphambilini okusekelwe:
• 10GBASE-R • 10GBASE-R 1588 • 10GBASE-R Ukubambezeleka Okuphansi • 10GBASE-R nge-KR FEC |
|
| I-Intel Arria 10 Transceiver Native PHY | Ukusetha ngaphambilini okusekelwe:
• 10GBASE-R • 10GBASE-R Imodi Yokubhalisa • 10GBASE-R Ukubambezeleka Okuphansi • 10GBASE-R nge-KR FEC |
Akutholakali | |
| I-Intel Arria 10 1G/10GbE kanye ne-10GBASE-KR PHY | Iyatholakala | Akutholakali | |
| I-Intel Stratix 10 10GBASE-KR PHY | Akutholakali | Iyatholakala | |
Ukuvala iwashi nokusetha kabusha Ingqalasizinda
I-Intel Stratix 10 LL 10GbE MAC kanye ne-Intel Stratix 10 Transceiver Native PHY IP Cores
Ungakwazi ukulungisa i-Intel Stratix 10 Transceiver Native PHY IP core ukuze usebenzise i-10GBASE-R PHY ngezandlalelo ezibonakalayo eziqondene ne-Ethernet ezisebenza ku-10.3125 Gbps izinga ledatha njengoba lichazwe Kusigaba 49 sokucaciswa kwe-IEEE 802.3-2008. Lokhu kulungiselelwa kunikeza i-XGMII kuya ku-LL 10GbE MAC Intel FPGA IP core futhi kusebenzisa isiteshi esisodwa esingu-10.3125Gbps PHY ukuze kuxhunywe ngokuqondile kumojula encane ye-form-factor pluggable plus (SFP+) esebenzisa isixhumi esibonakalayo esincane sikagesi (i-SFI) ukucaciswa.
Isibalo esilandelayo sibonisa ukufuduka kusuka kumklamo we-Intel Arria 10 kuya kumklamo we-Intel Stratix 10.
Isikimu Sokuvala Nokusetha Kabusha se-LL 10GbE MAC kanye ne-Intel Stratix 10 Transceiver Native PHY ku-10GBASE-R Design Example Interface
Ulwazi Oluhlobene
I-AN795: Ukusebenzisa Iziqondiso ze-10G Ethernet Subsystem Ukusebenzisa I-Low Latency 10G MAC IP Core kumadivayisi we-Arria 10
I-Intel Stratix 10 LL 10GbE MAC ne-Intel Stratix 10 1G/2.5G/5G/10G Multi-rate Ethernet PHY Intel FPGA IP Cores
I-1G/2.5G/5G/10G Multi-rate Ethernet PHY Intel FPGA IP core yamadivayisi we-Intel Stratix 10 inikeza i-GMII ne-XGMII ku-LL 10GbE MAC Intel FPGA IP core. I-1G/ 2.5G/5G/10G Multi-rate Ethernet PHY IP core isebenzisa isiteshi esisodwa esingu-1G/ 2.5G/5G/10Gbps serial PHY. Idizayini ihlinzeka ngoxhumano oluqondile kumamojula axhumekeka we-SFP+ amabili esivinini se-1G/2.5GbE, amadivayisi we-PHY wethusi angaphandle we-MGBASE-T, noma izixhumanisi ze-chip-to-chip. Lawa ma-IP cores asekela amanani edatha angalungiseka kabusha.
Isibalo esilandelayo sibonisa ukufuduka kusuka kumklamo we-Intel Arria 10 kuya kumklamo we-Intel Stratix 10.
Isikimu Sokuvala Nokusetha Kabusha se-LL 10GbE MAC kanye ne-1G/2.5G/5G/10G Multi-rate Ethernet PHY Design Example (Imodi ye-1G/2.5G/10G) ye-Intel Stratix 10 Devies

Isibalo esilandelayo sibonisa uhlelo lwakamuva lwewashi nokusetha kabusha kwe-1G/2.5G Ethernet nge-IEEE 1588v2 isici somklamo example iqondiswe kumadivayisi we-Intel Stratix 10. Kunomehluko phakathi kwalesi sixazululo kanye nenguqulo eyethulwa kumadivayisi we-Intel Arria 10. Ukuguqulwa kuyadingeka lapho uthutha umklamo usuka kumadivayisi we-Intel Arria 10 uye kumadivayisi we-Intel Stratix 10.
Isikimu Sokuvala Nokusetha Kabusha se-LL 10GbE MAC kanye ne-1G/2.5G/5G/10G Multi-rate Ethernet PHY Design Example (Imodi ye-1G/2.5G enesici se-IEEE 1588v2) yamadivayisi we-Intel Stratix 10

Imbobo yewashi yokufaka entsha i-latency_sclk iyatholakala kumadivayisi we-Intel Stratix 10. Le mbobo iyatholakala uma uvula ipharamitha yokunika amandla izimbobo zokulinganisa ukubambezeleka kumgogodla we-Intel Stratix 10 L/H-Tile Transceiver Native PHY IP noma ipharamitha ye-Enable IEEE 1588 Precision Time Protocol ku-1G/2.5G/5G/10G Multi- isilinganiso Ethernet PHY Intel FPGA IP core. Le port iyadingeka kumodeli yokulinganisa ukubambezeleka kwe-deterministic yamadivayisi we-Intel Stratix 10. Ukuze uthole ulwazi olwengeziwe, bheka isahluko se-Deterministic Latency Use Model ku-Intel Stratix 10 L/H-Tile Transceiver PHY Umhlahlandlela Womsebenzisi.
Ukuze uxhume iluphu ye-I/O phase-locked (IOPLL), engeza i-Intel Stratix 10 Clock Control (stratix10_clkctrl) IP kusukela kukhathalogi ye-IP. I-IOPLL inikeza amasekhondi amabiliampamawashi e-ling kulo mklamo: 53.33 MHz kumodi engu-2.5G kanye no-80 MHz kumodi engu-1G.
Isibalo esilandelayo sibonisa imininingwane yokuxhumana esekelwe kumklamo we-Ethernet we-1G/2.5G.
Umdwebo Wokuxhumana we-1G/2.5G Ethernet one-1588 Design ye-Intel Stratix 10 Devices

Kufanele uqinisekise ukuthi imbobo ye-inclk0x ixhumeka ku-2.5G sampiwashi le-ling kanye nembobo ye-inclk1x ixhuma ku-1G sampiwashi. Imbobo yewashi lokukhiphayo lokulawula iwashi iba imbobo ye-latency_sclk. Ngokuhamba komklamo kusuka kumadivayisi we-Intel Arria 10 kuya kumadivayisi we-Intel Stratix 10, ungasebenzisa kabusha ukuxhumana okufanayo phakathi kwebhulokhi yokumisa kabusha i-1G/2.5G nesilawuli sokusetha kabusha i-transceiver.
Ulwazi Oluhlobene
- I-Intel Stratix 10 L- kanye ne-H-Tile Transceiver PHY Umhlahlandlela Womsebenzisi
- I-AN795: Ukusebenzisa Imihlahlandlela ye-10G Ethernet Subsystem Ukusebenzisa I-Low Latency 10G MAC IP Core kumadivayisi we-Arria 10
- I-Intel Stratix 10 Clocking kanye ne-PLL User Guide
IP Register Mapping
I-LL 10GbE MAC Intel FPGA IP core yamadivayisi we-Intel Stratix 10 isebenzisa imephu yokubhalisa efanayo ne-LL 10GbE MAC Intel FPGA IP core yamadivayisi we-Intel Arria 10. I-Multi-rate Ethernet PHY kanye ne-10GBASE-R PHY yokusetha ngaphambilini iphinde isebenzise imephu yokubhalisa efanayo kuyo yomibili imiklamo ye-Intel Stratix 10 ne-Intel Arria 10. I-LL 10GbE MAC Intel FPGA IP core yamadivayisi we-Intel Stratix 10 isasekela ukuhambisana kwasemuva ne-10GbE IP ene-adaptha ye-Avalon Memory-Mapped (MM) engu-64-bit.
Ulwazi Oluhlobene
I-Low Latency Ethernet 10G MAC User Guide.
Umehluko Wokuxhumana Kwesiginali phakathi kwe-Intel Stratix 10 ne-Intel Arria 10 Ethernet Design ExampLes
Ku-LL 10GbE MAC Intel FPGA IP core, azikho izimpawu ezintsha ezethulwe amadivayisi we-Intel Stratix 10. Kukhona amasiginali amasha wesimo sokusetha kabusha asynchronous ethulwe ku-Intel Stratix 10 L/H-Tile Transceiver Native PHY IP Core. Umehluko usebenza kuwo wonke ama-Ethernet PHY IP cores, ahlanganisa zonke izinhlobo ze-1G/2.5G/5G/10G Multi-rate Ethernet PHY Intel FPGA IP cores kanye ne-10GBASE-R PHY Intel FPGA IP core.
Umehluko Wesiginali Yokuxhumana Phakathi Kwe-Intel Stratix 10 L/H-Tile Transceiver Native PHY/Isilinganiso esiningi se-Ethernet PHY kanye ne-Intel Arria 10 Transceiver Native PHY/Isilinganiso esiningi se-Ethernet PHY
Qaphela: = Inani lemizila.
| Intel Stratix 10 Interface Signals | Intel Arria 10 Interface Signals | Amazwana |
| tx_analogreset_stat[ -1
:0] |
Akutholakali | Lezi zimbobo zesimo sokusetha kabusha zisanda kwethulwa kumadivayisi we-Intel Stratix 10 kuphela.
Xhuma kusignali ehambisanayo ku-Transceiver PHY Setha Kabusha Isilawuli IP core, esebenzisa ukulandelana kokusetha kabusha okufanelekile kwedivayisi. |
| rx_analogreset_stat[ -1
:0] |
Akutholakali | |
| tx_digitalreset_stat[ - 1:0] | Akutholakali | |
| rx_digitalreset_stat[ - 1:0] | Akutholakali | |
| i-latency_sclk | Akutholakali | Iwashi lereferensi lokulinganisa ukubambezeleka. SampLing iwashi lokulinganisa ukubambezeleka kwebhulokhi yohlelo lokusebenza lwe-transceiver (AIB) idathapath.
Leli chweba liyatholakala uma inketho yamachweba wokulinganisa ukubambezeleka ku-Intel Stratix 10 L/H-Tile Transceiver Native PHY IP core noma inketho ye-IEEE 1588 Precision Time Protocol ku-1G/ 2.5G/5G/10G Multi-rate Ethernet PHY Intel FPGA I-IP core inikwe amandla. |
| reconfig_address [log2
+10:0] |
reconfig_address [log2+9:0] | Isignali yekheli yokumisa kabusha exhunywe kubhulokhi yokumisa kabusha. Ibhasi lekheli ebelivame ukucacisa ikheli okufanele lifinyelelwe kukho kokubili imisebenzi yokufunda nokubhala. |
Umehluko Wesiginali Yokuxhumana Phakathi Kwe-Intel Stratix 10 Transceiver Setha Kabusha Isilawuli IP kanye ne-Intel Arria 10 Transceiver Setha Kabusha Isilawuli Se-IP
Qaphela: = Inani lemizila.
| Intel Stratix 10 Interface Signals | Intel Arria 10 Interface Signals | Amazwana |
| tx_analogreset_stat[ -1
:0] |
Akutholakali | Lena isignali yesimo sokusetha kabusha evela ku-Transceiver Native PHY IP Core. Kune-tx_analogreset_stat eyodwa ngesiteshi ngasinye.
Uma kugonyelwa, setha kabusha ukulandelana kwe-TX PMA kuyaqala. Uma kucolile, setha kabusha ukulandelana kwe-TX PMA iphela. |
| rx_analogreset_stat[ -1
:0] |
Akutholakali | Lena isignali yesimo sokusetha kabusha evela ku-Transceiver Native PHY IP Core. Kune-rx_analogreset_stat eyodwa ngesiteshi ngasinye.
Uma kugonyelwa, setha kabusha ukulandelana kwe-RX PMA kuyaqala. Uma kukhishwe, setha kabusha ukulandelana kwe-RX PMA iphela. |
| tx_digitalreset_stat[ - 1:0] | Akutholakali | Lena isignali yesimo sokusetha kabusha evela ku-Transceiver Native PHY IP Core. Kune-tx_digitalreset_stat eyodwa ngesiteshi ngasinye. Uma kugonyelwa, setha kabusha ukulandelana kwe-TX PCS kuyaqala. |
| waqhubeka. | ||
| Intel Stratix 10 Interface Signals | Intel Arria 10 Interface Signals | Amazwana |
| Uma kukhishwe, setha kabusha ukulandelana kwe-TX PCS iphela. | ||
| rx_digitalreset_stat[ - 1:0] | Akutholakali | Lena isignali yesimo sokusetha kabusha evela ku-Transceiver Native PHY IP Core. Kukhona i-rx_digitalreset_stat eyodwa ngesiteshi ngasinye.
Uma kugonyelwa, ukusetha kabusha ukulandelana kwe-RX PCS kuyaqala. Uma kukhishwa, setha kabusha ukulandelana kwe-RX PCS iphela. |
Isibalo esilandelayo sibonisa ukuxhunyaniswa kwezimpawu zesimo sokusetha kabusha kwe-Intel Stratix 10 Ethernet 10G subsystem design. Lokhu kuyasebenza uma usebenzisa i-Intel Stratix 10 L-tile/H-tile Native PHY IP core noma i-1G/2.5G/5G/10G Multi-rate PHY Intel FPGA IP core.
Setha Kabusha Umdwebo Wezimpawu Zesimo Se-Intel Stratix 10 PHY IP Core futhi Setha Kabusha Isilawuli IP Core

Kukhona izinguquko ezithile kumasiginali we-ATX PLL kanye ne-fPLL yamadivayisi we-Intel Stratix 10 uma kuqhathaniswa namadivayisi we-Intel Arria 10. Uma uthutha imiklamo ye-Ethernet usuka kudivayisi ye-Intel Arria 10 uya kudivayisi ye-Intel Stratix 10, susa amasiginali wokusetha kabusha we-mcgb_rst kanye ne-pll_powerdown ngoba awatholakali ku-Intel Stratix 10.
Isibalo esilandelayo sibonisa umehluko phakathi kwe-Intel Stratix 10 L-Tile/H-Tile ATX PLL ne-Intel Arria 10 ATX PLL.
Ukuqhathaniswa phakathi kwe-Interface Signals ye-Intel Stratix 10 L-Tile/H-Tile Transceiver ATX PLL kanye ne-Intel Arria 10 Transceiver ATX PLL

Olunye ushintsho ku-Intel Stratix 10 L-Tile/H-Tile Transceiver PHY ibhithi eyengeziwe engu-1 eyengeziwe ebhasini le-reconfig_address, uma kuqhathaniswa nenguqulo ye-Intel Arria 10 Transceiver PHY. Ushintsho olufanayo luyadingeka ku-Multi-rate PHY njengoba idalwe ngokusebenzisa i-PHY yomdabu njengesisekelo.
Umfanekiso olandelayo ubonisa indlela yokuxhuma i-reconfig_address.
Vimba Umdwebo Wokuxhumanisa Ikheli Lokuhlela Kabusha we-Intel Stratix 10 Ethernet Subsystem Design
I-example ebonisiwe isekelwe ku-Ethernet design example imodeli. Kumabhulokhi akhiqizwa Umklami Wenkundla, ungathola amamojula ku-ex designample files.
Ulwazi Oluhlobene
- I-Intel Stratix 10 Low Latency Ethernet 10G MAC Design Example Umhlahlandlela Womsebenzisi
- I-Intel Stratix 10 L- kanye ne-H-Tile Transceiver PHY Umhlahlandlela Womsebenzisi
- I-Intel Stratix 10 Clocking kanye ne-PLL User Guide
Ukufuduka Ukugeleza
Isoftware ye-Intel Quartus Prime Pro Edition kuphela enikeza imiklamo ye-Intel Stratix 10. Uma usebenzisa idizayini ye-Intel Arria 10 Ethernet evela ku-Intel Quartus Prime Standard Edition, udinga ukuthuthela enguqulweni ye-Intel Quartus Prime Pro Edition yanoma iyiphi idizayini ye-Intel Stratix 10.
Ulwazi Oluhlobene
I-Intel Quartus Prime Pro Edition Handbook Volume 1: Idizayini kanye Nokuhlanganiswa
- Ihlinzeka ngolwazi olwengeziwe mayelana nokuthuthukisa ama-IP cores kanye nezinhlelo ze-Qsys Pro kusofthiwe ye-Quartus Prime Pro Edition.
Umlando Wokubuyekezwa Kwedokhumenti we-AN 808
Imihlahlandlela Yokufuduka isuka ku-Intel Arria 10 iye ku-Intel Stratix 10 ye-10G Ethernet Subsystem
| Inguqulo Yedokhumenti | Izinguquko |
| 2019.11.20 | • Iqanjwe kabusha njenge-Intel.
• Umfanekiso Obuyekeziwe: Uhlelo Lokuvala Nokusetha Kabusha lwe-LL 10GbE MAC kanye ne-1G/2.5G/5G/10G Multi-rate Ethernet PHY Design Example (Imodi ye-1G/2.5G enesici se-IEEE 1588v2) yamadivayisi we-Intel Stratix 10. • Wenze izibuyekezo zokuhlela kuyo yonke idokhumenti. |
| Usuku | Inguqulo | Izinguquko |
| Juni 2017 | 2017.06.19 | Ukukhishwa kokuqala. |
I-AN 808: Izinkombandlela Zokuthutha ukusuka ku-Intel® Arria® 10 ukuya ku-Intel® Stratix® 10 ye-10G Ethernet Subsystem.
Amadokhumenti / Izinsiza
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I-intel Migration Guidelines ukusuka ku-Arria 10 kuya ku-Stratix 10 ye-10G Ethernet Subsystem [pdf] Umhlahlandlela Womsebenzisi Imihlahlandlela Yokufuduka kusuka ku-Arria 10 kuya ku-Stratix 10 ye-10G Ethernet Subsystem, Iziqondiso Zokufuduka, Iziqondiso Zokufuduka kwe-Arria 10, Iziqondiso Zokufuduka ze-Stratix 10, I-10G Ethernet Subsystem Migration Guidelines |





